sim/riscv: fix multiply instructions on simulator

After this commit:

  commit 0938b032daa52129b4215d8e0eedb6c9804f5280
  Date:   Wed Feb 2 10:06:15 2022 +0900

      RISC-V: Add 'Zmmul' extension in assembler.

some instructions in the RISC-V simulator stopped working as a new
instruction class 'INSN_CLASS_ZMMUL' was added, and some existing
instructions were moved into this class.

The simulator doesn't currently handle this instruction class, and so
the instructions will now cause an illegal instruction trap.

This commit adds support for INSN_CLASS_ZMMUL, and adds a test that
ensures the affected instructions can be executed by the simulator.

Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
Reviewed-by: Andrew Burgess <aburgess@redhat.com>

diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index 30d2f1e1c9a9db2857f36c49ebcea32d2883082e..0156f791d4b91fff57c4697d865ba91ae7c95a3a 100644 (file)
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -936,6 +936,7 @@ execute_one (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
     case INSN_CLASS_I:
       return execute_i (cpu, iw, op);
     case INSN_CLASS_M:
+    case INSN_CLASS_ZMMUL:
       return execute_m (cpu, iw, op);
     default:
       TRACE_INSN (cpu, "UNHANDLED EXTENSION: %d", op->insn_class);

diff --git a/sim/testsuite/riscv/m-ext.s b/sim/testsuite/riscv/m-ext.s
new file mode 100644 (file)
index 0000000..b80bd14
--- /dev/null
+++ b/sim/testsuite/riscv/m-ext.s
@@ -0,0 +1,18 @@
+# Check that the RV32M instructions run without any faults.
+# mach: riscv
+
+.include "testutils.inc"
+
+       start
+
+       .option arch, +m
+       mul     x0, x1, x2
+       mulh    x0, x1, x2
+       mulhu   x0, x1, x2
+       mulhsu  x0, x1, x2
+       div     x0, x1, x2
+       divu    x0, x1, x2
+       rem     x0, x1, x2
+       remu    x0, x1, x2
+
+       pass