(no commit message)

diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn
index 3e34f0212bc73024c3f12638bb47c901e2139628..de6ef8824ebf76acf2a2d736a49c8b6c7814ae07 100644 (file)
--- a/openpower/sv.mdwn
+++ b/openpower/sv.mdwn
@@ -340,7 +340,8 @@ v3.1 EXT01 usage, and because SVP64 is already 64-bit Prefixed,
 Prefixed-Prefixed-instructions (SVP64 Prefixed v3.1 Prefixed)
 would become a whopping 96-bit long instruction. Avoiding this
 situation is a high priority which in turn by necessity puts pressure
-on the 32-bit Major Opcode space.
+on the 32-bit Major Opcode space.  Alternative locations for SVP64
+Prefixing include EXT006 and EXT017, with EXT006 being most favourable.
 
 SVP64 itself is already under pressure, being only 24 bits.  If it is
 not permitted to take up 25% of EXT001 then it would have to be proposed
@@ -356,7 +357,7 @@ available for "Custom non-approved purposes" according to the Power
 ISA Spec,
 is under severe design pressure as it is insufficient to hold
 the full extent of the instruction additions required to create
-a Hybrid 3D CPU-VPU-GPU.  Akthough the wording of the Power ISA
+a Hybrid 3D CPU-VPU-GPU.  Although the wording of the Power ISA
 Specification leaves open the *possibility* of not needing to
 propose ISA Extensions to the ISA WG, it is clear that EXT022
 is an inappropriate location for a large high-profile Extension