reorg

diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex
index 8cec8922e9c877d6a9922d40fce87bb2f7494817..09019e99231641e898cb1a642f0f2277fbf2701a 100644 (file)
--- a/simple_v_extension/simple_v_chennai_2018.tex
+++ b/simple_v_extension/simple_v_chennai_2018.tex
@@ -720,7 +720,7 @@ loop:
    \item An extra pipeline phase almost certainly essential\\
          for fast low-latency implementations\vspace{4pt}
    \item With zeroing off, skipping non-predicated elements is hard:\\
-         it is however an optimisation (and could be skipped).\vspace{4pt}
+         it is however an optimisation (and need not be done).\vspace{4pt}
    \item Setting up the Register/Predication tables (interpreting the\\
             CSR key-value stores) might be a bit complex to optimise
             (any change to a CSR key-value entry needs to redo the table)