verilog: fix leaking of type names in parser

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 7d750ea28dea16788e8c3b26a95c398d3bfed2f2..1a76d0dea0b5b44b689a1ba5e1116c20cf0d6e4e 100644 (file)
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -692,6 +692,7 @@ wire_type_token:
                astbuf3->is_custom_type = true;
                astbuf3->children.push_back(new AstNode(AST_WIRETYPE));
                astbuf3->children.back()->str = *$1;
+               delete $1;
        } |
        TOK_WOR {
                astbuf3->is_wor = true;
@@ -1458,6 +1459,7 @@ param_type:
                astbuf1->is_custom_type = true;
                astbuf1->children.push_back(new AstNode(AST_WIRETYPE));
                astbuf1->children.back()->str = *$1;
+               delete $1;
        };
 
 param_decl: