re PR target/64393 (ICE: in extract_insn, at recog.c:2327 (unrecognizable insn) with...

PR target/64393

gcc/
	* common/config/i386/i386-common.c (OPTION_MASK_ISA_AVX512VBMI_SET):
	Enable AVX512BW.
	(OPTION_MASK_ISA_AVX512BW_UNSET): Disable AVX512VBMI.
	* config/i386/i386.c (ix86_hard_regno_mode_ok): Don't check
	AVX512VBMI, as it implies AVX512BW.

testsuite/

	* gcc.target/i386/pr64393.c: New test.

From-SVN: r219599

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index d9ecac1a3e5e36962857988ed6f831ae2a1ee2c7..90414774303ac40e0395a749211e4939296b33ac 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,12 @@
+2014-01-14  Ilya Tocar  <ilya.tocar@intel.com>
+
+       PR target/64393
+       * common/config/i386/i386-common.c (OPTION_MASK_ISA_AVX512VBMI_SET):
+       Enable AVX512BW.
+       (OPTION_MASK_ISA_AVX512BW_UNSET): Disable AVX512VBMI.
+       * config/i386/i386.c (ix86_hard_regno_mode_ok): Don't check
+       AVX512VBMI, as it implies AVX512BW.
+
 2014-01-14  Ilya Tocar  <ilya.tocar@intel.com>
 
        PR target/64387

diff --git a/gcc/common/config/i386/i386-common.c b/gcc/common/config/i386/i386-common.c
index 77edb479b7711b1740344d41c1ebc808213d345a..4e5687ae5ab15ab4a558e1a63ff046ff14a9e088 100644 (file)
--- a/gcc/common/config/i386/i386-common.c
+++ b/gcc/common/config/i386/i386-common.c
@@ -74,7 +74,7 @@ along with GCC; see the file COPYING3.  If not see
 #define OPTION_MASK_ISA_AVX512IFMA_SET \
   (OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512F_SET)
 #define OPTION_MASK_ISA_AVX512VBMI_SET \
-  (OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512F_SET)
+  (OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512BW_SET)
 #define OPTION_MASK_ISA_RTM_SET OPTION_MASK_ISA_RTM
 #define OPTION_MASK_ISA_PRFCHW_SET OPTION_MASK_ISA_PRFCHW
 #define OPTION_MASK_ISA_RDSEED_SET OPTION_MASK_ISA_RDSEED
@@ -171,7 +171,8 @@ along with GCC; see the file COPYING3.  If not see
 #define OPTION_MASK_ISA_AVX512PF_UNSET OPTION_MASK_ISA_AVX512PF
 #define OPTION_MASK_ISA_AVX512ER_UNSET OPTION_MASK_ISA_AVX512ER
 #define OPTION_MASK_ISA_AVX512DQ_UNSET OPTION_MASK_ISA_AVX512DQ
-#define OPTION_MASK_ISA_AVX512BW_UNSET OPTION_MASK_ISA_AVX512BW
+#define OPTION_MASK_ISA_AVX512BW_UNSET \
+  (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VBMI_UNSET)
 #define OPTION_MASK_ISA_AVX512VL_UNSET OPTION_MASK_ISA_AVX512VL
 #define OPTION_MASK_ISA_AVX512IFMA_UNSET OPTION_MASK_ISA_AVX512IFMA
 #define OPTION_MASK_ISA_AVX512VBMI_UNSET OPTION_MASK_ISA_AVX512VBMI

diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 7a39f800d899df257ee56cd4f6fa6b5f7a361582..91eae5ae3b5830a09f6a9632c38d62e0b5ba83f8 100644 (file)
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -41669,7 +41669,7 @@ ix86_hard_regno_mode_ok (int regno, machine_mode mode)
     return VALID_FP_MODE_P (mode);
   if (MASK_REGNO_P (regno))
     return (VALID_MASK_REG_MODE (mode)
-           || ((TARGET_AVX512BW || TARGET_AVX512VBMI)
+           || (TARGET_AVX512BW
                && VALID_MASK_AVX512BW_MODE (mode)));
   if (BND_REGNO_P (regno))
     return VALID_BND_REG_MODE (mode);

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 8febe145a9225ee7ccd456876c3717b30a46eecb..12afaed3d82e91a664a5cd9883f40c91311cf1f8 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2014-01-14  Ilya Tocar  <ilya.tocar@intel.com>
+
+       PR target/64393
+       * gcc.target/i386/pr64393.c: New test.
+
 2014-01-14  Ilya Tocar  <ilya.tocar@intel.com>
 
        PR target/64387

diff --git a/gcc/testsuite/gcc.target/i386/pr64393.c b/gcc/testsuite/gcc.target/i386/pr64393.c
new file mode 100644 (file)
index 0000000..37a0e48
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr64393.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mavx512vbmi" } */
+
+int a[1024];
+
+void
+foo (int i)
+{
+  for (;; i++)
+    if (a[i] != (i ^ (i * 3) ^ (i * 7)))
+      return;
+}