{
struct si_vertex_element *velems = sctx->vertex_elements;
struct si_descriptors *desc = &sctx->vertex_buffers;
- bool bound[SI_NUM_VERTEX_BUFFERS] = {};
unsigned i, count = velems->count;
uint64_t va;
uint32_t *ptr;
return true;
unsigned fix_size3 = velems->fix_size3;
+ unsigned first_vb_use_mask = velems->first_vb_use_mask;
/* Vertex buffer descriptors are the only ones which are uploaded
* directly through a staging buffer and don't go through
struct pipe_vertex_buffer *vb;
struct r600_resource *rbuffer;
unsigned offset;
+ unsigned vbo_index = ve->vertex_buffer_index;
uint32_t *desc = &ptr[i*4];
- vb = &sctx->vertex_buffer[ve->vertex_buffer_index];
+ vb = &sctx->vertex_buffer[vbo_index];
rbuffer = (struct r600_resource*)vb->buffer;
if (!rbuffer) {
memset(desc, 0, 16);
desc[3] = velems->rsrc_word3[i];
- if (!bound[ve->vertex_buffer_index]) {
+ if (first_vb_use_mask & (1 << i)) {
radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
(struct r600_resource*)vb->buffer,
RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER);
- bound[ve->vertex_buffer_index] = true;
}
}
const struct pipe_vertex_element *elements)
{
struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
+ bool used[SI_NUM_VERTEX_BUFFERS] = {};
int i;
assert(count <= SI_MAX_ATTRIBS);
return NULL;
}
+ if (!used[vbo_index]) {
+ v->first_vb_use_mask |= 1 << i;
+ used[vbo_index] = true;
+ }
+
desc = util_format_description(elements[i].src_format);
first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);