rename madded->maddedu for consistency with PowerISA maddhdu instruction

diff --git a/openpower/isa/svfixedarith.mdwn b/openpower/isa/svfixedarith.mdwn
index a799236446a7943f551e776a6c293d0756a7f0a7..bb9ffc6e35e9bace3721521ff23a93ded18b49ce 100644 (file)
--- a/openpower/isa/svfixedarith.mdwn
+++ b/openpower/isa/svfixedarith.mdwn
@@ -2,7 +2,7 @@
 
 VA-Form
 
-* madded RT,RA,RB,RC
+* maddedu RT,RA,RB,RC
 
 Pseudo-code:
 

diff --git a/openpower/isatables/RM-1P-3S1D.csv b/openpower/isatables/RM-1P-3S1D.csv
index e3e59de1d67a8330852a2636efd7262fd16934b0..6a2990c12a8fe034d225f2aba464c0fd2c303574 100644 (file)
--- a/openpower/isatables/RM-1P-3S1D.csv
+++ b/openpower/isatables/RM-1P-3S1D.csv
@@ -33,7 +33,7 @@ isel,NORMAL,,1P,EXTRA2,NO,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
 isel,NORMAL,,1P,EXTRA2,NO,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
 maddhd,NORMAL,,1P,EXTRA2,NO,d:RT,s:RA,s:RB,s:RC,RA,RB,RC,RT,0,0,0
 maddhdu,NORMAL,,1P,EXTRA2,NO,d:RT,s:RA,s:RB,s:RC,RA,RB,RC,RT,0,0,0
-madded,NORMAL,,1P,EXTRA2,NO,d:RT,s:RA,s:RB,s:RC,RA,RB,RC,RT,0,0,0
+maddedu,NORMAL,,1P,EXTRA2,NO,d:RT,s:RA,s:RB,s:RC,RA,RB,RC,RT,0,0,0
 maddld,NORMAL,,1P,EXTRA2,NO,d:RT,s:RA,s:RB,s:RC,RA,RB,RC,RT,0,0,0
 divmod2du,NORMAL,,1P,EXTRA2,NO,d:RT,s:RA,s:RB,s:RC,RA,RB,RC,RT,0,0,0
 absdacs,NORMAL,,1P,EXTRA2,NO,d:RT;d:CR0,s:RA,s:RB,s:RT,RA,RB,RT,RT,0,CR0,0

diff --git a/openpower/isatables/minor_4.csv b/openpower/isatables/minor_4.csv
index 57fd539699c94687fa9333cf4007126ded450d7c..d0f3f962197ec8c762dcf295e0653167e6851ae7 100644 (file)
--- a/openpower/isatables/minor_4.csv
+++ b/openpower/isatables/minor_4.csv
@@ -3,7 +3,7 @@
 opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe,comment,form,CONDITIONS,unofficial,comment2
 48,ALU,OP_MADDHD,RA,RB,RC,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,maddhd,VA,,,
 49,ALU,OP_MADDHDU,RA,RB,RC,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,maddhdu,VA,,,
-50,ALU,OP_MADDED,RA,RB,RC,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,madded,VA,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+50,ALU,OP_MADDEDU,RA,RB,RC,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,maddedu,VA,,1,unofficial until submitted and approved/renumbered by the opf isa wg
 51,ALU,OP_MADDLD,RA,RB,RC,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,maddld,VA,,,
 52,ALU,OP_DIVMOD2DU,RA,RB,RC,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,divmod2du,VA,,1,unofficial until submitted and approved/renumbered by the opf isa wg
 56,ALU,OP_PCDEC,RA,RB,RC,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,ONE,0,0,pcdec,VA2,,1,unofficial until submitted and approved/renumbered by the opf isa wg

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index 34c776280b3e04b07f15f1dbabbea1e36424d9a3..a0bd9678244b99c37ac943a92a4f2ded7ddaf031 100644 (file)
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -1588,7 +1588,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop):
                        'svshape', 'svshape2',
                        'grev', 'ternlogi', 'bmask', 'cprop',
                        'absdu', 'absds', 'absdacs', 'absdacu', 'avgadd',
-                       'fmvis', 'fishmv', 'pcdec', "madded", "divmod2du",
+                       'fmvis', 'fishmv', 'pcdec', "maddedu", "divmod2du",
                        "dsld", "dsrd",
                        ]:
             illegal = False

diff --git a/src/openpower/decoder/power_decoder2.py b/src/openpower/decoder/power_decoder2.py
index 6d9e2a7a5f6d4f4ef97034cb12e7d4a7eebb3af2..dd0302c4c5d82d62e050094a13a37780512b9401 100644 (file)
--- a/src/openpower/decoder/power_decoder2.py
+++ b/src/openpower/decoder/power_decoder2.py
@@ -1037,7 +1037,7 @@ class PowerDecodeSubset(Elaboratable):
             comb += xo6.eq(self.dec.opcode_in[0:6])
             with m.If((major == 4) & xo6.matches(
                     '11100-',  # pcdec
-                    '110010',  # madded
+                    '110010',  # maddedu
                     '110100',  # divmod2du
                 )):
                 comb += self.implicit_rs.eq(1)

diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py
index 7eb310ff5c6f88e73812e832d7335be8dbe81f55..2eef375801e3aee0badac50711507da07c787506 100644 (file)
--- a/src/openpower/decoder/power_enums.py
+++ b/src/openpower/decoder/power_enums.py
@@ -541,7 +541,7 @@ _insns = [
     "lwz", "lwzcix", "lwzu", "lwzux", "lwzx",           # more load word
     # "lwabr",           # load word SVP64 bit-reversed
     # "lwzbr", "lwzubr", # more load word SVP64 bit-reversed
-    "madded",
+    "maddedu",
     "maddhd", "maddhdu", "maddld",                      # INT multiply-and-add
     "mcrf", "mcrxr", "mcrxrx", "mfcr/mfocrf",           # CR mvs
     "mfmsr", "mfspr",
@@ -698,7 +698,7 @@ class MicrOp(Enum):
     OP_FMVIS = 96
     OP_FISHMV = 97
     OP_PCDEC = 98
-    OP_MADDED = 99
+    OP_MADDEDU = 99
     OP_DIVMOD2DU = 100
     OP_DSHL = 101
     OP_DSHR = 102

diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py
index 209cb08bb7e37ddec629b6a1c75b14a777af0d5a..e08c9775e2c1b89af5d4c6e4e4534ebc35b0f26e 100644 (file)
--- a/src/openpower/sv/trans/svp64.py
+++ b/src/openpower/sv/trans/svp64.py
@@ -587,7 +587,7 @@ def pcdec(fields):
 
 
 @_custom_insns(
-    _insn("madded", XO=50),
+    _insn("maddedu", XO=50),
     _insn("divmod2du", XO=52),
 )
 def va_form(fields, XO):

diff --git a/src/openpower/test/bigint/bigint_cases.py b/src/openpower/test/bigint/bigint_cases.py
index 622bbf373581c9fd95439fa06c5232cab8c15c83..fdafea597001026b57b3458e96658930ac1aa658 100644 (file)
--- a/src/openpower/test/bigint/bigint_cases.py
+++ b/src/openpower/test/bigint/bigint_cases.py
@@ -7,8 +7,8 @@ _SHIFT_TEST_RANGE = range(-64, 128, 16)
 
 
 class BigIntCases(TestAccumulatorBase):
-    def case_madded(self):
-        lst = list(SVP64Asm(["madded 3,5,6,7"]))
+    def case_maddedu(self):
+        lst = list(SVP64Asm(["maddedu 3,5,6,7"]))
         gprs = [0] * 32
         gprs[5] = 0x123456789ABCDEF
         gprs[6] = 0xFEDCBA9876543210