r600g: more integer support

just some more trivial integer changes for r600/r700.

Signed-off-by: Dave Airlie <airlied@redhat.com>

diff --git a/src/gallium/drivers/r600/r600_asm.c b/src/gallium/drivers/r600/r600_asm.c
index 0e2f0714b48b852888fa9e5d8d660a4ca5fcbf36..c4cc92202ced8563ae82e8252a62977bec7b8a28 100644 (file)
--- a/src/gallium/drivers/r600/r600_asm.c
+++ b/src/gallium/drivers/r600/r600_asm.c
@@ -50,6 +50,8 @@ static inline unsigned int r600_bytecode_get_num_operands(struct r600_bytecode *
                case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD:
                case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT:
                case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT:
+               case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT:
+               case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_OR_INT:
                case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE:
                case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT:
                case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE:
@@ -61,10 +63,20 @@ static inline unsigned int r600_bytecode_get_num_operands(struct r600_bytecode *
                case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT:
                case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX:
                case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN:
+               case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT:
+               case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT:
+               case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT:
+               case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT:
                case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE:
+               case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT:
                case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE:
+               case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_INT:
                case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT:
+               case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT:
+               case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_UINT:
                case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE:
+               case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT:
+               case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT:
                case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE:
                case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT:
                case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE:
@@ -95,6 +107,7 @@ static inline unsigned int r600_bytecode_get_num_operands(struct r600_bytecode *
                case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN:
                case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS:
                case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE:
+               case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT:
                        return 1;
                default: R600_ERR(
                        "Need instruction operand number for 0x%x.\n", alu->inst);
@@ -441,8 +454,9 @@ static int is_alu_trans_unit_inst(struct r600_bytecode *bc, struct r600_bytecode
        case R700:
                if (!alu->is_op3)
                        return alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT ||
-                               alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT ||
                                alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT ||
+                               alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT ||
+                               alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT ||
                                alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT ||
                                alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT ||
                                alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT ||

diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index bb0a9a99e7d59f20c5a1f59836f3821df63ddc10..87164ce48df491733191a1f1e6691bb6ad60f7f4 100644 (file)
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -3377,7 +3377,7 @@ static int tgsi_umad(struct r600_shader_ctx *ctx)
                alu.dst.sel = ctx->temp_reg;
                alu.dst.write = 1;
 
-               alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT;
+               alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT);
                for (j = 0; j < 2; j++) {
                        r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
                }
@@ -3396,7 +3396,7 @@ static int tgsi_umad(struct r600_shader_ctx *ctx)
                memset(&alu, 0, sizeof(struct r600_bytecode_alu));
                tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
 
-               alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT;
+               alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT);
 
                alu.src[0].sel = ctx->temp_reg;
                alu.src[0].chan = i;
@@ -3508,14 +3508,14 @@ static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
        {TGSI_OPCODE_PUSHA,     0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
        {TGSI_OPCODE_POPA,      0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
        {TGSI_OPCODE_CEIL,      0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-       {TGSI_OPCODE_I2F,       0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_I2F,       0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT, tgsi_op2_trans},
        {TGSI_OPCODE_NOT,       0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT, tgsi_op2},
        {TGSI_OPCODE_TRUNC,     0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_op2},
        {TGSI_OPCODE_SHL,       0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
        /* gap */
        {88,                    0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-       {TGSI_OPCODE_AND,       0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-       {TGSI_OPCODE_OR,        0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_AND,       0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT, tgsi_op2},
+       {TGSI_OPCODE_OR,        0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_OR_INT, tgsi_op2},
        {TGSI_OPCODE_MOD,       0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
        {TGSI_OPCODE_XOR,       0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT, tgsi_op2},
        {TGSI_OPCODE_SAD,       0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
@@ -3547,28 +3547,28 @@ static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
        {TGSI_OPCODE_END,       0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end},  /* aka HALT */
        /* gap */
        {118,                   0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-       {TGSI_OPCODE_F2I,       0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_F2I,       0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT, tgsi_op2},
        {TGSI_OPCODE_IDIV,      0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-       {TGSI_OPCODE_IMAX,      0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-       {TGSI_OPCODE_IMIN,      0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-       {TGSI_OPCODE_INEG,      0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-       {TGSI_OPCODE_ISGE,      0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_IMAX,      0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT, tgsi_op2},
+       {TGSI_OPCODE_IMIN,      0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT, tgsi_op2},
+       {TGSI_OPCODE_INEG,      0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT, tgsi_op2},
+       {TGSI_OPCODE_ISGE,      0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT, tgsi_op2},
        {TGSI_OPCODE_ISHR,      0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-       {TGSI_OPCODE_ISLT,      0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-       {TGSI_OPCODE_F2U,       0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-       {TGSI_OPCODE_U2F,       0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-       {TGSI_OPCODE_UADD,      0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_ISLT,      0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT, tgsi_op2},
+       {TGSI_OPCODE_F2U,       0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT, tgsi_op2},
+       {TGSI_OPCODE_U2F,       0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT, tgsi_op2},
+       {TGSI_OPCODE_UADD,      0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT, tgsi_op2},
        {TGSI_OPCODE_UDIV,      0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-       {TGSI_OPCODE_UMAD,      0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-       {TGSI_OPCODE_UMAX,      0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-       {TGSI_OPCODE_UMIN,      0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_UMAD,      0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_umad},
+       {TGSI_OPCODE_UMAX,      0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT, tgsi_op2},
+       {TGSI_OPCODE_UMIN,      0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT, tgsi_op2},
        {TGSI_OPCODE_UMOD,      0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-       {TGSI_OPCODE_UMUL,      0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-       {TGSI_OPCODE_USEQ,      0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-       {TGSI_OPCODE_USGE,      0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_UMUL,      0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT, tgsi_op2},
+       {TGSI_OPCODE_USEQ,      0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT, tgsi_op2},
+       {TGSI_OPCODE_USGE,      0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT, tgsi_op2},
        {TGSI_OPCODE_USHR,      0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-       {TGSI_OPCODE_USLT,      0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-       {TGSI_OPCODE_USNE,      0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_USLT,      0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT, tgsi_op2_swap},
+       {TGSI_OPCODE_USNE,      0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_INT, tgsi_op2_swap},
        {TGSI_OPCODE_SWITCH,    0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
        {TGSI_OPCODE_CASE,      0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
        {TGSI_OPCODE_DEFAULT,   0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},