(no commit message)

diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn
index d6b82ea9308827e9b4943f222591affc6ded52b6..370efc7fc52c25dd25acb94a738cfd36b539b278 100644 (file)
--- a/openpower/sv/rfc/ls001.mdwn
+++ b/openpower/sv/rfc/ls001.mdwn
@@ -74,12 +74,12 @@ they are all required to be reserved.
 * To hold all Vector Context, five SPRs are needed for userspace (MSR.PR=1 Problem State).
   If Supervisor and Hypervisor mode are to also support Simple-V they will correspondingly
   need five SPRs each.
-* Six 5/6-bit XO (A-Form) "Management" instructions are needed.
+* Five 6-bit XO (A-Form) "Management" instructions are needed.
 
 **Summary of Opcode space**
 
 * 75% of one Major Opcode (equivalent to the rest of EXT017)
-* Six 5/6-bit operations.
+* Five 6-bit operations.
 
 No further opcode space *for Simple-V* is envisaged to be required for at least
 the next decade.
@@ -96,11 +96,20 @@ the next decade.
 
 * Management Instructions
 
-**setvl** 
+* **setvl** - Cray-style Scalar Vector Length instruction
+* **svremap** - "tags" registers for activating REMAP
+* **svshape** - convenience instruction for quickly setting up Matrix, DCT, FFT and
+  Parallel Reduction REMAP
+* **svshape2** - additional convenience instruction to set up "Indexed" REMAP
+  (fits within svshape's XO encoding)
+* **svindex** - 
 
 # SVP64 24-bit Prefix
 
-The SVP64 24-bit Prefix provides several options 
+The SVP64 24-bit Prefix provides several options, too numerous to describe in this
+document. The primary options are:
+
+
 
 * Due to a concept called "Element-width Overrides