fix for self.rom core

diff --git a/src/openpower/test/runner.py b/src/openpower/test/runner.py
index bb43c5588ae397359b02e32ffcd76c22755a0bf8..a6ecd9f05593c4d9a4510ddc1a697f421cb82ea4 100644 (file)
--- a/src/openpower/test/runner.py
+++ b/src/openpower/test/runner.py
@@ -402,7 +402,7 @@ class TestRunnerBase(FHDLTestCase):
         # optionally, if a wishbone-based ROM is passed in, run that as an
         # extra emulated process
         if self.rom is not None:
-            dcache = core.fus.fus["mmu0"].alu.dcache
+            dcache = hdlrun.issuer.core.fus.fus["mmu0"].alu.dcache
             default_mem = self.rom
             sim.add_sync_process(wrap(wb_get(dcache, default_mem, "DCACHE")))