ac/nir: split 8-bit SSBO stores on GFX6

Due to possible alignment issues, make sure to split stores of
8-bit vectors.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4339>

diff --git a/src/amd/llvm/ac_nir_to_llvm.c b/src/amd/llvm/ac_nir_to_llvm.c
index be1c599fbb1825387cb47cfc4237f8c2fa17ee0d..84067667ef4cbbce0be7461b78b261ae372f6dd4 100644 (file)
--- a/src/amd/llvm/ac_nir_to_llvm.c
+++ b/src/amd/llvm/ac_nir_to_llvm.c
@@ -1740,6 +1740,15 @@ static void visit_store_ssbo(struct ac_nir_context *ctx,
                        count = 1;
                        num_bytes = 2;
                }
+
+               /* Due to alignment issues, split stores of 8-bit vectors. */
+               if (ctx->ac.chip_class == GFX6 &&
+                    elem_size_bytes == 1 && count > 1) {
+                       writemask |= ((1u << (count - 1)) - 1u) << (start + 1);
+                       count = 1;
+                       num_bytes = 1;
+               }
+
                data = extract_vector_range(&ctx->ac, base_data, start, count);
 
                offset = LLVMBuildAdd(ctx->ac.builder, base_offset,