soc: cores: fix name of EHXPLLL output clock in ECP5PLL

diff --git a/litex/soc/cores/clock.py b/litex/soc/cores/clock.py
index eb44d84986c92e3d1e31ae80c802ac3d91ae5f60..d5a8f4929e856b1fa864187a8d122d768c9d59eb 100644 (file)
--- a/litex/soc/cores/clock.py
+++ b/litex/soc/cores/clock.py
@@ -476,7 +476,7 @@ class ECP5PLL(Module):
             p_CLKI_DIV=1,
         )
         for n, (clk, f, p, m) in sorted(self.clkouts.items()):
-            n_to_l = {0: "P", 1: "S", 2: "OS2"}
+            n_to_l = {0: "P", 1: "S", 2: "S2"}
             self.params["p_CLKO{}_ENABLE".format(n_to_l[n])] = "ENABLED"
             self.params["p_CLKO{}_DIV".format(n_to_l[n])] = config["clko{}_div".format(n)]
             self.params["p_CLKO{}_FPHASE".format(n_to_l[n])] = 0