soc/interconnect/axi: add AXI Lite definition

diff --git a/litex/soc/interconnect/axi.py b/litex/soc/interconnect/axi.py
index eb82820c764766ec458665119d68fcdd6bdd9639..27174bb17b9655600a8dc9c54deb9b2922077a97 100644 (file)
--- a/litex/soc/interconnect/axi.py
+++ b/litex/soc/interconnect/axi.py
@@ -50,7 +50,6 @@ def r_description(data_width, id_width):
         ("id",   id_width)
     ]
 
-
 class AXIInterface(Record):
     def __init__(self, data_width, address_width, id_width=1, clock_domain="sys"):
         self.data_width = data_width
@@ -64,6 +63,38 @@ class AXIInterface(Record):
         self.ar = stream.Endpoint(ax_description(address_width, id_width))
         self.r = stream.Endpoint(r_description(data_width, id_width))
 
+# AXI Lite Definition -----------------------------------------------------------------------------------
+
+def ax_lite_description(address_width):
+    return [("addr",  address_width)]
+
+def w_lite_description(data_width):
+    return [
+        ("data", data_width),
+        ("strb", data_width//8)
+    ]
+
+def b_lite_description():
+    return [("resp", 2)]
+
+def r_lite_description(data_width):
+    return [
+        ("resp", 2),
+        ("data", data_width)
+    ]
+
+class AXILiteInterface(Record):
+    def __init__(self, data_width, address_width, clock_domain="sys"):
+        self.data_width = data_width
+        self.address_width = address_width
+        self.clock_domain = clock_domain
+
+        self.aw = stream.Endpoint(ax_lite_description(address_width))
+        self.w = stream.Endpoint(w_lite_description(data_width))
+        self.b = stream.Endpoint(b_lite_description())
+        self.ar = stream.Endpoint(ax_lite_description(address_width))
+        self.r = stream.Endpoint(r_lite_description(data_width))
+
 # AXI Bursts to Beats ------------------------------------------------------------------------------
 
 class AXIBurst2Beat(Module):