This commit removes parser and printer support for old SMT-LIB standards and also converts all regression tests to 2.6.
/** define the end points of smt2 languages */
namespace input {
+Language LANG_SMTLIB_V2_START = LANG_SMTLIB_V2_6;
Language LANG_SMTLIB_V2_END = LANG_SMTLIB_V2_6;
}
namespace output {
+Language LANG_SMTLIB_V2_START = LANG_SMTLIB_V2_6;
Language LANG_SMTLIB_V2_END = LANG_SMTLIB_V2_6;
}
bool isInputLang_smt2(InputLanguage lang)
{
- return lang >= input::LANG_SMTLIB_V2_0 && lang <= input::LANG_SMTLIB_V2_END;
+ return lang >= input::LANG_SMTLIB_V2_START
+ && lang <= input::LANG_SMTLIB_V2_END;
}
bool isOutputLang_smt2(OutputLanguage lang)
{
- return lang >= output::LANG_SMTLIB_V2_0 && lang <= output::LANG_SMTLIB_V2_END;
-}
-
-bool isInputLang_smt2_5(InputLanguage lang, bool exact)
-{
- return exact ? lang == input::LANG_SMTLIB_V2_5
- : (lang >= input::LANG_SMTLIB_V2_5
- && lang <= input::LANG_SMTLIB_V2_END);
-}
-
-bool isOutputLang_smt2_5(OutputLanguage lang, bool exact)
-{
- return exact ? lang == output::LANG_SMTLIB_V2_5
- : (lang >= output::LANG_SMTLIB_V2_5
- && lang <= output::LANG_SMTLIB_V2_END);
+ return lang >= output::LANG_SMTLIB_V2_START
+ && lang <= output::LANG_SMTLIB_V2_END;
}
bool isInputLang_smt2_6(InputLanguage lang, bool exact)
InputLanguage toInputLanguage(OutputLanguage language) {
switch(language) {
- case output::LANG_SMTLIB_V2_0:
- case output::LANG_SMTLIB_V2_5:
case output::LANG_SMTLIB_V2_6:
case output::LANG_TPTP:
case output::LANG_CVC4:
OutputLanguage toOutputLanguage(InputLanguage language) {
switch(language) {
- case input::LANG_SMTLIB_V2_0:
- case input::LANG_SMTLIB_V2_5:
case input::LANG_SMTLIB_V2_6:
case input::LANG_TPTP:
case input::LANG_CVC4:
} else if(language == "cvc3" || language == "LANG_CVC3") {
return output::LANG_CVC3;
}
- else if (language == "smtlib2.0" || language == "smt2.0"
- || language == "LANG_SMTLIB_V2_0")
- {
- return output::LANG_SMTLIB_V2_0;
- } else if(language == "smtlib2.5" || language == "smt2.5" ||
- language == "LANG_SMTLIB_V2_5") {
- return output::LANG_SMTLIB_V2_5;
- }
else if (language == "smtlib" || language == "smt" || language == "smtlib2"
|| language == "smt2" || language == "smtlib2.6"
|| language == "smt2.6" || language == "LANG_SMTLIB_V2_6"
language == "presentation" || language == "native" ||
language == "LANG_CVC4") {
return input::LANG_CVC4;
- } else if(language == "smtlib2.0" || language == "smt2.0" ||
- language == "LANG_SMTLIB_V2_0") {
- return input::LANG_SMTLIB_V2_0;
- } else if(language == "smtlib2.5" || language == "smt2.5" ||
- language == "LANG_SMTLIB_V2_5") {
- return input::LANG_SMTLIB_V2_5;
} else if(language == "smtlib" || language == "smt" ||
language == "smtlib2" || language == "smt2" ||
language == "smtlib2.6" || language == "smt2.6" ||
// OUTPUT LANGUAGE, IF IT IS "IN PRINCIPLE" A COMMON LANGUAGE,
// INCLUDE IT HERE
- /** The SMTLIB v2.0 input language */
- LANG_SMTLIB_V2_0 = 0,
- /** The SMTLIB v2.5 input language */
- LANG_SMTLIB_V2_5,
/** The SMTLIB v2.6 input language, with support for the strings standard */
- LANG_SMTLIB_V2_6,
+ LANG_SMTLIB_V2_6 = 0,
/** Backward-compatibility for enumeration naming */
LANG_SMTLIB_V2 = LANG_SMTLIB_V2_6,
/** The TPTP input language */
case LANG_AUTO:
out << "LANG_AUTO";
break;
- case LANG_SMTLIB_V2_0:
- out << "LANG_SMTLIB_V2_0";
- break;
- case LANG_SMTLIB_V2_5:
- out << "LANG_SMTLIB_V2_5";
- break;
case LANG_SMTLIB_V2_6:
out << "LANG_SMTLIB_V2_6";
break;
// OUTPUT LANGUAGE, IF IT IS "IN PRINCIPLE" A COMMON LANGUAGE,
// INCLUDE IT HERE
- /** The SMTLIB v2.0 output language */
- LANG_SMTLIB_V2_0 = input::LANG_SMTLIB_V2_0,
- /** The SMTLIB v2.5 output language */
- LANG_SMTLIB_V2_5 = input::LANG_SMTLIB_V2_5,
/** The SMTLIB v2.6 output language, with support for the strings standard */
LANG_SMTLIB_V2_6 = input::LANG_SMTLIB_V2_6,
/** Backward-compatibility for enumeration naming */
inline std::ostream& operator<<(std::ostream& out, Language lang) CVC4_PUBLIC;
inline std::ostream& operator<<(std::ostream& out, Language lang) {
switch(lang) {
- case LANG_SMTLIB_V2_0:
- out << "LANG_SMTLIB_V2_0";
- break;
- case LANG_SMTLIB_V2_5:
- out << "LANG_SMTLIB_V2_5";
- break;
case LANG_SMTLIB_V2_6: out << "LANG_SMTLIB_V2_6"; break;
case LANG_TPTP:
out << "LANG_TPTP";
bool isInputLang_smt2(InputLanguage lang) CVC4_PUBLIC;
bool isOutputLang_smt2(OutputLanguage lang) CVC4_PUBLIC;
-/**
- * Is the language smtlib 2.5 or above? If exact=true, then this method returns
- * false if the input language is not exactly SMT-LIB 2.5.
- */
-bool isInputLang_smt2_5(InputLanguage lang, bool exact = false) CVC4_PUBLIC;
-bool isOutputLang_smt2_5(OutputLanguage lang, bool exact = false) CVC4_PUBLIC;
/**
* Is the language smtlib 2.6 or above? If exact=true, then this method returns
* false if the input language is not exactly SMT-LIB 2.6.
auto attempt to automatically determine language\n\
cvc4 | presentation | pl CVC4 presentation language\n\
smt | smtlib | smt2 |\n\
- smt2.0 | smtlib2 | smtlib2.0 SMT-LIB format 2.0\n\
- smt2.5 | smtlib2.5 SMT-LIB format 2.5\n\
smt2.6 | smtlib2.6 SMT-LIB format 2.6 with support for the strings standard\n\
tptp TPTP format (cnf, fof and tff)\n\
sygus | sygus2 SyGuS version 2.0\n\
cvc4 | presentation | pl CVC4 presentation language\n\
cvc3 CVC3 presentation language\n\
smt | smtlib | smt2 |\n\
- smt2.0 | smtlib2.0 | smtlib2 SMT-LIB format 2.0\n\
- smt2.5 | smtlib2.5 SMT-LIB format 2.5\n\
smt2.6 | smtlib2.6 SMT-LIB format 2.6 with support for the strings standard\n\
tptp TPTP format\n\
ast internal format (simple syntax trees)\n\
OutputLanguage d_language;
};/* class SetLanguage */
-
/**
* Sets the output language when pretty-printing a Expr to an ostream.
- * This is used liek this:
- *
- * // let out be an ostream, e an Expr
- * out << language::SetLanguage(LANG_SMTLIB_V2_5) << e << endl;
- *
- * This used to be used like this:
+ * This is used like this:
*
* // let out be an ostream, e an Expr
- * out << Expr::setlanguage(LANG_SMTLIB_V2_5) << e << endl;
+ * out << Expr::setlanguage(LANG_SMTLIB_V2_6) << e << endl;
*
* The setting stays permanently (until set again) with the stream.
*/
/* New SMT-LIB 2.5 command set */
| smt25Command[cmd]
- { if(PARSER_STATE->v2_0() && PARSER_STATE->strictModeEnabled()) {
- PARSER_STATE->parseError(
- "SMT-LIB 2.5 commands are not permitted while operating in strict "
- "compliance mode and in SMT-LIB 2.0 mode.");
- }
- }
/* CVC4-extended SMT-LIB commands */
| extendedCommand[cmd]
}
/* Extended SMT-LIB set of commands syntax, not permitted in
* --smtlib2 compliance mode. */
- : DECLARE_DATATYPES_2_5_TOK datatypes_2_5_DefCommand[false, cmd]
- | DECLARE_CODATATYPES_2_5_TOK datatypes_2_5_DefCommand[true, cmd]
- | DECLARE_CODATATYPE_TOK datatypeDefCommand[true, cmd]
+ : DECLARE_CODATATYPE_TOK datatypeDefCommand[true, cmd]
| DECLARE_CODATATYPES_TOK datatypesDefCommand[true, cmd]
/* Support some of Z3's extended SMT-LIB commands */
)
;
-
-datatypes_2_5_DefCommand[bool isCo, std::unique_ptr<CVC4::Command>* cmd]
-@declarations {
- std::vector<api::DatatypeDecl> dts;
- std::string name;
- std::vector<api::Sort> sorts;
- std::vector<std::string> dnames;
- std::vector<unsigned> arities;
-}
- : { PARSER_STATE->checkThatLogicIsSet();
- /* open a scope to keep the UnresolvedTypes contained */
- PARSER_STATE->pushScope(); }
- LPAREN_TOK /* parametric sorts */
- ( symbol[name,CHECK_UNDECLARED,SYM_SORT]
- {
- sorts.push_back(PARSER_STATE->mkSort(name));
- }
- )*
- RPAREN_TOK
- LPAREN_TOK ( LPAREN_TOK datatypeDef[isCo, dts, sorts] RPAREN_TOK )+ RPAREN_TOK
- { PARSER_STATE->popScope();
- cmd->reset(new DatatypeDeclarationCommand(
- PARSER_STATE->bindMutualDatatypeTypes(dts, true)));
- }
- ;
-
datatypeDefCommand[bool isCo, std::unique_ptr<CVC4::Command>* cmd]
@declarations {
std::vector<api::DatatypeDecl> dts;
GET_UNSAT_ASSUMPTIONS_TOK : 'get-unsat-assumptions';
GET_UNSAT_CORE_TOK : 'get-unsat-core';
EXIT_TOK : 'exit';
-RESET_TOK : { PARSER_STATE->v2_5() }? 'reset';
+RESET_TOK : 'reset';
RESET_ASSERTIONS_TOK : 'reset-assertions';
LET_TOK : 'let';
ATTRIBUTE_TOK : '!';
addOperator(api::SEQ_UNIT, "seq.unit");
addOperator(api::SEQ_NTH, "seq.nth");
}
- // at the moment, we only use this syntax for smt2.6
- if (getLanguage() == language::input::LANG_SMTLIB_V2_6
- || getLanguage() == language::input::LANG_SYGUS_V2)
- {
- addOperator(api::STRING_FROM_INT, "str.from_int");
- addOperator(api::STRING_TO_INT, "str.to_int");
- addOperator(api::STRING_IN_REGEXP, "str.in_re");
- addOperator(api::STRING_TO_REGEXP, "str.to_re");
- addOperator(api::STRING_TO_CODE, "str.to_code");
- addOperator(api::STRING_REPLACE_ALL, "str.replace_all");
- }
- else
- {
- addOperator(api::STRING_FROM_INT, "int.to.str");
- addOperator(api::STRING_TO_INT, "str.to.int");
- addOperator(api::STRING_IN_REGEXP, "str.in.re");
- addOperator(api::STRING_TO_REGEXP, "str.to.re");
- addOperator(api::STRING_TO_CODE, "str.code");
- addOperator(api::STRING_REPLACE_ALL, "str.replaceall");
- }
+ addOperator(api::STRING_FROM_INT, "str.from_int");
+ addOperator(api::STRING_TO_INT, "str.to_int");
+ addOperator(api::STRING_IN_REGEXP, "str.in_re");
+ addOperator(api::STRING_TO_REGEXP, "str.to_re");
+ addOperator(api::STRING_TO_CODE, "str.to_code");
+ addOperator(api::STRING_REPLACE_ALL, "str.replace_all");
addOperator(api::REGEXP_CONCAT, "re.++");
addOperator(api::REGEXP_UNION, "re.union");
defineType("RegLan", d_solver->getRegExpSort(), true, true);
defineType("Int", d_solver->getIntegerSort(), true, true);
- if (getLanguage() == language::input::LANG_SMTLIB_V2_6
- || getLanguage() == language::input::LANG_SYGUS_V2)
- {
- defineVar("re.none", d_solver->mkRegexpEmpty());
- }
- else
- {
- defineVar("re.nostr", d_solver->mkRegexpEmpty());
- }
+ defineVar("re.none", d_solver->mkRegexpEmpty());
defineVar("re.allchar", d_solver->mkRegexpSigma());
// Boolean is a placeholder
api::Grammar* mkGrammar(const std::vector<api::Term>& boundVars,
const std::vector<api::Term>& ntSymbols);
- bool v2_0() const
- {
- return getLanguage() == language::input::LANG_SMTLIB_V2_0;
- }
- /**
- * Are we using smtlib 2.5 or above? If exact=true, then this method returns
- * false if the input language is not exactly SMT-LIB 2.5.
- */
- bool v2_5(bool exact = false) const
- {
- return language::isInputLang_smt2_5(getLanguage(), exact);
- }
/**
* Are we using smtlib 2.6 or above? If exact=true, then this method returns
* false if the input language is not exactly SMT-LIB 2.6.
* and SyGuS) treats duplicate double quotes ("") as an escape sequence
* denoting a single double quote (").
*/
- bool escapeDupDblQuote() const { return v2_5() || sygus(); }
+ bool escapeDupDblQuote() const { return v2_6() || sygus(); }
void checkThatLogicIsSet();
using namespace CVC4::language::output;
switch(lang) {
- case LANG_SMTLIB_V2_0:
- return unique_ptr<Printer>(
- new printer::smt2::Smt2Printer(printer::smt2::smt2_0_variant));
-
- case LANG_SMTLIB_V2_5:
- return unique_ptr<Printer>(new printer::smt2::Smt2Printer());
-
case LANG_SMTLIB_V2_6:
return unique_ptr<Printer>(
new printer::smt2::Smt2Printer(printer::smt2::smt2_6_variant));
namespace printer {
namespace smt2 {
-/** returns whether the variant is smt-lib 2.6 or greater */
-bool isVariant_2_6(Variant v) { return v == smt2_6_variant; }
-
static void toStreamRational(std::ostream& out,
const Rational& r,
bool decimal,
for(size_t i = 0; i < s.size(); ++i) {
char c = s[i];
if(c == '"') {
- if(d_variant == smt2_0_variant) {
- out << "\\\"";
- } else {
- out << "\"\"";
- }
+ out << "\"\"";
} else {
out << c;
}
case kind::BITVECTOR_PLUS: out << "bvadd "; forceBinary = true; break;
case kind::BITVECTOR_SUB: out << "bvsub "; break;
case kind::BITVECTOR_NEG: out << "bvneg "; break;
- case kind::BITVECTOR_UDIV: out << "bvudiv "; break;
- case kind::BITVECTOR_UDIV_TOTAL:
- out << (isVariant_2_6(d_variant) ? "bvudiv " : "bvudiv_total ");
- break;
- case kind::BITVECTOR_UREM: out << "bvurem "; break;
- case kind::BITVECTOR_UREM_TOTAL:
- out << (isVariant_2_6(d_variant) ? "bvurem " : "bvurem_total ");
- break;
+ case kind::BITVECTOR_UDIV:
+ case kind::BITVECTOR_UDIV_TOTAL: out << "bvudiv "; break;
+ case kind::BITVECTOR_UREM:
+ case kind::BITVECTOR_UREM_TOTAL: out << "bvurem "; break;
case kind::BITVECTOR_SDIV: out << "bvsdiv "; break;
case kind::BITVECTOR_SREM: out << "bvsrem "; break;
case kind::BITVECTOR_SMOD: out << "bvsmod "; break;
{
unsigned cindex = DType::indexOf(n.getOperator().toExpr());
const DType& dt = DType::datatypeOf(n.getOperator().toExpr());
- if (isVariant_2_6(d_variant))
- {
- out << "(_ is ";
- toStream(out,
- dt[cindex].getConstructor(),
- toDepth < 0 ? toDepth : toDepth - 1);
- out << ")";
- }else{
- out << "is-";
- toStream(out,
- dt[cindex].getConstructor(),
- toDepth < 0 ? toDepth : toDepth - 1);
- }
+ out << "(_ is ";
+ toStream(out,
+ dt[cindex].getConstructor(),
+ toDepth < 0 ? toDepth : toDepth - 1);
+ out << ")";
}else{
toStream(
out, n.getOperator(), toDepth < 0 ? toDepth : toDepth - 1, lbind);
std::vector<Node> elements = tm->getDomainElements(tn);
if (options::modelUninterpPrint() == options::ModelUninterpPrintMode::DtEnum)
{
- if (isVariant_2_6(d_variant))
- {
- out << "(declare-datatypes ((" << tn << " 0)) (";
- }
- else
- {
- out << "(declare-datatypes () ((" << tn << " ";
- }
+ out << "(declare-datatypes ((" << tn << " 0)) (";
for (const Node& type_ref : elements)
{
out << "(" << type_ref << ")";
{
if (!n.isNull())
{
- if (d_variant == smt2_0_variant)
- {
- toStreamCmdCheckSat(out, BooleanSimplification::negate(n));
- }
- else
- {
- toStreamCmdCheckSatAssuming(out, {n});
- }
+ toStreamCmdCheckSatAssuming(out, {n});
}
else
{
out << "co";
}
out << "datatypes";
- if (isVariant_2_6(d_variant))
+ out << " (";
+ for (const TypeNode& t : datatypes)
{
- out << " (";
- for (const TypeNode& t : datatypes)
- {
- Assert(t.isDatatype());
- const DType& d = t.getDType();
- out << "(" << CVC4::quoteSymbol(d.getName());
- out << " " << d.getNumParameters() << ")";
- }
- out << ") (";
- for (const TypeNode& t : datatypes)
- {
- Assert(t.isDatatype());
- const DType& d = t.getDType();
- if (d.isParametric())
- {
- out << "(par (";
- for (unsigned p = 0, nparam = d.getNumParameters(); p < nparam; p++)
- {
- out << (p > 0 ? " " : "") << d.getParameter(p);
- }
- out << ")";
- }
- out << "(";
- toStream(out, d);
- out << ")";
- if (d.isParametric())
- {
- out << ")";
- }
- }
- out << ")";
+ Assert(t.isDatatype());
+ const DType& d = t.getDType();
+ out << "(" << CVC4::quoteSymbol(d.getName());
+ out << " " << d.getNumParameters() << ")";
}
- else
+ out << ") (";
+ for (const TypeNode& t : datatypes)
{
- out << " (";
- // Can only print if all datatypes in this block have the same parameters.
- // In theory, given input language 2.6 and output language 2.5, it could
- // be impossible to print a datatype block where datatypes were given
- // different parameter lists.
- bool success = true;
- unsigned nparam = d0.getNumParameters();
- for (unsigned j = 1, ndt = datatypes.size(); j < ndt; j++)
- {
- Assert(datatypes[j].isDatatype());
- const DType& dj = datatypes[j].getDType();
- if (dj.getNumParameters() != nparam)
- {
- success = false;
- }
- else
- {
- // must also have identical parameter lists
- for (unsigned k = 0; k < nparam; k++)
- {
- if (dj.getParameter(k) != d0.getParameter(k))
- {
- success = false;
- break;
- }
- }
- }
- if (!success)
- {
- break;
- }
- }
- if (success)
+ Assert(t.isDatatype());
+ const DType& d = t.getDType();
+ if (d.isParametric())
{
- for (unsigned j = 0; j < nparam; j++)
+ out << "(par (";
+ for (unsigned p = 0, nparam = d.getNumParameters(); p < nparam; p++)
{
- out << (j > 0 ? " " : "") << d0.getParameter(j);
+ out << (p > 0 ? " " : "") << d.getParameter(p);
}
+ out << ")";
}
- else
- {
- out << std::endl;
- out << "ERROR: datatypes in each block must have identical parameter "
- "lists.";
- out << std::endl;
- }
- out << ") (";
- for (const TypeNode& t : datatypes)
+ out << "(";
+ toStream(out, d);
+ out << ")";
+ if (d.isParametric())
{
- Assert(t.isDatatype());
- const DType& dt = t.getDType();
- out << "(" << CVC4::quoteSymbol(dt.getName()) << " ";
- toStream(out, dt);
out << ")";
}
- out << ")";
}
+ out << ")";
out << ")" << std::endl;
}
size_t pos = 0;
while ((pos = s.find_first_of('"', pos)) != string::npos)
{
- s.replace(pos, 1, d_variant == smt2_0_variant ? "\\\"" : "\"\"");
+ s.replace(pos, 1, "\"\"");
pos += 2;
}
out << "(set-info :notes \"" << s << "\")" << std::endl;
size_t pos = 0;
while ((pos = s.find('"', pos)) != string::npos)
{
- s.replace(pos, 1, d_variant == smt2_0_variant ? "\\\"" : "\"\"");
+ s.replace(pos, 1, "\"\"");
pos += 2;
}
out << "(echo \"" << s << "\")" << std::endl;
// escape all double-quotes
size_t pos = 0;
while((pos = message.find('"', pos)) != string::npos) {
- message.replace(pos, 1, v == smt2_0_variant ? "\\\"" : "\"\"");
+ message.replace(pos, 1, "\"\"");
pos += 2;
}
out << "(error \"" << message << "\")" << endl;
enum Variant
{
no_variant,
- smt2_0_variant, // old-style 2.0 syntax, when it makes a difference
smt2_6_variant, // new-style 2.6 syntax, when it makes a difference, with
// support for the string standard
}; /* enum Variant */
int toDepth,
size_t dag) const
{
- n.toStream(out, toDepth, dag, language::output::LANG_SMTLIB_V2_5);
+ n.toStream(out, toDepth, dag, language::output::LANG_SMTLIB_V2_6);
}/* TptpPrinter::toStream() */
void TptpPrinter::toStream(std::ostream& out, const CommandStatus* s) const
{
- s->toStream(out, language::output::LANG_SMTLIB_V2_5);
+ s->toStream(out, language::output::LANG_SMTLIB_V2_6);
}/* TptpPrinter::toStream() */
void TptpPrinter::toStream(std::ostream& out, const smt::Model& m) const
: "CandidateFiniteModel");
out << "% SZS output start " << statusName << " for " << m.getInputName()
<< endl;
- this->Printer::toStreamUsing(language::output::LANG_SMTLIB_V2_5, out, m);
+ this->Printer::toStreamUsing(language::output::LANG_SMTLIB_V2_6, out, m);
out << "% SZS output end " << statusName << " for " << m.getInputName()
<< endl;
}
{
language::input::Language ilang = language::input::LANG_AUTO;
- if (value == "2" || value == "2.0")
- {
- ilang = language::input::LANG_SMTLIB_V2_0;
- }
- else if (value == "2.5")
- {
- ilang = language::input::LANG_SMTLIB_V2_5;
- }
- else if (value == "2.6")
+ if (value == "2.6")
{
ilang = language::input::LANG_SMTLIB_V2_6;
}
regress0/fmf/Arrow_Order-smtlib.778341.smtv1.smt2
regress0/fmf/bounded_sets.smt2
regress0/fmf/bug-041417-set-options.cvc
- regress0/fmf/bug652.smt2
regress0/fmf/bug782.smt2
regress0/fmf/cruanes-no-minimal-unk.smt2
regress0/fmf/fc-simple.smt2
regress0/ite2.smt2
regress0/ite3.smt2
regress0/ite4.smt2
- regress0/lang_opts_2_5.smt2
regress0/lang_opts_2_6_1.smt2
regress0/lemmas/clocksynchro_5clocks.main_invar.base.model.smtv1.smt2
regress0/lemmas/fs_not_sc_seen.induction.smtv1.smt2
; COMMAND-LINE: --no-check-unsat-cores
; EXPECT: unsat
(set-logic QF_AUFLIRA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status unsat)
(declare-fun v1 () Int)
(set-logic QF_NIA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :status unsat)
(declare-fun n () Int)
; COMMAND-LINE: -q
; EXPECT: sat
(set-logic QF_NIA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :status sat)
(declare-fun n () Int)
(set-logic QF_NRA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :status unsat)
(declare-fun x () Real)
(declare-fun y () Real)
; EXPECT: sat
(set-logic QF_NRA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :status sat)
(declare-fun x () Real)
(declare-fun y () Real)
(set-logic QF_NRA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :status unsat)
(declare-fun x () Real)
(declare-fun y () Real)
; COMMAND-LINE: --ackermann --no-check-models --no-check-unsat-cores
; EXPECT: unsat
(set-logic QF_ALIA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status unsat)
; COMMAND-LINE: --ackermann --no-check-models
; EXPECT: sat
(set-logic QF_UFLIA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(declare-fun v0 () Int)
(declare-fun f (Int) Int)
; COMMAND-LINE: --ackermann --no-check-models --no-check-unsat-cores
; EXPECT: unsat
(set-logic QF_UFLIA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(declare-fun v0 () Int)
(declare-fun f (Int) Int)
; EXPECT: sat
(set-logic QF_NIA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :status sat)
(declare-fun n () Int)
(declare-fun x () Int)
; EXPECT: unsat
(set-logic QF_NRA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :status unsat)
(declare-fun n () Real)
(declare-fun x () Real)
|)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status unsat)
(declare-sort Index 0)
|)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status unsat)
(declare-sort Index 0)
|)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status sat)
(declare-sort Index 0)
|)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status sat)
(declare-sort Index 0)
|)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status unsat)
(declare-sort Index 0)
(set-info :source |fuzzsmt|)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "random")
(set-info :status sat)
(set-logic QF_AUFBV)
(set-info :source | This is based on an example in Section 6.2 of "A Decision
Procedure for an Extensional Theory of Arrays" by Stump, Barrett, Dill, and
Levitt. |)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "check")
(set-info :status unsat)
(set-info :notes |This benchmark is designed to require an array DP to propagate a properly entailed disjunction of equalities between shared terms.|)
; EXPECT: unsat
(set-logic QF_UF)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status unsat)
; EXPECT: unsat
(set-logic QF_UF)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status unsat)
(set-logic QF_LIA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :status unsat)
(assert (let
((a 2))
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :status sat)
(set-logic QF_BV)
(declare-fun v0 () (_ BitVec 1))
; removal for PARAMETERIZED kinds.
; Thanks to Andrew Reynolds for catching this.
(set-logic QF_UF)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :status sat)
(declare-sort U 0)
(declare-fun a () U)
; COMMAND-LINE: --bitblast=eager --bv-solver=simple --no-check-models --no-check-unsat-cores
; EXPECT: sat
(set-logic QF_UFBV)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(declare-fun v0 () (_ BitVec 4))
(declare-fun f ((_ BitVec 4)) (_ BitVec 4))
; COMMAND-LINE: --bitblast=eager --bv-sat-solver=cryptominisat --no-check-unsat-cores
; EXPECT: unsat
(set-logic QF_UFBV)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status unsat)
(declare-fun v0 () (_ BitVec 4))
; COMMAND-LINE: --bitblast=eager --no-check-models --no-check-unsat-cores
; EXPECT: unsat
(set-logic QF_ABV)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status unsat)
; COMMAND-LINE: --bitblast=eager --no-check-models --no-check-unsat-cores
; EXPECT: sat
(set-logic QF_UFBV)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(declare-fun v0 () (_ BitVec 4))
(declare-fun f ((_ BitVec 4)) (_ BitVec 4))
; EXPECT: unsat
; EXIT: 0
(set-logic QF_BV)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(declare-fun v0 () (_ BitVec 16))
(declare-fun v1 () (_ BitVec 16))
(set-logic QF_BV)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status unsat)
(declare-fun x () (_ BitVec 3))
(set-logic QF_BV)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status unsat)
(declare-fun v0 () (_ BitVec 16))
(set-logic QF_BV)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status sat)
(declare-fun v0 () (_ BitVec 16))
(set-logic QF_BV)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status unsat)
(declare-fun v0 () (_ BitVec 16))
(set-logic QF_BV)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status unsat)
(declare-fun v0 () (_ BitVec 16))
(set-logic QF_BV)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status unsat)
(declare-fun v0 () (_ BitVec 16))
(set-logic QF_BV)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status sat)
(declare-fun v0 () (_ BitVec 16))
; EXPECT: sat
(set-logic AUFLIRA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "industrial")
(set-info :status sat)
(declare-sort U 0)
+++ /dev/null
-; COMMAND-LINE: --fmf-fun --no-check-models
-; EXPECT: sat
-(set-logic UFDTSLIA)
-(set-info :smt-lib-version 2.5)
-(set-option :produce-models true)
-
-(declare-datatypes () (
- (List_boolean (List_boolean$CNil_boolean) (List_boolean$Cstr_boolean (List_boolean$Cstr_boolean$head Bool) (List_boolean$Cstr_boolean$tail List_boolean)))
-) )
-
-(define-funs-rec
- (
- (f4208$lengthList_boolean((x List_boolean)) Int)
- )
- (
- (ite (is-List_boolean$CNil_boolean x) 0 (+ 1 (f4208$lengthList_boolean (List_boolean$Cstr_boolean$tail x))))
- )
-)
-
-
-(declare-const boolean Bool)
-(check-sat)
(set-logic QF_FP)
(set-info :source |Written by Andres Noetzli for issue #2183|)
-(set-info :smt-lib-version 2.5)
+(set-info :smt-lib-version 2.6)
(set-info :category crafted)
(set-info :status unsat)
\r
(set-logic QF_FP)\r
(set-info :source |Written by Martin for issue #2932|)\r
-(set-info :smt-lib-version 2.5)\r
+(set-info :smt-lib-version 2.6)\r
(set-info :category crafted)\r
(set-info :status unsat)\r
\r
; COMMAND-LINE: --incremental
; EXPECT: sat
; EXPECT: (((f 0) 1))
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-option :produce-models true)
(set-logic QF_UFLIA)
; EXPECT: sat
; EXPECT: ((pos 1) (zero 0) (neg (- 6)))
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-option :produce-models true)
(set-logic QF_LIA)
; EXPECT: sat
; EXPECT: ((pos_int 5) (pos_real_int_value 3.0) (pos_rat (/ 1 3)) (zero 0.0) (neg_rat (/ (- 2) 3)) (neg_real_int_value (- 2.0)) (neg_int (- 6)))
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-option :produce-models true)
(set-logic QF_LIRA)
; EXPECT: sat
; EXPECT: ((pos_int 3.0) (pos_rat (/ 1 3)) (zero 0.0) (neg_rat (/ (- 2) 3)) (neg_int (- 2.0)))
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-option :produce-models true)
(set-logic QF_LRA)
( set-logic QF_ALL_SUPPORTED)
( set-info :source | SMT-COMP'06 organizers |)
-( set-info :smt-lib-version 2.0)
+( set-info :smt-lib-version 2.6)
( set-info :category "check")
( set-info :status sat)
( declare-fun x1 () Bool)
( set-logic QF_ALL_SUPPORTED)
( set-info :source | SMT-COMP'06 organizers |)
-( set-info :smt-lib-version 2.0)
+( set-info :smt-lib-version 2.6)
( set-info :category "check")
( set-info :status sat)
( declare-fun x1 () Bool)
+++ /dev/null
-; Check that the language set in the command line options has higher priority
-; than the language specified in the input file.
-;
-; COMMAND-LINE: --lang=smt2.5
-; EXPECT: "LANG_SMTLIB_V2_5"
-(set-info :smt-lib-version 2.6)
-(get-option :input-language)
Submitted by Harald Roman Zankl <Harald.Zankl@uibk.ac.at>
|)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "industrial")
(set-info :status sat)
(define-fun x6 () Real
|)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "industrial")
(set-info :status sat)
(declare-fun skoC () Real)
Harald Roman Zankl <Harald.Zankl@uibk.ac.at>
|)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status unsat)
(declare-fun a () Real)
(set-logic QF_UF)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status sat)
(declare-sort I 0)
; EXPECT: sat
; EXPECT: (
-; EXPECT: (define-fun s () String "\"")
+; EXPECT: (define-fun s () String "\u{5c}""")
; EXPECT: )
(set-logic QF_S)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-option :produce-models true)
(declare-fun s () String)
-(assert (= s "\""))
+(assert (= s "\"""))
(check-sat)
(get-model)
; EXPECT: )
(set-logic QF_S)
-(set-info :smt-lib-version 2.5)
(set-option :produce-models true)
(declare-fun s () String)
; EXPECT: sat
; EXPECT: sat
(set-logic UFDTSLIA)
-(set-info :smt-lib-version 2.5)
-
-(declare-datatypes () (
- (Response (Response$Response (Response$Response$success Bool)))
- ) )
+(set-info :smt-lib-version 2.6)
+(declare-datatype Response ((Response$Response (Response$Response$success Bool))))
(push 1)
(declare-fun $BLout$3248$0$1$() Response)
(set-logic AUFLIA)
(set-info :source | Simple list theorem |)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status unsat)
(declare-sort List 0)
Boogie/Spec# benchmarks.
This benchmark was translated by Michal Moskal.
|)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "industrial")
(set-info :status sat)
(declare-fun select2 (Int) Int)
(set-logic AUFLIRA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "industrial")
(set-info :status unsat)
(declare-sort U 0)
(set-logic AUFLIRA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "industrial")
(set-info :status unsat)
(declare-sort U 0)
-(set-info :smt-lib-version 2.5)
+(set-info :smt-lib-version 2.6)
(set-logic QF_S)
(set-info :status sat)
(declare-fun y () String)
(declare-fun z () String)
-(assert (= "\x4a" x))
-(assert (= "\x6a" y))
+(assert (= "J" x))
+(assert (= "j" y))
-(assert (= "\x4A" z))
+(assert (= "J" z))
(assert (= x z))
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-logic ASLIA)
(set-option :strings-exp true)
(set-info :status sat)
; regex = [\*-,\t\*-\|](.{6,}()?)+
-(define-fun strinre ((?s String)) Bool (str.in.re ?s (re.union re.nostr (re.++ (str.to.re "") (str.to.re "") (re.union re.nostr (re.range "*" ",") (str.to.re "\t") (re.range "*" "|") ) (re.+ (re.union re.nostr (re.++ (str.to.re "") (str.to.re "") ((_ re.^ 6) re.allchar) (re.opt (re.union re.nostr (re.++ (str.to.re "") (str.to.re "") ) ) ) ) ) ) ) ) ) )
+(define-fun strinre ((?s String)) Bool (str.in_re ?s (re.union re.none (re.++ (str.to_re "") (str.to_re "") (re.union re.none (re.range "*" ",") (str.to_re "\t") (re.range "*" "|") ) (re.+ (re.union re.none (re.++ (str.to_re "") (str.to_re "") ((_ re.^ 6) re.allchar) (re.opt (re.union re.none (re.++ (str.to_re "") (str.to_re "") ) ) ) ) ) ) ) ) ) )
(assert (not (strinre "6O\1\127\n?")))
(check-sat)
(set-logic QF_S)
(set-info :status sat)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(declare-fun x () String)
(declare-const I Int)
-(assert (= x "\0\1\2\3\04\005\x06\7\8\9ABC\\\"\t\a\b"))
+(assert (= x "\0\1\2\3\04\005\x06\7\8\9ABC\\""\t\a\b"))
(assert (= I (str.len x)))
; COMMAND-LINE: --incremental
; EXPECT: sat
(set-logic QF_UFLIA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :status sat)
(declare-fun f (Int) Bool)
; COMMAND-LINE: --unconstrained-simp --no-check-models
(set-logic QF_AUFBVLIA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status sat)
(declare-fun v1 () Int)
; COMMAND-LINE: --unconstrained-simp --no-check-models
(set-logic QF_AUFLIRA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status unsat)
(declare-fun v1 () Int)
; COMMAND-LINE: --unconstrained-simp --no-check-models
(set-logic QF_AUFLIRA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status unsat)
(declare-fun v1 () Int)
; COMMAND-LINE: --unconstrained-simp --no-check-models
(set-logic QF_AUFNIRA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status unsat)
(declare-fun v1 () Int)
; COMMAND-LINE: --unconstrained-simp --no-check-models
(set-logic QF_AUFBVLRA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status sat)
(declare-fun v1 () Real)
; COMMAND-LINE: --unconstrained-simp --no-check-models
(set-logic QF_AUFBVLRA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status sat)
(declare-fun v1 () Real)
; COMMAND-LINE: --unconstrained-simp --no-check-models
(set-logic QF_AUFLIRA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status unsat)
(declare-fun v1 () Int)
; COMMAND-LINE: --unconstrained-simp --no-check-models
(set-logic QF_AUFBV)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status sat)
(declare-fun v1 () (_ BitVec 16))
; COMMAND-LINE: --unconstrained-simp --no-check-models
(set-logic QF_AUFBVLIA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status sat)
(declare-fun x0 () (_ BitVec 10))
; COMMAND-LINE: --unconstrained-simp --no-check-models
(set-logic QF_AUFBVLIA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status unsat)
(declare-fun x0 () (_ BitVec 10))
; COMMAND-LINE: --unconstrained-simp --no-check-models
(set-logic QF_AUFBVLIA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status sat)
(declare-fun x0 () (_ BitVec 10))
; COMMAND-LINE: --unconstrained-simp --no-check-models
(set-logic QF_AUFBVLIA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status sat)
(declare-fun v1 () (_ BitVec 1))
; COMMAND-LINE: --unconstrained-simp --no-check-models
(set-logic QF_AUFBVLIA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status sat)
(declare-fun x0 () (_ BitVec 10))
; COMMAND-LINE: --unconstrained-simp --no-check-models
(set-logic QF_AUFBVLIA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status unsat)
(declare-fun x0 () (_ BitVec 10))
; COMMAND-LINE: --unconstrained-simp --no-check-models
(set-logic QF_AUFBVLIA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status sat)
(declare-fun x0 () (_ BitVec 10))
; COMMAND-LINE: --unconstrained-simp --no-check-models
(set-logic QF_AUFBVLIA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status sat)
(declare-fun v1 () (_ BitVec 10))
; COMMAND-LINE: --unconstrained-simp --no-check-models
(set-logic QF_AUFBVLIA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status sat)
(declare-fun x0 () (_ BitVec 10))
; COMMAND-LINE: --unconstrained-simp --no-check-models
(set-logic QF_AUFBVLIA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status sat)
(declare-fun x0 () (_ BitVec 10))
; COMMAND-LINE: --unconstrained-simp --no-check-models
(set-logic QF_AUFBVLIA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status unsat)
(declare-fun x0 () (_ BitVec 10))
; COMMAND-LINE: --unconstrained-simp --no-check-models
(set-logic QF_AUFBVLIA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status sat)
(declare-fun x0 () (_ BitVec 10))
; COMMAND-LINE: --unconstrained-simp --no-check-models
(set-logic QF_AUFBVLIA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status sat)
(declare-fun v1 () (_ BitVec 1))
; COMMAND-LINE: --unconstrained-simp --no-check-models
(set-logic QF_AUFBVLIA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status sat)
(declare-fun x0 () (_ BitVec 10))
; COMMAND-LINE: --unconstrained-simp --no-check-models
(set-logic QF_AUFBVLIA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status sat)
(declare-fun x0 () (_ BitVec 10))
; COMMAND-LINE: --unconstrained-simp --no-check-models
(set-logic QF_AUFBVLIA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status unsat)
(declare-fun x0 () (_ BitVec 10))
; COMMAND-LINE: --unconstrained-simp --no-check-models
(set-logic QF_AUFBVLIA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status sat)
(declare-fun x0 () (_ BitVec 10))
; COMMAND-LINE: --unconstrained-simp --no-check-models
(set-logic QF_AUFBVLIA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status unsat)
(declare-fun x0 () (_ BitVec 10))
; COMMAND-LINE: --unconstrained-simp --no-check-models
(set-logic QF_AUFBVLIA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status sat)
(declare-fun x0 () (_ BitVec 10))
; COMMAND-LINE: --unconstrained-simp --no-check-models
(set-logic QF_AUFBVLIA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status sat)
(declare-fun x0 () (_ BitVec 10))
; COMMAND-LINE: --unconstrained-simp --no-check-models
(set-logic QF_AUFBVLIA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status unsat)
(declare-fun x0 () (_ BitVec 10))
; COMMAND-LINE: --unconstrained-simp --no-check-models
(set-logic QF_AUFBVLIA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status sat)
(declare-fun x0 () (_ BitVec 10))
; COMMAND-LINE: --unconstrained-simp --no-check-models
(set-logic QF_AUFBVLIA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status unsat)
(declare-fun x0 () (_ BitVec 10))
; COMMAND-LINE: --unconstrained-simp --no-check-models
(set-logic QF_AUFBVLIA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status sat)
(declare-fun x0 () (_ BitVec 10))
; COMMAND-LINE: --unconstrained-simp --no-check-models
(set-logic QF_AUFBVLIA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status sat)
(declare-fun x0 () (_ BitVec 10))
; COMMAND-LINE: --unconstrained-simp --no-check-models
(set-logic QF_AUFBVLIA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status unsat)
(declare-fun x0 () (_ BitVec 10))
; COMMAND-LINE: --unconstrained-simp --no-check-models
(set-logic QF_AUFBVLIA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status sat)
(declare-fun x0 () (_ BitVec 10))
; COMMAND-LINE: --unconstrained-simp --no-check-models
(set-logic QF_AUFBVLIA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status unsat)
(declare-fun x0 () (_ BitVec 10))
; COMMAND-LINE: --unconstrained-simp --no-check-models
(set-logic QF_AUFBVLIA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status sat)
(declare-fun x0 () (_ BitVec 10))
; COMMAND-LINE: --unconstrained-simp --no-check-models
(set-logic QF_AUFBVLIA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status sat)
(declare-fun x0 () (_ BitVec 10))
; COMMAND-LINE: --unconstrained-simp --no-check-models
(set-logic QF_AUFBVLIA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status unsat)
(declare-fun x0 () (_ BitVec 10))
; COMMAND-LINE: --unconstrained-simp --no-check-models
(set-logic QF_AUFBVLIA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status sat)
(declare-fun x0 () (_ BitVec 10))
; COMMAND-LINE: --unconstrained-simp --no-check-models
(set-logic QF_AUFBVLIA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status unsat)
(declare-fun x0 () (_ BitVec 10))
; COMMAND-LINE: --unconstrained-simp --no-check-models
(set-logic QF_AUFBVLIA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status sat)
(declare-fun v1 () Int)
; COMMAND-LINE: --unconstrained-simp --no-check-models
(set-logic QF_AUFBVLIA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status sat)
(declare-fun v1 () Int)
; COMMAND-LINE: --unconstrained-simp --no-check-models
(set-logic QF_AUFBVLIA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status sat)
(declare-fun v1 () Int)
; COMMAND-LINE: --unconstrained-simp --no-check-models
(set-logic QF_AUFBVLIA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status sat)
(declare-fun v1 () Int)
; COMMAND-LINE: --unconstrained-simp --no-check-models
(set-logic QF_AUFBVLIA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status sat)
(declare-fun v1 () Int)
; COMMAND-LINE: --unconstrained-simp --no-check-models
(set-logic QF_AUFBVLIA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status sat)
(declare-fun x0 () (_ BitVec 10))
(set-logic AUFBVDTLIRA)
;; produced by cvc4_15.drv ;;
(set-info :source |VC generated by SPARK 2014|)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category industrial)
(set-info :status unknown)
;;; generated by SMT-LIB2 driver
; EXPECT: unsat
(set-logic QF_NIA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :status unsat)
(declare-fun x () Int)
(declare-fun n () Int)
; COMMAND-LINE: -q
; EXPECT: sat
(set-logic QF_NRA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :status sat)
(declare-fun x () Real)
(declare-fun y () Real)
(set-logic QF_NIA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :status unsat)
(declare-fun n () Int)
; EXPECT: unsat
(set-logic QF_NIA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :status unsat)
(declare-fun n () Int)
; COMMAND-LINE: -q
; EXPECT: sat
(set-logic QF_NIA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :status sat)
(declare-fun n () Int)
(declare-fun x () Int)
Alberto Griggio
|)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "random")
(set-info :status sat)
(declare-fun x0 () Int)
(set-info :source |fuzzsmt|)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "random")
(set-info :status sat)
(set-logic QF_AUFBV)
This benchmark was automatically translated into SMT-LIB format from
CVC format using CVC Lite
|)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "industrial")
(set-info :status unsat)
(set-info :difficulty | 0 |)
; EXPECT: (:reason-unknown incomplete)
; EXPECT: unsat
(set-option :print-success false)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
;(set-option :AUTO_CONFIG false)
;(set-option :MODEL_HIDE_UNUSED_PARTITIONS false)
;(set-option :MODEL_V2 true)
;(set-option :produce-unsat-cores true)
(set-option :incremental true)
(set-option :print-success false)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :status sat)
(set-option :produce-models true)
(set-logic ALL_SUPPORTED)
(set-logic ALL)
(set-option :strings-exp true)
(set-option :produce-models true)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :status unknown)
(declare-fun text () String)
(assert (= html_escape_table
(store (store (store (store (store ((as const (Array String String)) "A")
"&" "&")
- "\"" """)
+ "\\""" """)
"'" "'")
">" ">")
"<" "<")))
(assert (= html_escape_table_keys
(store (store (store (store (store ((as const (Array Int String)) "B")
0 "&")
- 1 "\"")
+ 1 "\\""")
2 "'")
3 ">")
4 "<")))
; EXPECT: sat
(set-logic QF_UFLRA)
(set-info :source |CPAchecker with bounded model checking on SV-COMP14 program using MathSAT5, submitted by Philipp Wendler, http://cpachecker.sosy-lab.org|)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "industrial")
Patrice Godefroid, SAGE (systematic dynamic test generation)
For more information: http://research.microsoft.com/en-us/um/people/pg/public_psfiles/ndss2008.pdf
|)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "industrial")
(set-info :status unknown)
(declare-fun x () (_ BitVec 32))
(set-logic QF_AUFBVLIA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status unsat)
(declare-fun x0 () (_ BitVec 10))
; COMMAND-LINE: --fmf-fun-rlv --no-check-models
; EXPECT: sat
-(set-info :smt-lib-version 2.5)
+(set-info :smt-lib-version 2.6)
(set-option :produce-models true)
(set-logic ALL)
-(declare-datatypes () ((a0(c0$0)(c0$1(c0$1$0 String)(c0$1$1 Int))(c0$2(c0$2$0 Bool)(c0$2$1 Int)(c0$2$2 String)))
- (a1(c1$0)(c1$1)(c1$2))
- (a2(c2$0(c2$0$0 Int)(c2$0$1 a0)(c2$0$2 String)(c2$0$3 a3)(c2$0$4 String)(c2$0$5 Bool)))
- (a3(c3$0(c3$0$0 a7)(c3$0$1 a1)(c3$0$2 a5)(c3$0$3 a6)(c3$0$4 Int)(c3$0$5 Bool)(c3$0$6 Bool))(c3$1(c3$1$0 String)))
- (a4(c4$0(c4$0$0 String)(c4$0$1 a2)(c4$0$2 String))(c4$1(c4$1$0 a0)(c4$1$1 a4)(c4$1$2 a4)(c4$1$3 a7))(c4$2))
- (a5(c5$0(c5$0$0 a2))(c5$1)(c5$2)(c5$3(c5$3$0 a0))(c5$4)(c5$5(c5$5$0 a4)(c5$5$1 Int))(c5$6))
- (a6(c6$0(c6$0$0 a7)(c6$0$1 a7)(c6$0$2 String))(c6$1)(c6$2)(c6$3)(c6$4)(c6$5)(c6$6))
- (a7(c7$0(c7$0$0 a2)(c7$0$1 Int))(c7$1(c7$1$0 a4)(c7$1$1 Int)(c7$1$2 Bool)))))
+(declare-datatypes ((a0 0)(a1 0)(a2 0)(a3 0)(a4 0)(a5 0)(a6 0)(a7 0)) (((c0$0) (c0$1 (c0$1$0 String) (c0$1$1 Int)) (c0$2 (c0$2$0 Bool) (c0$2$1 Int) (c0$2$2 String)))((c1$0) (c1$1) (c1$2))((c2$0 (c2$0$0 Int) (c2$0$1 a0) (c2$0$2 String) (c2$0$3 a3) (c2$0$4 String) (c2$0$5 Bool)))((c3$0 (c3$0$0 a7) (c3$0$1 a1) (c3$0$2 a5) (c3$0$3 a6) (c3$0$4 Int) (c3$0$5 Bool) (c3$0$6 Bool)) (c3$1 (c3$1$0 String)))((c4$0 (c4$0$0 String) (c4$0$1 a2) (c4$0$2 String)) (c4$1 (c4$1$0 a0) (c4$1$1 a4) (c4$1$2 a4) (c4$1$3 a7)) (c4$2))((c5$0 (c5$0$0 a2)) (c5$1) (c5$2) (c5$3 (c5$3$0 a0)) (c5$4) (c5$5 (c5$5$0 a4) (c5$5$1 Int)) (c5$6))((c6$0 (c6$0$0 a7) (c6$0$1 a7) (c6$0$2 String)) (c6$1) (c6$2) (c6$3) (c6$4) (c6$5) (c6$6))((c7$0 (c7$0$0 a2) (c7$0$1 Int)) (c7$1 (c7$1$0 a4) (c7$1$1 Int) (c7$1$2 Bool)))))
(define-funs-rec ((f0((v0 a6))a4))
(c4$2))
(check-sat)
; EXPECT: sat\r
; EXPECT: sat\r
; EXPECT: sat\r
-(set-info :smt-lib-version 2.5)\r
+(set-info :smt-lib-version 2.6)\r
(set-option :produce-models true)\r
(set-logic ALL)\r
-(declare-datatypes () ((a0(c0$0)(c0$1)(c0$2)(c0$3(c0$3$0 a8)(c0$3$1 Int))(c0$4(c0$4$0 a5)(c0$4$1 a6))(c0$5)(c0$6)(c0$7)(c0$8))(a1(c1$0)(c1$1(c1$1$0 a4)(c1$1$1 Bool)(c1$1$2 a6)(c1$1$3 a4)(c1$1$4 ab)(c1$1$5 Int)(c1$1$6 a0))(c1$2)(c1$3)(c1$4)(c1$5(c1$5$0 a7))(c1$6(c1$6$0 String)(c1$6$1 a4)(c1$6$2 a4)(c1$6$3 a0))(c1$7))(a2(c2$0)(c2$1(c2$1$0 aa)(c2$1$1 aa)(c2$1$2 a1)(c2$1$3 a0)(c2$1$4 a0)(c2$1$5 a0)(c2$1$6 a9))(c2$2(c2$2$0 a5)(c2$2$1 ab))(c2$3(c2$3$0 Bool)(c2$3$1 a7)(c2$3$2 a3)(c2$3$3 Bool)(c2$3$4 a0)(c2$3$5 String))(c2$4))(a3(c3$0(c3$0$0 a7))(c3$1)(c3$2)(c3$3)(c3$4)(c3$5)(c3$6)(c3$7)(c3$8)(c3$9)(c3$a)(c3$b)(c3$c))(a4(c4$0(c4$0$0 a2)(c4$0$1 a1)(c4$0$2 Bool)(c4$0$3 String)(c4$0$4 a3)(c4$0$5 Int)(c4$0$6 a2)))(a5(c5$0)(c5$1)(c5$2(c5$2$0 String))(c5$3)(c5$4)(c5$5)(c5$6(c5$6$0 a0)(c5$6$1 a6)(c5$6$2 a3)(c5$6$3 a3)(c5$6$4 a9))(c5$7))(a6(c6$0)(c6$1(c6$1$0 a7))(c6$2)(c6$3)(c6$4(c6$4$0 a7)(c6$4$1 a3)(c6$4$2 a4))(c6$5(c6$5$0 a9)(c6$5$1 a9)(c6$5$2 a7)(c6$5$3 a6)(c6$5$4 ab)(c6$5$5 a5)(c6$5$6 a3)(c6$5$7 aa))(c6$6)(c6$7)(c6$8)(c6$9)(c6$a)(c6$b)(c6$c))(a7(c7$0)(c7$1)(c7$2)(c7$3(c7$3$0 a8)(c7$3$1 Bool)(c7$3$2 Int)(c7$3$3 a5)(c7$3$4 a8))(c7$4)(c7$5)(c7$6)(c7$7)(c7$8(c7$8$0 a5)(c7$8$1 a1)))(a8(c8$0(c8$0$0 a6)(c8$0$1 ab)(c8$0$2 ab)(c8$0$3 a1)(c8$0$4 Bool))(c8$1(c8$1$0 a4)(c8$1$1 Bool)(c8$1$2 a2)(c8$1$3 String)(c8$1$4 Bool)))(a9(c9$0(c9$0$0 String))(c9$1(c9$1$0 String)(c9$1$1 ab))(c9$2(c9$2$0 a5)(c9$2$1 a9))(c9$3(c9$3$0 String)(c9$3$1 a8)(c9$3$2 a6))(c9$4)(c9$5))(aa(ca$0(ca$0$0 String)(ca$0$1 a3)(ca$0$2 a9)(ca$0$3 a3)(ca$0$4 Bool)(ca$0$5 a1)(ca$0$6 a1)(ca$0$7 a4))(ca$1)(ca$2(ca$2$0 a4)(ca$2$1 String)(ca$2$2 aa)(ca$2$3 ab)))(ab(cb$0(cb$0$0 a5)(cb$0$1 a2)(cb$0$2 a3)(cb$0$3 aa)(cb$0$4 Bool))(cb$1(cb$1$0 a0))(cb$2)(cb$3)(cb$4)(cb$5)(cb$6)(cb$7(cb$7$0 String)(cb$7$1 a0)(cb$7$2 a7)(cb$7$3 ab)(cb$7$4 aa)(cb$7$5 a8))(cb$8))))\r
+(declare-datatypes ((a0 0)(a1 0)(a2 0)(a3 0)(a4 0)(a5 0)(a6 0)(a7 0)(a8 0)(a9 0)(aa 0)(ab 0)) (((c0$0) (c0$1) (c0$2) (c0$3 (c0$3$0 a8) (c0$3$1 Int)) (c0$4 (c0$4$0 a5) (c0$4$1 a6)) (c0$5) (c0$6) (c0$7) (c0$8))((c1$0) (c1$1 (c1$1$0 a4) (c1$1$1 Bool) (c1$1$2 a6) (c1$1$3 a4) (c1$1$4 ab) (c1$1$5 Int) (c1$1$6 a0)) (c1$2) (c1$3) (c1$4) (c1$5 (c1$5$0 a7)) (c1$6 (c1$6$0 String) (c1$6$1 a4) (c1$6$2 a4) (c1$6$3 a0)) (c1$7))((c2$0) (c2$1 (c2$1$0 aa) (c2$1$1 aa) (c2$1$2 a1) (c2$1$3 a0) (c2$1$4 a0) (c2$1$5 a0) (c2$1$6 a9)) (c2$2 (c2$2$0 a5) (c2$2$1 ab)) (c2$3 (c2$3$0 Bool) (c2$3$1 a7) (c2$3$2 a3) (c2$3$3 Bool) (c2$3$4 a0) (c2$3$5 String)) (c2$4))((c3$0 (c3$0$0 a7)) (c3$1) (c3$2) (c3$3) (c3$4) (c3$5) (c3$6) (c3$7) (c3$8) (c3$9) (c3$a) (c3$b) (c3$c))((c4$0 (c4$0$0 a2) (c4$0$1 a1) (c4$0$2 Bool) (c4$0$3 String) (c4$0$4 a3) (c4$0$5 Int) (c4$0$6 a2)))((c5$0) (c5$1) (c5$2 (c5$2$0 String)) (c5$3) (c5$4) (c5$5) (c5$6 (c5$6$0 a0) (c5$6$1 a6) (c5$6$2 a3) (c5$6$3 a3) (c5$6$4 a9)) (c5$7))((c6$0) (c6$1 (c6$1$0 a7)) (c6$2) (c6$3) (c6$4 (c6$4$0 a7) (c6$4$1 a3) (c6$4$2 a4)) (c6$5 (c6$5$0 a9) (c6$5$1 a9) (c6$5$2 a7) (c6$5$3 a6) (c6$5$4 ab) (c6$5$5 a5) (c6$5$6 a3) (c6$5$7 aa)) (c6$6) (c6$7) (c6$8) (c6$9) (c6$a) (c6$b) (c6$c))((c7$0) (c7$1) (c7$2) (c7$3 (c7$3$0 a8) (c7$3$1 Bool) (c7$3$2 Int) (c7$3$3 a5) (c7$3$4 a8)) (c7$4) (c7$5) (c7$6) (c7$7) (c7$8 (c7$8$0 a5) (c7$8$1 a1)))((c8$0 (c8$0$0 a6) (c8$0$1 ab) (c8$0$2 ab) (c8$0$3 a1) (c8$0$4 Bool)) (c8$1 (c8$1$0 a4) (c8$1$1 Bool) (c8$1$2 a2) (c8$1$3 String) (c8$1$4 Bool)))((c9$0 (c9$0$0 String)) (c9$1 (c9$1$0 String) (c9$1$1 ab)) (c9$2 (c9$2$0 a5) (c9$2$1 a9)) (c9$3 (c9$3$0 String) (c9$3$1 a8) (c9$3$2 a6)) (c9$4) (c9$5))((ca$0 (ca$0$0 String) (ca$0$1 a3) (ca$0$2 a9) (ca$0$3 a3) (ca$0$4 Bool) (ca$0$5 a1) (ca$0$6 a1) (ca$0$7 a4)) (ca$1) (ca$2 (ca$2$0 a4) (ca$2$1 String) (ca$2$2 aa) (ca$2$3 ab)))((cb$0 (cb$0$0 a5) (cb$0$1 a2) (cb$0$2 a3) (cb$0$3 aa) (cb$0$4 Bool)) (cb$1 (cb$1$0 a0)) (cb$2) (cb$3) (cb$4) (cb$5) (cb$6) (cb$7 (cb$7$0 String) (cb$7$1 a0) (cb$7$2 a7) (cb$7$3 ab) (cb$7$4 aa) (cb$7$5 a8)) (cb$8))))\r
(push 1)\r
(declare-fun v0() a0)\r
(push 1)\r
Boogie/Spec# benchmarks.
This benchmark was translated by Michal Moskal.
|)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "industrial")
(set-info :status unsat)
(declare-fun InRange (Int Int) Bool)
; EXPECT: sat
(set-logic UFDTLIA)
-(set-info :smt-lib-version 2.5)
+(set-info :smt-lib-version 2.6)
(define-funs-rec
(
)
)
-(declare-datatypes (T) ( (List (Nil) (Cstr (head T) (tail List) ) ) ) )
-(declare-datatypes (T S) ( (Pair (Pair (first T) (second S)) ) ) )
+(declare-datatypes ((List 1)) ((par (T)((Nil) (Cstr (head T) (tail (List T)))))))
+(declare-datatypes ((Pair 2)) ((par (T S)((Pair (first T) (second S))))))
(define-funs-rec
(
; COMMAND-LINE: --finite-model-find -q
; EXPECT: sat
(set-logic ALL_SUPPORTED)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "unknown")
(set-info :status sat)
-(declare-datatypes ()
-((UNIT (Unit))
-))
-(declare-datatypes ()
-((BOOL (Truth) (Falsity))
-))
+(declare-datatype UNIT ((Unit)))
+(declare-datatype BOOL ((Truth) (Falsity)))
(declare-sort resource$type 0)
(declare-sort process$type 0)
(declare-fun null () resource$type)
-; REQUIRES: symfpu\r
-; COMMAND-LINE: --fp-exp\r
-; EXPECT: unsat\r
-\r
-(set-logic FP)\r
-(set-info :source |Written by Mathias Preiner for issue #2932|)\r
-(set-info :smt-lib-version 2.5)\r
-(set-info :category crafted)\r
-(set-info :status unsat)\r
-\r
-(define-sort FP () (_ FloatingPoint 3 5))\r
-(declare-const t FP)\r
-(assert\r
- (distinct\r
- (= t (fp.roundToIntegral RNA t)) \r
- (exists ((x FP)) (= (fp.roundToIntegral RNA x) t)) \r
- )\r
-)\r
-(check-sat)\r
-(exit)\r
+; REQUIRES: symfpu
+; COMMAND-LINE: --fp-exp
+; EXPECT: unsat
+
+(set-logic FP)
+(set-info :source |Written by Mathias Preiner for issue #2932|)
+(set-info :smt-lib-version 2.6)
+(set-info :category crafted)
+(set-info :status unsat)
+
+(define-sort FP () (_ FloatingPoint 3 5))
+(declare-const t FP)
+(assert
+ (distinct
+ (= t (fp.roundToIntegral RNA t))
+ (exists ((x FP)) (= (fp.roundToIntegral RNA x) t))
+ )
+)
+(check-sat)
+(exit)
http://www.cs.bham.ac.uk/~vxs/quasigroups/benchmark/
|)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status sat)
(declare-sort U 0)
; COMMAND-LINE: --incremental --nl-ext --fmf-fun-rlv --no-check-models
(set-logic UFNIA)
-(set-info :smt-lib-version 2.5)
+(set-info :smt-lib-version 2.6)
; EXPECT: sat
(declare-fun fixedAdd() Int)
|)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "industrial")
(set-info :status sat)
(declare-fun skoCOSS () Real)
|)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "industrial")
(set-info :status sat)
(declare-fun skoX () Real)
|)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "industrial")
(set-info :status sat)
(declare-fun skoX () Real)
(set-logic UFNIA)
(set-info :status unsat)
(set-info :source |Benchmarks from the paper: "Extending Sledgehammer with SMT Solvers" by Jasmin Blanchette, Sascha Bohme, and Lawrence C. Paulson, CADE 2011. Translated to SMT2 by Andrew Reynolds and Morgan Deters.|)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "industrial")
(declare-sort S1 0)
(declare-sort S2 0)
; EXPECT: unsat
(set-logic UFNIA)
(set-info :source |Benchmarks from the paper: "Extending Sledgehammer with SMT Solvers" by Jasmin Blanchette, Sascha Bohme, and Lawrence C. Paulson, CADE 2011. Translated to SMT2 by Andrew Reynolds and Morgan Deters.|)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "industrial")
(set-info :status unsat)
(declare-sort S1 0)
|)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "industrial")
(set-info :status sat)
(declare-fun skoX () Real)
(set-logic UFNIA)
(set-info :status unsat)
(set-info :source |Benchmarks from the paper: "Extending Sledgehammer with SMT Solvers" by Jasmin Blanchette, Sascha Bohme, and Lawrence C. Paulson, CADE 2011. Translated to SMT2 by Andrew Reynolds and Morgan Deters.|)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "industrial")
(declare-sort S1 0)
(declare-sort S2 0)
This benchmark was obtained by trying to find a finite model of a first-order
formula (Albert Oliveras).
|)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status unsat)
(declare-sort U 0)
Boogie/Spec# benchmarks.
This benchmark was translated by Michal Moskal.
|)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "industrial")
(set-info :status unsat)
(declare-fun boolIff (Int Int) Int)
Boogie/Spec# benchmarks.
This benchmark was translated by Michal Moskal.
|)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "industrial")
(set-info :status unsat)
(declare-fun InRange (Int Int) Bool)
; COMMAND-LINE: --full-saturate-quant
; EXPECT: unsat
(set-logic AUFLIA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status unsat)
(declare-sort Index 0)
(set-logic AUFLIA)
(set-info :source | SMT-COMP'06 organizers |)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "check")
(set-info :status unsat)
(set-info :notes |This benchmark is designed to check if the DP supports bignumbers.|)
These benchmarks stem from an evaluation described in Wintersteiger, Hamadi, de Moura: Efficiently solving quantified bit-vector formulas, FMSD 42(1), 2013.
The hardware models that were used are from the VCEGAR benchmark suite (see www.cprover.org/hardware/).
|)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "industrial")
(set-info :status unsat)
(assert (forall ((Verilog__main.reset_64_0 Bool)) (forall ((Verilog__main.rst_64_0 Bool)) (forall ((Verilog__main.usb_rst_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.hold_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.stuff_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.sft_done_e_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.sft_done_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.sft_done_r_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.one_cnt_64_0 (_ BitVec 3))) (forall ((Verilog__main.i_tx_phy.eop_done_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.append_eop_sync3_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.clk_64_0 Bool)) (forall ((Verilog__main.clk_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.rst_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.fs_ce_64_0 Bool)) (forall ((Verilog__main.fs_ce_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.phy_mode_64_0 Bool)) (forall ((Verilog__main.phy_tx_mode_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.txdp_64_0 Bool)) (forall ((Verilog__main.txdp_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.txdn_64_0 Bool)) (forall ((Verilog__main.txdn_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.txoe_64_0 Bool)) (forall ((Verilog__main.txoe_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.DataOut_i_64_0 (_ BitVec 8))) (forall ((Verilog__main.DataOut_i_64_0 (_ BitVec 8))) (forall ((Verilog__main.i_tx_phy.TxValid_i_64_0 Bool)) (forall ((Verilog__main.TxValid_i_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.TxReady_o_64_0 Bool)) (forall ((Verilog__main.TxReady_o_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.RxActive_o_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.rx_active_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.RxValid_o_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.rx_valid_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.RxError_o_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.DataIn_o_64_0 (_ BitVec 8))) (forall ((Verilog__main.i_rx_phy.hold_reg_64_0 (_ BitVec 8))) (forall ((Verilog__main.i_rx_phy.LineState_64_0 (_ BitVec 2))) (forall ((Verilog__main.i_rx_phy.rxdp_s1_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.rxdn_s1_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.k_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.rxdp_s_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.rxdn_s_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.j_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.se0_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.lock_en_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.rx_en_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.change_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.rxdp_s1r_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.rxdn_s1r_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.drop_bit_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.one_cnt_64_0 (_ BitVec 3))) (forall ((Verilog__main.i_rx_phy.clk_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.rst_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.fs_ce_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.rxd_64_0 Bool)) (forall ((Verilog__main.rxd_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.rxdp_64_0 Bool)) (forall ((Verilog__main.rxdp_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.rxdn_64_0 Bool)) (forall ((Verilog__main.rxdn_64_0 Bool)) (forall ((Verilog__main.DataIn_o_64_0 (_ BitVec 8))) (forall ((Verilog__main.RxValid_o_64_0 Bool)) (forall ((Verilog__main.RxActive_o_64_0 Bool)) (forall ((Verilog__main.RxError_o_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.RxEn_i_64_0 Bool)) (forall ((Verilog__main.LineState_o_64_0 (_ BitVec 2))) (forall ((Verilog__main.reset_64_1 Bool)) (forall ((Verilog__main.rst_64_1 Bool)) (forall ((Verilog__main.usb_rst_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.hold_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.stuff_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.sft_done_e_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.sft_done_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.sft_done_r_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.one_cnt_64_1 (_ BitVec 3))) (forall ((Verilog__main.i_tx_phy.eop_done_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.append_eop_sync3_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.clk_64_1 Bool)) (forall ((Verilog__main.clk_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.rst_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.fs_ce_64_1 Bool)) (forall ((Verilog__main.fs_ce_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.phy_mode_64_1 Bool)) (forall ((Verilog__main.phy_tx_mode_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.txdp_64_1 Bool)) (forall ((Verilog__main.txdp_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.txdn_64_1 Bool)) (forall ((Verilog__main.txdn_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.txoe_64_1 Bool)) (forall ((Verilog__main.txoe_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.DataOut_i_64_1 (_ BitVec 8))) (forall ((Verilog__main.DataOut_i_64_1 (_ BitVec 8))) (forall ((Verilog__main.i_tx_phy.TxValid_i_64_1 Bool)) (forall ((Verilog__main.TxValid_i_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.TxReady_o_64_1 Bool)) (forall ((Verilog__main.TxReady_o_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.RxActive_o_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.rx_active_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.RxValid_o_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.rx_valid_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.RxError_o_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.DataIn_o_64_1 (_ BitVec 8))) (forall ((Verilog__main.i_rx_phy.hold_reg_64_1 (_ BitVec 8))) (forall ((Verilog__main.i_rx_phy.LineState_64_1 (_ BitVec 2))) (forall ((Verilog__main.i_rx_phy.rxdp_s1_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.rxdn_s1_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.k_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.rxdp_s_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.rxdn_s_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.j_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.se0_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.lock_en_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.rx_en_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.change_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.rxdp_s1r_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.rxdn_s1r_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.drop_bit_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.one_cnt_64_1 (_ BitVec 3))) (forall ((Verilog__main.i_rx_phy.clk_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.rst_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.fs_ce_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.rxd_64_1 Bool)) (forall ((Verilog__main.rxd_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.rxdp_64_1 Bool)) (forall ((Verilog__main.rxdp_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.rxdn_64_1 Bool)) (forall ((Verilog__main.rxdn_64_1 Bool)) (forall ((Verilog__main.DataIn_o_64_1 (_ BitVec 8))) (forall ((Verilog__main.RxValid_o_64_1 Bool)) (forall ((Verilog__main.RxActive_o_64_1 Bool)) (forall ((Verilog__main.RxError_o_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.RxEn_i_64_1 Bool)) (forall ((Verilog__main.LineState_o_64_1 (_ BitVec 2))) (forall ((Verilog__main.reset_64_2 Bool)) (forall ((Verilog__main.rst_64_2 Bool)) (forall ((Verilog__main.usb_rst_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.hold_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.stuff_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.sft_done_e_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.sft_done_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.sft_done_r_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.one_cnt_64_2 (_ BitVec 3))) (forall ((Verilog__main.i_tx_phy.eop_done_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.append_eop_sync3_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.clk_64_2 Bool)) (forall ((Verilog__main.clk_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.rst_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.fs_ce_64_2 Bool)) (forall ((Verilog__main.fs_ce_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.phy_mode_64_2 Bool)) (forall ((Verilog__main.phy_tx_mode_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.txdp_64_2 Bool)) (forall ((Verilog__main.txdp_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.txdn_64_2 Bool)) (forall ((Verilog__main.txdn_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.txoe_64_2 Bool)) (forall ((Verilog__main.txoe_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.DataOut_i_64_2 (_ BitVec 8))) (forall ((Verilog__main.DataOut_i_64_2 (_ BitVec 8))) (forall ((Verilog__main.i_tx_phy.TxValid_i_64_2 Bool)) (forall ((Verilog__main.TxValid_i_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.TxReady_o_64_2 Bool)) (forall ((Verilog__main.TxReady_o_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.RxActive_o_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.rx_active_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.RxValid_o_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.rx_valid_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.RxError_o_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.DataIn_o_64_2 (_ BitVec 8))) (forall ((Verilog__main.i_rx_phy.hold_reg_64_2 (_ BitVec 8))) (forall ((Verilog__main.i_rx_phy.LineState_64_2 (_ BitVec 2))) (forall ((Verilog__main.i_rx_phy.rxdp_s1_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.rxdn_s1_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.k_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.rxdp_s_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.rxdn_s_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.j_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.se0_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.lock_en_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.rx_en_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.change_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.rxdp_s1r_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.rxdn_s1r_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.drop_bit_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.one_cnt_64_2 (_ BitVec 3))) (forall ((Verilog__main.i_rx_phy.clk_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.rst_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.fs_ce_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.rxd_64_2 Bool)) (forall ((Verilog__main.rxd_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.rxdp_64_2 Bool)) (forall ((Verilog__main.rxdp_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.rxdn_64_2 Bool)) (forall ((Verilog__main.rxdn_64_2 Bool)) (forall ((Verilog__main.DataIn_o_64_2 (_ BitVec 8))) (forall ((Verilog__main.RxValid_o_64_2 Bool)) (forall ((Verilog__main.RxActive_o_64_2 Bool)) (forall ((Verilog__main.RxError_o_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.RxEn_i_64_2 Bool)) (forall ((Verilog__main.LineState_o_64_2 (_ BitVec 2))) (forall ((Verilog__main.i_tx_phy.sd_bs_o_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.sd_nrzi_o_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.append_eop_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.append_eop_sync1_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.append_eop_sync2_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.txoe_r1_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.txoe_r2_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.state_64_0 (_ BitVec 3))) (forall ((Verilog__main.i_tx_phy.tx_ready_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.tx_ready_d_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.ld_sop_d_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.ld_data_d_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.ld_eop_d_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.tx_ip_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.tx_ip_sync_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.bit_cnt_64_0 (_ BitVec 3))) (forall ((Verilog__main.i_tx_phy.hold_reg_64_0 (_ BitVec 8))) (forall ((Verilog__main.i_tx_phy.sd_raw_o_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.data_done_64_0 Bool)) (forall ((Verilog__main.i_tx_phy.ld_data_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.rxd_t1_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.rxd_s1_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.rxd_s_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.rxdp_t1_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.rxdn_t1_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.synced_d_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.bit_cnt_64_0 (_ BitVec 3))) (forall ((Verilog__main.i_rx_phy.rx_valid1_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.shift_en_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.sd_r_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.sd_nrzi_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.dpll_state_64_0 (_ BitVec 2))) (forall ((Verilog__main.i_rx_phy.fs_ce_d_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.fs_ce_r1_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.fs_ce_r2_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.fs_ce_r3_64_0 Bool)) (forall ((Verilog__main.i_rx_phy.fs_state_64_0 (_ BitVec 3))) (forall ((Verilog__main.i_rx_phy.rx_valid_r_64_0 Bool)) (forall ((Verilog__main.rst_cnt_64_0 (_ BitVec 5))) (forall ((Verilog__main.i_tx_phy.sd_bs_o_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.sd_nrzi_o_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.append_eop_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.append_eop_sync1_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.append_eop_sync2_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.txoe_r1_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.txoe_r2_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.state_64_1 (_ BitVec 3))) (forall ((Verilog__main.i_tx_phy.tx_ready_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.tx_ready_d_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.ld_sop_d_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.ld_data_d_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.ld_eop_d_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.tx_ip_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.tx_ip_sync_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.bit_cnt_64_1 (_ BitVec 3))) (forall ((Verilog__main.i_tx_phy.hold_reg_64_1 (_ BitVec 8))) (forall ((Verilog__main.i_tx_phy.sd_raw_o_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.data_done_64_1 Bool)) (forall ((Verilog__main.i_tx_phy.ld_data_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.rxd_t1_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.rxd_s1_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.rxd_s_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.rxdp_t1_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.rxdn_t1_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.synced_d_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.bit_cnt_64_1 (_ BitVec 3))) (forall ((Verilog__main.i_rx_phy.rx_valid1_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.shift_en_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.sd_r_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.sd_nrzi_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.dpll_state_64_1 (_ BitVec 2))) (forall ((Verilog__main.i_rx_phy.fs_ce_d_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.fs_ce_r1_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.fs_ce_r2_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.fs_ce_r3_64_1 Bool)) (forall ((Verilog__main.i_rx_phy.fs_state_64_1 (_ BitVec 3))) (forall ((Verilog__main.i_rx_phy.rx_valid_r_64_1 Bool)) (forall ((Verilog__main.rst_cnt_64_1 (_ BitVec 5))) (forall ((Verilog__main.i_tx_phy.sd_bs_o_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.sd_nrzi_o_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.append_eop_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.append_eop_sync1_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.append_eop_sync2_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.txoe_r1_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.txoe_r2_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.state_64_2 (_ BitVec 3))) (forall ((Verilog__main.i_tx_phy.tx_ready_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.tx_ready_d_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.ld_sop_d_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.ld_data_d_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.ld_eop_d_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.tx_ip_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.tx_ip_sync_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.bit_cnt_64_2 (_ BitVec 3))) (forall ((Verilog__main.i_tx_phy.hold_reg_64_2 (_ BitVec 8))) (forall ((Verilog__main.i_tx_phy.sd_raw_o_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.data_done_64_2 Bool)) (forall ((Verilog__main.i_tx_phy.ld_data_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.rxd_t1_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.rxd_s1_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.rxd_s_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.rxdp_t1_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.rxdn_t1_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.synced_d_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.bit_cnt_64_2 (_ BitVec 3))) (forall ((Verilog__main.i_rx_phy.rx_valid1_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.shift_en_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.sd_r_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.sd_nrzi_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.dpll_state_64_2 (_ BitVec 2))) (forall ((Verilog__main.i_rx_phy.fs_ce_d_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.fs_ce_r1_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.fs_ce_r2_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.fs_ce_r3_64_2 Bool)) (forall ((Verilog__main.i_rx_phy.fs_state_64_2 (_ BitVec 3))) (forall ((Verilog__main.i_rx_phy.rx_valid_r_64_2 Bool)) (forall ((Verilog__main.rst_cnt_64_2 (_ BitVec 5))) (exists ((Verilog__main.reset_64_0_39_ Bool)) (exists ((Verilog__main.rst_64_0_39_ Bool)) (exists ((Verilog__main.usb_rst_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.hold_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.stuff_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.sft_done_e_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.sft_done_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.sft_done_r_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.one_cnt_64_0_39_ (_ BitVec 3))) (exists ((Verilog__main.i_tx_phy.eop_done_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.append_eop_sync3_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.clk_64_0_39_ Bool)) (exists ((Verilog__main.clk_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.rst_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.fs_ce_64_0_39_ Bool)) (exists ((Verilog__main.fs_ce_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.phy_mode_64_0_39_ Bool)) (exists ((Verilog__main.phy_tx_mode_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.txdp_64_0_39_ Bool)) (exists ((Verilog__main.txdp_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.txdn_64_0_39_ Bool)) (exists ((Verilog__main.txdn_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.txoe_64_0_39_ Bool)) (exists ((Verilog__main.txoe_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.DataOut_i_64_0_39_ (_ BitVec 8))) (exists ((Verilog__main.DataOut_i_64_0_39_ (_ BitVec 8))) (exists ((Verilog__main.i_tx_phy.TxValid_i_64_0_39_ Bool)) (exists ((Verilog__main.TxValid_i_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.TxReady_o_64_0_39_ Bool)) (exists ((Verilog__main.TxReady_o_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.RxActive_o_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rx_active_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.RxValid_o_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rx_valid_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.RxError_o_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.DataIn_o_64_0_39_ (_ BitVec 8))) (exists ((Verilog__main.i_rx_phy.hold_reg_64_0_39_ (_ BitVec 8))) (exists ((Verilog__main.i_rx_phy.LineState_64_0_39_ (_ BitVec 2))) (exists ((Verilog__main.i_rx_phy.rxdp_s1_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxdn_s1_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.k_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxdp_s_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxdn_s_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.j_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.se0_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.lock_en_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rx_en_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.change_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxdp_s1r_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxdn_s1r_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.drop_bit_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.one_cnt_64_0_39_ (_ BitVec 3))) (exists ((Verilog__main.i_rx_phy.clk_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rst_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.fs_ce_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxd_64_0_39_ Bool)) (exists ((Verilog__main.rxd_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxdp_64_0_39_ Bool)) (exists ((Verilog__main.rxdp_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxdn_64_0_39_ Bool)) (exists ((Verilog__main.rxdn_64_0_39_ Bool)) (exists ((Verilog__main.DataIn_o_64_0_39_ (_ BitVec 8))) (exists ((Verilog__main.RxValid_o_64_0_39_ Bool)) (exists ((Verilog__main.RxActive_o_64_0_39_ Bool)) (exists ((Verilog__main.RxError_o_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.RxEn_i_64_0_39_ Bool)) (exists ((Verilog__main.LineState_o_64_0_39_ (_ BitVec 2))) (exists ((Verilog__main.reset_64_1_39_ Bool)) (exists ((Verilog__main.rst_64_1_39_ Bool)) (exists ((Verilog__main.usb_rst_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.hold_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.stuff_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.sft_done_e_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.sft_done_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.sft_done_r_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.one_cnt_64_1_39_ (_ BitVec 3))) (exists ((Verilog__main.i_tx_phy.eop_done_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.append_eop_sync3_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.clk_64_1_39_ Bool)) (exists ((Verilog__main.clk_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.rst_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.fs_ce_64_1_39_ Bool)) (exists ((Verilog__main.fs_ce_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.phy_mode_64_1_39_ Bool)) (exists ((Verilog__main.phy_tx_mode_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.txdp_64_1_39_ Bool)) (exists ((Verilog__main.txdp_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.txdn_64_1_39_ Bool)) (exists ((Verilog__main.txdn_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.txoe_64_1_39_ Bool)) (exists ((Verilog__main.txoe_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.DataOut_i_64_1_39_ (_ BitVec 8))) (exists ((Verilog__main.DataOut_i_64_1_39_ (_ BitVec 8))) (exists ((Verilog__main.i_tx_phy.TxValid_i_64_1_39_ Bool)) (exists ((Verilog__main.TxValid_i_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.TxReady_o_64_1_39_ Bool)) (exists ((Verilog__main.TxReady_o_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.RxActive_o_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rx_active_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.RxValid_o_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rx_valid_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.RxError_o_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.DataIn_o_64_1_39_ (_ BitVec 8))) (exists ((Verilog__main.i_rx_phy.hold_reg_64_1_39_ (_ BitVec 8))) (exists ((Verilog__main.i_rx_phy.LineState_64_1_39_ (_ BitVec 2))) (exists ((Verilog__main.i_rx_phy.rxdp_s1_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxdn_s1_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.k_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxdp_s_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxdn_s_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.j_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.se0_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.lock_en_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rx_en_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.change_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxdp_s1r_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxdn_s1r_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.drop_bit_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.one_cnt_64_1_39_ (_ BitVec 3))) (exists ((Verilog__main.i_rx_phy.clk_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rst_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.fs_ce_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxd_64_1_39_ Bool)) (exists ((Verilog__main.rxd_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxdp_64_1_39_ Bool)) (exists ((Verilog__main.rxdp_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxdn_64_1_39_ Bool)) (exists ((Verilog__main.rxdn_64_1_39_ Bool)) (exists ((Verilog__main.DataIn_o_64_1_39_ (_ BitVec 8))) (exists ((Verilog__main.RxValid_o_64_1_39_ Bool)) (exists ((Verilog__main.RxActive_o_64_1_39_ Bool)) (exists ((Verilog__main.RxError_o_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.RxEn_i_64_1_39_ Bool)) (exists ((Verilog__main.LineState_o_64_1_39_ (_ BitVec 2))) (exists ((Verilog__main.i_tx_phy.sd_bs_o_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.sd_nrzi_o_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.append_eop_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.append_eop_sync1_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.append_eop_sync2_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.txoe_r1_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.txoe_r2_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.state_64_0_39_ (_ BitVec 3))) (exists ((Verilog__main.i_tx_phy.tx_ready_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.tx_ready_d_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.ld_sop_d_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.ld_data_d_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.ld_eop_d_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.tx_ip_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.tx_ip_sync_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.bit_cnt_64_0_39_ (_ BitVec 3))) (exists ((Verilog__main.i_tx_phy.hold_reg_64_0_39_ (_ BitVec 8))) (exists ((Verilog__main.i_tx_phy.sd_raw_o_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.data_done_64_0_39_ Bool)) (exists ((Verilog__main.i_tx_phy.ld_data_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxd_t1_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxd_s1_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxd_s_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxdp_t1_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxdn_t1_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.synced_d_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.bit_cnt_64_0_39_ (_ BitVec 3))) (exists ((Verilog__main.i_rx_phy.rx_valid1_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.shift_en_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.sd_r_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.sd_nrzi_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.dpll_state_64_0_39_ (_ BitVec 2))) (exists ((Verilog__main.i_rx_phy.fs_ce_d_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.fs_ce_r1_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.fs_ce_r2_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.fs_ce_r3_64_0_39_ Bool)) (exists ((Verilog__main.i_rx_phy.fs_state_64_0_39_ (_ BitVec 3))) (exists ((Verilog__main.i_rx_phy.rx_valid_r_64_0_39_ Bool)) (exists ((Verilog__main.rst_cnt_64_0_39_ (_ BitVec 5))) (exists ((Verilog__main.i_tx_phy.sd_bs_o_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.sd_nrzi_o_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.append_eop_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.append_eop_sync1_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.append_eop_sync2_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.txoe_r1_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.txoe_r2_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.state_64_1_39_ (_ BitVec 3))) (exists ((Verilog__main.i_tx_phy.tx_ready_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.tx_ready_d_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.ld_sop_d_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.ld_data_d_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.ld_eop_d_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.tx_ip_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.tx_ip_sync_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.bit_cnt_64_1_39_ (_ BitVec 3))) (exists ((Verilog__main.i_tx_phy.hold_reg_64_1_39_ (_ BitVec 8))) (exists ((Verilog__main.i_tx_phy.sd_raw_o_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.data_done_64_1_39_ Bool)) (exists ((Verilog__main.i_tx_phy.ld_data_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxd_t1_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxd_s1_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxd_s_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxdp_t1_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.rxdn_t1_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.synced_d_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.bit_cnt_64_1_39_ (_ BitVec 3))) (exists ((Verilog__main.i_rx_phy.rx_valid1_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.shift_en_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.sd_r_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.sd_nrzi_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.dpll_state_64_1_39_ (_ BitVec 2))) (exists ((Verilog__main.i_rx_phy.fs_ce_d_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.fs_ce_r1_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.fs_ce_r2_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.fs_ce_r3_64_1_39_ Bool)) (exists ((Verilog__main.i_rx_phy.fs_state_64_1_39_ (_ BitVec 3))) (exists ((Verilog__main.i_rx_phy.rx_valid_r_64_1_39_ Bool)) (exists ((Verilog__main.rst_cnt_64_1_39_ (_ BitVec 5))) (=> (and (and (= Verilog__main.reset_64_0 (and Verilog__main.rst_64_0 (not Verilog__main.usb_rst_64_0))) (and (= Verilog__main.i_tx_phy.hold_64_0 Verilog__main.i_tx_phy.stuff_64_0) (= Verilog__main.i_tx_phy.sft_done_e_64_0 (and Verilog__main.i_tx_phy.sft_done_64_0 (not Verilog__main.i_tx_phy.sft_done_r_64_0))) (= Verilog__main.i_tx_phy.stuff_64_0 (= Verilog__main.i_tx_phy.one_cnt_64_0 (_ bv6 3))) (= Verilog__main.i_tx_phy.eop_done_64_0 Verilog__main.i_tx_phy.append_eop_sync3_64_0)) (= Verilog__main.i_tx_phy.clk_64_0 Verilog__main.clk_64_0) (= Verilog__main.i_tx_phy.rst_64_0 Verilog__main.reset_64_0) (= Verilog__main.i_tx_phy.fs_ce_64_0 Verilog__main.fs_ce_64_0) (= Verilog__main.i_tx_phy.phy_mode_64_0 Verilog__main.phy_tx_mode_64_0) (= Verilog__main.i_tx_phy.txdp_64_0 Verilog__main.txdp_64_0) (= Verilog__main.i_tx_phy.txdn_64_0 Verilog__main.txdn_64_0) (= Verilog__main.i_tx_phy.txoe_64_0 Verilog__main.txoe_64_0) (= Verilog__main.i_tx_phy.DataOut_i_64_0 Verilog__main.DataOut_i_64_0) (= Verilog__main.i_tx_phy.TxValid_i_64_0 Verilog__main.TxValid_i_64_0) (= Verilog__main.i_tx_phy.TxReady_o_64_0 Verilog__main.TxReady_o_64_0) (and (= Verilog__main.i_rx_phy.RxActive_o_64_0 Verilog__main.i_rx_phy.rx_active_64_0) (= Verilog__main.i_rx_phy.RxValid_o_64_0 Verilog__main.i_rx_phy.rx_valid_64_0) (= Verilog__main.i_rx_phy.RxError_o_64_0 false) (= Verilog__main.i_rx_phy.DataIn_o_64_0 Verilog__main.i_rx_phy.hold_reg_64_0) (= Verilog__main.i_rx_phy.LineState_64_0 (concat (ite Verilog__main.i_rx_phy.rxdp_s1_64_0 (_ bv1 1) (_ bv0 1)) (ite Verilog__main.i_rx_phy.rxdn_s1_64_0 (_ bv1 1) (_ bv0 1)))) (= Verilog__main.i_rx_phy.k_64_0 (and (not Verilog__main.i_rx_phy.rxdp_s_64_0) Verilog__main.i_rx_phy.rxdn_s_64_0)) (= Verilog__main.i_rx_phy.j_64_0 (and Verilog__main.i_rx_phy.rxdp_s_64_0 (not Verilog__main.i_rx_phy.rxdn_s_64_0))) (= Verilog__main.i_rx_phy.se0_64_0 (and (not Verilog__main.i_rx_phy.rxdp_s_64_0) (not Verilog__main.i_rx_phy.rxdn_s_64_0))) (= Verilog__main.i_rx_phy.lock_en_64_0 Verilog__main.i_rx_phy.rx_en_64_0) (= Verilog__main.i_rx_phy.change_64_0 (or (xor Verilog__main.i_rx_phy.rxdp_s1r_64_0 Verilog__main.i_rx_phy.rxdp_s1_64_0) (xor Verilog__main.i_rx_phy.rxdn_s1r_64_0 Verilog__main.i_rx_phy.rxdn_s1_64_0))) (= Verilog__main.i_rx_phy.drop_bit_64_0 (= Verilog__main.i_rx_phy.one_cnt_64_0 (_ bv6 3)))) (= Verilog__main.i_rx_phy.clk_64_0 Verilog__main.clk_64_0) (= Verilog__main.i_rx_phy.rst_64_0 Verilog__main.reset_64_0) (= Verilog__main.i_rx_phy.fs_ce_64_0 Verilog__main.fs_ce_64_0) (= Verilog__main.i_rx_phy.rxd_64_0 Verilog__main.rxd_64_0) (= Verilog__main.i_rx_phy.rxdp_64_0 Verilog__main.rxdp_64_0) (= Verilog__main.i_rx_phy.rxdn_64_0 Verilog__main.rxdn_64_0) (= Verilog__main.i_rx_phy.DataIn_o_64_0 Verilog__main.DataIn_o_64_0) (= Verilog__main.i_rx_phy.RxValid_o_64_0 Verilog__main.RxValid_o_64_0) (= Verilog__main.i_rx_phy.RxActive_o_64_0 Verilog__main.RxActive_o_64_0) (= Verilog__main.i_rx_phy.RxError_o_64_0 Verilog__main.RxError_o_64_0) (= Verilog__main.i_rx_phy.RxEn_i_64_0 Verilog__main.txoe_64_0) (= Verilog__main.i_rx_phy.LineState_64_0 Verilog__main.LineState_o_64_0)) (and (= Verilog__main.reset_64_1 (and Verilog__main.rst_64_1 (not Verilog__main.usb_rst_64_1))) (and (= Verilog__main.i_tx_phy.hold_64_1 Verilog__main.i_tx_phy.stuff_64_1) (= Verilog__main.i_tx_phy.sft_done_e_64_1 (and Verilog__main.i_tx_phy.sft_done_64_1 (not Verilog__main.i_tx_phy.sft_done_r_64_1))) (= Verilog__main.i_tx_phy.stuff_64_1 (= Verilog__main.i_tx_phy.one_cnt_64_1 (_ bv6 3))) (= Verilog__main.i_tx_phy.eop_done_64_1 Verilog__main.i_tx_phy.append_eop_sync3_64_1)) (= Verilog__main.i_tx_phy.clk_64_1 Verilog__main.clk_64_1) (= Verilog__main.i_tx_phy.rst_64_1 Verilog__main.reset_64_1) (= Verilog__main.i_tx_phy.fs_ce_64_1 Verilog__main.fs_ce_64_1) (= Verilog__main.i_tx_phy.phy_mode_64_1 Verilog__main.phy_tx_mode_64_1) (= Verilog__main.i_tx_phy.txdp_64_1 Verilog__main.txdp_64_1) (= Verilog__main.i_tx_phy.txdn_64_1 Verilog__main.txdn_64_1) (= Verilog__main.i_tx_phy.txoe_64_1 Verilog__main.txoe_64_1) (= Verilog__main.i_tx_phy.DataOut_i_64_1 Verilog__main.DataOut_i_64_1) (= Verilog__main.i_tx_phy.TxValid_i_64_1 Verilog__main.TxValid_i_64_1) (= Verilog__main.i_tx_phy.TxReady_o_64_1 Verilog__main.TxReady_o_64_1) (and (= Verilog__main.i_rx_phy.RxActive_o_64_1 Verilog__main.i_rx_phy.rx_active_64_1) (= Verilog__main.i_rx_phy.RxValid_o_64_1 Verilog__main.i_rx_phy.rx_valid_64_1) (= Verilog__main.i_rx_phy.RxError_o_64_1 false) (= Verilog__main.i_rx_phy.DataIn_o_64_1 Verilog__main.i_rx_phy.hold_reg_64_1) (= Verilog__main.i_rx_phy.LineState_64_1 (concat (ite Verilog__main.i_rx_phy.rxdp_s1_64_1 (_ bv1 1) (_ bv0 1)) (ite Verilog__main.i_rx_phy.rxdn_s1_64_1 (_ bv1 1) (_ bv0 1)))) (= Verilog__main.i_rx_phy.k_64_1 (and (not Verilog__main.i_rx_phy.rxdp_s_64_1) Verilog__main.i_rx_phy.rxdn_s_64_1)) (= Verilog__main.i_rx_phy.j_64_1 (and Verilog__main.i_rx_phy.rxdp_s_64_1 (not Verilog__main.i_rx_phy.rxdn_s_64_1))) (= Verilog__main.i_rx_phy.se0_64_1 (and (not Verilog__main.i_rx_phy.rxdp_s_64_1) (not Verilog__main.i_rx_phy.rxdn_s_64_1))) (= Verilog__main.i_rx_phy.lock_en_64_1 Verilog__main.i_rx_phy.rx_en_64_1) (= Verilog__main.i_rx_phy.change_64_1 (or (xor Verilog__main.i_rx_phy.rxdp_s1r_64_1 Verilog__main.i_rx_phy.rxdp_s1_64_1) (xor Verilog__main.i_rx_phy.rxdn_s1r_64_1 Verilog__main.i_rx_phy.rxdn_s1_64_1))) (= Verilog__main.i_rx_phy.drop_bit_64_1 (= Verilog__main.i_rx_phy.one_cnt_64_1 (_ bv6 3)))) (= Verilog__main.i_rx_phy.clk_64_1 Verilog__main.clk_64_1) (= Verilog__main.i_rx_phy.rst_64_1 Verilog__main.reset_64_1) (= Verilog__main.i_rx_phy.fs_ce_64_1 Verilog__main.fs_ce_64_1) (= Verilog__main.i_rx_phy.rxd_64_1 Verilog__main.rxd_64_1) (= Verilog__main.i_rx_phy.rxdp_64_1 Verilog__main.rxdp_64_1) (= Verilog__main.i_rx_phy.rxdn_64_1 Verilog__main.rxdn_64_1) (= Verilog__main.i_rx_phy.DataIn_o_64_1 Verilog__main.DataIn_o_64_1) (= Verilog__main.i_rx_phy.RxValid_o_64_1 Verilog__main.RxValid_o_64_1) (= Verilog__main.i_rx_phy.RxActive_o_64_1 Verilog__main.RxActive_o_64_1) (= Verilog__main.i_rx_phy.RxError_o_64_1 Verilog__main.RxError_o_64_1) (= Verilog__main.i_rx_phy.RxEn_i_64_1 Verilog__main.txoe_64_1) (= Verilog__main.i_rx_phy.LineState_64_1 Verilog__main.LineState_o_64_1)) (and (= Verilog__main.reset_64_2 (and Verilog__main.rst_64_2 (not Verilog__main.usb_rst_64_2))) (and (= Verilog__main.i_tx_phy.hold_64_2 Verilog__main.i_tx_phy.stuff_64_2) (= Verilog__main.i_tx_phy.sft_done_e_64_2 (and Verilog__main.i_tx_phy.sft_done_64_2 (not Verilog__main.i_tx_phy.sft_done_r_64_2))) (= Verilog__main.i_tx_phy.stuff_64_2 (= Verilog__main.i_tx_phy.one_cnt_64_2 (_ bv6 3))) (= Verilog__main.i_tx_phy.eop_done_64_2 Verilog__main.i_tx_phy.append_eop_sync3_64_2)) (= Verilog__main.i_tx_phy.clk_64_2 Verilog__main.clk_64_2) (= Verilog__main.i_tx_phy.rst_64_2 Verilog__main.reset_64_2) (= Verilog__main.i_tx_phy.fs_ce_64_2 Verilog__main.fs_ce_64_2) (= Verilog__main.i_tx_phy.phy_mode_64_2 Verilog__main.phy_tx_mode_64_2) (= Verilog__main.i_tx_phy.txdp_64_2 Verilog__main.txdp_64_2) (= Verilog__main.i_tx_phy.txdn_64_2 Verilog__main.txdn_64_2) (= Verilog__main.i_tx_phy.txoe_64_2 Verilog__main.txoe_64_2) (= Verilog__main.i_tx_phy.DataOut_i_64_2 Verilog__main.DataOut_i_64_2) (= Verilog__main.i_tx_phy.TxValid_i_64_2 Verilog__main.TxValid_i_64_2) (= Verilog__main.i_tx_phy.TxReady_o_64_2 Verilog__main.TxReady_o_64_2) (and (= Verilog__main.i_rx_phy.RxActive_o_64_2 Verilog__main.i_rx_phy.rx_active_64_2) (= Verilog__main.i_rx_phy.RxValid_o_64_2 Verilog__main.i_rx_phy.rx_valid_64_2) (= Verilog__main.i_rx_phy.RxError_o_64_2 false) (= Verilog__main.i_rx_phy.DataIn_o_64_2 Verilog__main.i_rx_phy.hold_reg_64_2) (= Verilog__main.i_rx_phy.LineState_64_2 (concat (ite Verilog__main.i_rx_phy.rxdp_s1_64_2 (_ bv1 1) (_ bv0 1)) (ite Verilog__main.i_rx_phy.rxdn_s1_64_2 (_ bv1 1) (_ bv0 1)))) (= Verilog__main.i_rx_phy.k_64_2 (and (not Verilog__main.i_rx_phy.rxdp_s_64_2) Verilog__main.i_rx_phy.rxdn_s_64_2)) (= Verilog__main.i_rx_phy.j_64_2 (and Verilog__main.i_rx_phy.rxdp_s_64_2 (not Verilog__main.i_rx_phy.rxdn_s_64_2))) (= Verilog__main.i_rx_phy.se0_64_2 (and (not Verilog__main.i_rx_phy.rxdp_s_64_2) (not Verilog__main.i_rx_phy.rxdn_s_64_2))) (= Verilog__main.i_rx_phy.lock_en_64_2 Verilog__main.i_rx_phy.rx_en_64_2) (= Verilog__main.i_rx_phy.change_64_2 (or (xor Verilog__main.i_rx_phy.rxdp_s1r_64_2 Verilog__main.i_rx_phy.rxdp_s1_64_2) (xor Verilog__main.i_rx_phy.rxdn_s1r_64_2 Verilog__main.i_rx_phy.rxdn_s1_64_2))) (= Verilog__main.i_rx_phy.drop_bit_64_2 (= Verilog__main.i_rx_phy.one_cnt_64_2 (_ bv6 3)))) (= Verilog__main.i_rx_phy.clk_64_2 Verilog__main.clk_64_2) (= Verilog__main.i_rx_phy.rst_64_2 Verilog__main.reset_64_2) (= Verilog__main.i_rx_phy.fs_ce_64_2 Verilog__main.fs_ce_64_2) (= Verilog__main.i_rx_phy.rxd_64_2 Verilog__main.rxd_64_2) (= Verilog__main.i_rx_phy.rxdp_64_2 Verilog__main.rxdp_64_2) (= Verilog__main.i_rx_phy.rxdn_64_2 Verilog__main.rxdn_64_2) (= Verilog__main.i_rx_phy.DataIn_o_64_2 Verilog__main.DataIn_o_64_2) (= Verilog__main.i_rx_phy.RxValid_o_64_2 Verilog__main.RxValid_o_64_2) (= Verilog__main.i_rx_phy.RxActive_o_64_2 Verilog__main.RxActive_o_64_2) (= Verilog__main.i_rx_phy.RxError_o_64_2 Verilog__main.RxError_o_64_2) (= Verilog__main.i_rx_phy.RxEn_i_64_2 Verilog__main.txoe_64_2) (= Verilog__main.i_rx_phy.LineState_64_2 Verilog__main.LineState_o_64_2)) (and (and (= Verilog__main.i_tx_phy.sd_bs_o_64_0 false) (= Verilog__main.i_tx_phy.sd_nrzi_o_64_0 true) (= Verilog__main.i_tx_phy.append_eop_64_0 false) (= Verilog__main.i_tx_phy.append_eop_sync1_64_0 false) (= Verilog__main.i_tx_phy.append_eop_sync2_64_0 false) (= Verilog__main.i_tx_phy.append_eop_sync3_64_0 false) (= Verilog__main.i_tx_phy.txoe_r1_64_0 false) (= Verilog__main.i_tx_phy.txoe_r2_64_0 false) (= Verilog__main.i_tx_phy.txdp_64_0 true) (= Verilog__main.i_tx_phy.txdn_64_0 false) (= Verilog__main.i_tx_phy.txoe_64_0 true) (= Verilog__main.i_tx_phy.TxReady_o_64_0 false) (= Verilog__main.i_tx_phy.state_64_0 (_ bv0 3)) (= Verilog__main.i_tx_phy.tx_ready_64_0 false) (= Verilog__main.i_tx_phy.tx_ready_d_64_0 false) (= Verilog__main.i_tx_phy.ld_sop_d_64_0 false) (= Verilog__main.i_tx_phy.ld_data_d_64_0 false) (= Verilog__main.i_tx_phy.ld_eop_d_64_0 false) (= Verilog__main.i_tx_phy.tx_ip_64_0 false) (= Verilog__main.i_tx_phy.tx_ip_sync_64_0 false) (= Verilog__main.i_tx_phy.bit_cnt_64_0 (_ bv0 3)) (= Verilog__main.i_tx_phy.hold_reg_64_0 (_ bv0 8)) (= Verilog__main.i_tx_phy.sd_raw_o_64_0 false) (= Verilog__main.i_tx_phy.data_done_64_0 false) (= Verilog__main.i_tx_phy.sft_done_64_0 false) (= Verilog__main.i_tx_phy.sft_done_r_64_0 false) (= Verilog__main.i_tx_phy.ld_data_64_0 false) (= Verilog__main.i_tx_phy.one_cnt_64_0 (_ bv0 3))) (and (= Verilog__main.i_rx_phy.fs_ce_64_0 false) (= Verilog__main.i_rx_phy.rxd_t1_64_0 false) (= Verilog__main.i_rx_phy.rxd_s1_64_0 false) (= Verilog__main.i_rx_phy.rxd_s_64_0 false) (= Verilog__main.i_rx_phy.rxdp_t1_64_0 false) (= Verilog__main.i_rx_phy.rxdp_s1_64_0 false) (= Verilog__main.i_rx_phy.rxdp_s_64_0 false) (= Verilog__main.i_rx_phy.rxdn_t1_64_0 false) (= Verilog__main.i_rx_phy.rxdn_s1_64_0 false) (= Verilog__main.i_rx_phy.rxdn_s_64_0 false) (= Verilog__main.i_rx_phy.synced_d_64_0 false) (= Verilog__main.i_rx_phy.rx_en_64_0 false) (= Verilog__main.i_rx_phy.rx_active_64_0 false) (= Verilog__main.i_rx_phy.bit_cnt_64_0 (_ bv0 3)) (= Verilog__main.i_rx_phy.rx_valid1_64_0 false) (= Verilog__main.i_rx_phy.rx_valid_64_0 false) (= Verilog__main.i_rx_phy.shift_en_64_0 false) (= Verilog__main.i_rx_phy.sd_r_64_0 false) (= Verilog__main.i_rx_phy.sd_nrzi_64_0 false) (= Verilog__main.i_rx_phy.hold_reg_64_0 (_ bv0 8)) (= Verilog__main.i_rx_phy.one_cnt_64_0 (_ bv0 3)) (= Verilog__main.i_rx_phy.dpll_state_64_0 (_ bv1 2)) (= Verilog__main.i_rx_phy.fs_ce_d_64_0 false) (= Verilog__main.i_rx_phy.rxdp_s1r_64_0 false) (= Verilog__main.i_rx_phy.rxdn_s1r_64_0 false) (= Verilog__main.i_rx_phy.fs_ce_r1_64_0 false) (= Verilog__main.i_rx_phy.fs_ce_r2_64_0 false) (= Verilog__main.i_rx_phy.fs_ce_r3_64_0 false) (= Verilog__main.i_rx_phy.fs_state_64_0 (_ bv0 3)) (= Verilog__main.i_rx_phy.rx_valid_r_64_0 false)) (= Verilog__main.usb_rst_64_0 false) (= Verilog__main.rst_cnt_64_0 (_ bv0 5))) (and (and (= Verilog__main.i_tx_phy.sd_bs_o_64_1 (ite (not Verilog__main.i_tx_phy.rst_64_0) false (ite Verilog__main.i_tx_phy.fs_ce_64_0 (ite (not Verilog__main.i_tx_phy.tx_ip_sync_64_0) false (ite Verilog__main.i_tx_phy.stuff_64_0 false (= ((_ extract 0 0) (ite Verilog__main.i_tx_phy.sd_raw_o_64_0 (_ bv1 1) (_ bv0 1))) (_ bv1 1)))) Verilog__main.i_tx_phy.sd_bs_o_64_0))) (= Verilog__main.i_tx_phy.sd_nrzi_o_64_1 (ite (not Verilog__main.i_tx_phy.rst_64_0) true (ite (or (not Verilog__main.i_tx_phy.tx_ip_sync_64_0) (not Verilog__main.i_tx_phy.txoe_r1_64_0)) true (ite Verilog__main.i_tx_phy.fs_ce_64_0 (ite Verilog__main.i_tx_phy.sd_bs_o_64_0 Verilog__main.i_tx_phy.sd_nrzi_o_64_0 (not Verilog__main.i_tx_phy.sd_nrzi_o_64_0)) Verilog__main.i_tx_phy.sd_nrzi_o_64_0)))) (= Verilog__main.i_tx_phy.append_eop_64_1 (ite (not Verilog__main.i_tx_phy.rst_64_0) false (ite Verilog__main.i_tx_phy.ld_eop_d_64_0 true (ite Verilog__main.i_tx_phy.append_eop_sync2_64_0 false Verilog__main.i_tx_phy.append_eop_64_0)))) (= Verilog__main.i_tx_phy.append_eop_sync1_64_1 (ite (not Verilog__main.i_tx_phy.rst_64_0) false (ite Verilog__main.i_tx_phy.fs_ce_64_0 Verilog__main.i_tx_phy.append_eop_64_0 Verilog__main.i_tx_phy.append_eop_sync1_64_0))) (= Verilog__main.i_tx_phy.append_eop_sync2_64_1 (ite (not Verilog__main.i_tx_phy.rst_64_0) false (ite Verilog__main.i_tx_phy.fs_ce_64_0 Verilog__main.i_tx_phy.append_eop_sync1_64_0 Verilog__main.i_tx_phy.append_eop_sync2_64_0))) (= Verilog__main.i_tx_phy.append_eop_sync3_64_1 (ite (not Verilog__main.i_tx_phy.rst_64_0) false (ite Verilog__main.i_tx_phy.fs_ce_64_0 Verilog__main.i_tx_phy.append_eop_sync2_64_0 Verilog__main.i_tx_phy.append_eop_sync3_64_0))) (= Verilog__main.i_tx_phy.txoe_r1_64_1 (ite (not Verilog__main.i_tx_phy.rst_64_0) false (ite Verilog__main.i_tx_phy.fs_ce_64_0 Verilog__main.i_tx_phy.tx_ip_sync_64_0 Verilog__main.i_tx_phy.txoe_r1_64_0))) (= Verilog__main.i_tx_phy.txoe_r2_64_1 (ite (not Verilog__main.i_tx_phy.rst_64_0) false (ite Verilog__main.i_tx_phy.fs_ce_64_0 Verilog__main.i_tx_phy.txoe_r1_64_0 Verilog__main.i_tx_phy.txoe_r2_64_0))) (= Verilog__main.i_tx_phy.txdp_64_1 (ite (not Verilog__main.i_tx_phy.rst_64_0) true (ite Verilog__main.i_tx_phy.fs_ce_64_0 (ite Verilog__main.i_tx_phy.phy_mode_64_0 (and (not Verilog__main.i_tx_phy.append_eop_sync3_64_0) Verilog__main.i_tx_phy.sd_nrzi_o_64_0) Verilog__main.i_tx_phy.sd_nrzi_o_64_0) Verilog__main.i_tx_phy.txdp_64_0))) (= Verilog__main.i_tx_phy.txdn_64_1 (ite (not Verilog__main.i_tx_phy.rst_64_0) false (ite Verilog__main.i_tx_phy.fs_ce_64_0 (ite Verilog__main.i_tx_phy.phy_mode_64_0 (and (not Verilog__main.i_tx_phy.append_eop_sync3_64_0) (not Verilog__main.i_tx_phy.sd_nrzi_o_64_0)) Verilog__main.i_tx_phy.append_eop_sync3_64_0) Verilog__main.i_tx_phy.txdn_64_0))) (= Verilog__main.i_tx_phy.txoe_64_1 (ite (not Verilog__main.i_tx_phy.rst_64_0) true (ite Verilog__main.i_tx_phy.fs_ce_64_0 (not (or Verilog__main.i_tx_phy.txoe_r1_64_0 Verilog__main.i_tx_phy.txoe_r2_64_0)) Verilog__main.i_tx_phy.txoe_64_0))) (= Verilog__main.i_tx_phy.TxReady_o_64_1 (ite (not Verilog__main.i_tx_phy.rst_64_0) false (and Verilog__main.i_tx_phy.tx_ready_d_64_0 Verilog__main.i_tx_phy.TxValid_i_64_0))) (= Verilog__main.i_tx_phy.state_64_1 (ite (not Verilog__main.i_tx_phy.rst_64_0) (_ bv0 3) (ite (= Verilog__main.i_tx_phy.state_64_0 (_ bv0 3)) (ite Verilog__main.i_tx_phy.TxValid_i_64_0 (_ bv1 3) Verilog__main.i_tx_phy.state_64_0) (ite (= Verilog__main.i_tx_phy.state_64_0 (_ bv1 3)) (ite Verilog__main.i_tx_phy.sft_done_e_64_0 (_ bv3 3) Verilog__main.i_tx_phy.state_64_0) (ite (= Verilog__main.i_tx_phy.state_64_0 (_ bv3 3)) (ite (and (not Verilog__main.i_tx_phy.data_done_64_0) Verilog__main.i_tx_phy.sft_done_e_64_0) (_ bv4 3) Verilog__main.i_tx_phy.state_64_0) (ite (= Verilog__main.i_tx_phy.state_64_0 (_ bv4 3)) (ite Verilog__main.i_tx_phy.eop_done_64_0 (_ bv5 3) Verilog__main.i_tx_phy.state_64_0) (ite (= Verilog__main.i_tx_phy.state_64_0 (_ bv5 3)) (ite (and (not Verilog__main.i_tx_phy.eop_done_64_0) Verilog__main.i_tx_phy.fs_ce_64_0) (_ bv6 3) Verilog__main.i_tx_phy.state_64_0) (ite (= Verilog__main.i_tx_phy.state_64_0 (_ bv6 3)) (ite Verilog__main.i_tx_phy.fs_ce_64_0 (_ bv0 3) Verilog__main.i_tx_phy.state_64_0) Verilog__main.i_tx_phy.state_64_0)))))))) (= Verilog__main.i_tx_phy.tx_ready_64_1 Verilog__main.i_tx_phy.tx_ready_d_64_0) (= Verilog__main.i_tx_phy.tx_ready_d_64_1 (ite (not Verilog__main.i_tx_phy.rst_64_0) Verilog__main.i_tx_phy.tx_ready_d_64_0 (ite (= Verilog__main.i_tx_phy.state_64_0 (_ bv0 3)) false (ite (= Verilog__main.i_tx_phy.state_64_0 (_ bv1 3)) (ite Verilog__main.i_tx_phy.sft_done_e_64_0 true false) (ite (= Verilog__main.i_tx_phy.state_64_0 (_ bv3 3)) (ite (and Verilog__main.i_tx_phy.data_done_64_0 Verilog__main.i_tx_phy.sft_done_e_64_0) true false) false))))) (= Verilog__main.i_tx_phy.ld_sop_d_64_1 (ite (not Verilog__main.i_tx_phy.rst_64_0) Verilog__main.i_tx_phy.ld_sop_d_64_0 (ite (= Verilog__main.i_tx_phy.state_64_0 (_ bv0 3)) (ite Verilog__main.i_tx_phy.TxValid_i_64_0 true false) false))) (= Verilog__main.i_tx_phy.ld_data_d_64_1 (ite (not Verilog__main.i_tx_phy.rst_64_0) Verilog__main.i_tx_phy.ld_data_d_64_0 (ite (= Verilog__main.i_tx_phy.state_64_0 (_ bv0 3)) false (ite (= Verilog__main.i_tx_phy.state_64_0 (_ bv1 3)) (ite Verilog__main.i_tx_phy.sft_done_e_64_0 true false) (ite (= Verilog__main.i_tx_phy.state_64_0 (_ bv3 3)) (ite (and Verilog__main.i_tx_phy.data_done_64_0 Verilog__main.i_tx_phy.sft_done_e_64_0) true false) false))))) (= Verilog__main.i_tx_phy.ld_eop_d_64_1 (ite (not Verilog__main.i_tx_phy.rst_64_0) Verilog__main.i_tx_phy.ld_eop_d_64_0 (ite (= Verilog__main.i_tx_phy.state_64_0 (_ bv0 3)) false (ite (= Verilog__main.i_tx_phy.state_64_0 (_ bv1 3)) false (ite (= Verilog__main.i_tx_phy.state_64_0 (_ bv3 3)) (ite (and (not Verilog__main.i_tx_phy.data_done_64_0) Verilog__main.i_tx_phy.sft_done_e_64_0) true false) false))))) (= Verilog__main.i_tx_phy.tx_ip_64_1 (ite (not Verilog__main.i_tx_phy.rst_64_0) false (ite Verilog__main.i_tx_phy.ld_sop_d_64_0 true (ite Verilog__main.i_tx_phy.eop_done_64_0 false Verilog__main.i_tx_phy.tx_ip_64_0)))) (= Verilog__main.i_tx_phy.tx_ip_sync_64_1 (ite (not Verilog__main.i_tx_phy.rst_64_0) false (ite Verilog__main.i_tx_phy.fs_ce_64_0 Verilog__main.i_tx_phy.tx_ip_64_0 Verilog__main.i_tx_phy.tx_ip_sync_64_0))) (= Verilog__main.i_tx_phy.bit_cnt_64_1 (ite (not Verilog__main.i_tx_phy.rst_64_0) (_ bv0 3) (ite (not Verilog__main.i_tx_phy.tx_ip_sync_64_0) (_ bv0 3) (ite (and Verilog__main.i_tx_phy.fs_ce_64_0 (not Verilog__main.i_tx_phy.hold_64_0)) (bvadd Verilog__main.i_tx_phy.bit_cnt_64_0 (_ bv1 3)) Verilog__main.i_tx_phy.bit_cnt_64_0)))) (= Verilog__main.i_tx_phy.hold_reg_64_1 (ite Verilog__main.i_tx_phy.ld_sop_d_64_0 (_ bv128 8) (ite Verilog__main.i_tx_phy.ld_data_64_0 Verilog__main.i_tx_phy.DataOut_i_64_0 Verilog__main.i_tx_phy.hold_reg_64_0))) (= Verilog__main.i_tx_phy.sd_raw_o_64_1 (ite (not Verilog__main.i_tx_phy.tx_ip_sync_64_0) false (ite (= Verilog__main.i_tx_phy.bit_cnt_64_0 (_ bv0 3)) (= ((_ extract 0 0) Verilog__main.i_tx_phy.hold_reg_64_0) (_ bv1 1)) (ite (= Verilog__main.i_tx_phy.bit_cnt_64_0 (_ bv1 3)) (= ((_ extract 1 1) Verilog__main.i_tx_phy.hold_reg_64_0) (_ bv1 1)) (ite (= Verilog__main.i_tx_phy.bit_cnt_64_0 (_ bv2 3)) (= ((_ extract 2 2) Verilog__main.i_tx_phy.hold_reg_64_0) (_ bv1 1)) (ite (= Verilog__main.i_tx_phy.bit_cnt_64_0 (_ bv3 3)) (= ((_ extract 3 3) Verilog__main.i_tx_phy.hold_reg_64_0) (_ bv1 1)) (ite (= Verilog__main.i_tx_phy.bit_cnt_64_0 (_ bv4 3)) (= ((_ extract 4 4) Verilog__main.i_tx_phy.hold_reg_64_0) (_ bv1 1)) (ite (= Verilog__main.i_tx_phy.bit_cnt_64_0 (_ bv5 3)) (= ((_ extract 5 5) Verilog__main.i_tx_phy.hold_reg_64_0) (_ bv1 1)) (ite (= Verilog__main.i_tx_phy.bit_cnt_64_0 (_ bv6 3)) (= ((_ extract 6 6) Verilog__main.i_tx_phy.hold_reg_64_0) (_ bv1 1)) (ite (= Verilog__main.i_tx_phy.bit_cnt_64_0 (_ bv7 3)) (= ((_ extract 7 7) Verilog__main.i_tx_phy.hold_reg_64_0) (_ bv1 1)) Verilog__main.i_tx_phy.sd_raw_o_64_0)))))))))) (= Verilog__main.i_tx_phy.data_done_64_1 (ite (not Verilog__main.i_tx_phy.rst_64_0) false (ite (and Verilog__main.i_tx_phy.TxValid_i_64_0 (not Verilog__main.i_tx_phy.tx_ip_64_0)) true (ite (not Verilog__main.i_tx_phy.TxValid_i_64_0) false Verilog__main.i_tx_phy.data_done_64_0)))) (= Verilog__main.i_tx_phy.sft_done_64_1 (and (not Verilog__main.i_tx_phy.hold_64_0) (= Verilog__main.i_tx_phy.bit_cnt_64_0 (_ bv7 3)))) (= Verilog__main.i_tx_phy.sft_done_r_64_1 Verilog__main.i_tx_phy.sft_done_64_0) (= Verilog__main.i_tx_phy.ld_data_64_1 Verilog__main.i_tx_phy.ld_data_d_64_0) (= Verilog__main.i_tx_phy.one_cnt_64_1 (ite (not Verilog__main.i_tx_phy.rst_64_0) (_ bv0 3) (ite (not Verilog__main.i_tx_phy.tx_ip_sync_64_0) (_ bv0 3) (ite Verilog__main.i_tx_phy.fs_ce_64_0 (ite (or (not Verilog__main.i_tx_phy.sd_raw_o_64_0) Verilog__main.i_tx_phy.stuff_64_0) (_ bv0 3) (bvadd Verilog__main.i_tx_phy.one_cnt_64_0 (_ bv1 3))) Verilog__main.i_tx_phy.one_cnt_64_0))))) (and (= Verilog__main.i_rx_phy.fs_ce_64_1 Verilog__main.i_rx_phy.fs_ce_r3_64_0) (= Verilog__main.i_rx_phy.rxd_t1_64_1 Verilog__main.i_rx_phy.rxd_64_0) (= Verilog__main.i_rx_phy.rxd_s1_64_1 Verilog__main.i_rx_phy.rxd_t1_64_0) (= Verilog__main.i_rx_phy.rxd_s_64_1 Verilog__main.i_rx_phy.rxd_s1_64_0) (= Verilog__main.i_rx_phy.rxdp_t1_64_1 Verilog__main.i_rx_phy.rxdp_64_0) (= Verilog__main.i_rx_phy.rxdp_s1_64_1 Verilog__main.i_rx_phy.rxdp_t1_64_0) (= Verilog__main.i_rx_phy.rxdp_s_64_1 Verilog__main.i_rx_phy.rxdp_s1_64_0) (= Verilog__main.i_rx_phy.rxdn_t1_64_1 Verilog__main.i_rx_phy.rxdn_64_0) (= Verilog__main.i_rx_phy.rxdn_s1_64_1 Verilog__main.i_rx_phy.rxdn_t1_64_0) (= Verilog__main.i_rx_phy.rxdn_s_64_1 Verilog__main.i_rx_phy.rxdn_s1_64_0) (= Verilog__main.i_rx_phy.synced_d_64_1 (ite (not Verilog__main.i_rx_phy.rst_64_0) Verilog__main.i_rx_phy.synced_d_64_0 (ite Verilog__main.i_rx_phy.fs_ce_64_0 (ite (= Verilog__main.i_rx_phy.fs_state_64_0 (_ bv0 3)) false (ite (= Verilog__main.i_rx_phy.fs_state_64_0 (_ bv1 3)) false (ite (= Verilog__main.i_rx_phy.fs_state_64_0 (_ bv2 3)) false (ite (= Verilog__main.i_rx_phy.fs_state_64_0 (_ bv3 3)) false (ite (= Verilog__main.i_rx_phy.fs_state_64_0 (_ bv4 3)) false (ite (= Verilog__main.i_rx_phy.fs_state_64_0 (_ bv5 3)) false (ite (= Verilog__main.i_rx_phy.fs_state_64_0 (_ bv6 3)) false (ite (= Verilog__main.i_rx_phy.fs_state_64_0 (_ bv7 3)) (ite Verilog__main.i_rx_phy.k_64_0 true false) false)))))))) false))) (= Verilog__main.i_rx_phy.rx_en_64_1 Verilog__main.i_rx_phy.RxEn_i_64_0) (= Verilog__main.i_rx_phy.rx_active_64_1 (ite (not Verilog__main.i_rx_phy.rst_64_0) false (ite (and Verilog__main.i_rx_phy.synced_d_64_0 Verilog__main.i_rx_phy.rx_en_64_0) true (ite (and Verilog__main.i_rx_phy.se0_64_0 Verilog__main.i_rx_phy.rx_valid_r_64_0) false Verilog__main.i_rx_phy.rx_active_64_0)))) (= Verilog__main.i_rx_phy.bit_cnt_64_1 (ite (not Verilog__main.i_rx_phy.rst_64_0) (_ bv0 3) (ite (not Verilog__main.i_rx_phy.shift_en_64_0) (_ bv0 3) (ite (and Verilog__main.i_rx_phy.fs_ce_64_0 (not Verilog__main.i_rx_phy.drop_bit_64_0)) (bvadd Verilog__main.i_rx_phy.bit_cnt_64_0 (_ bv1 3)) Verilog__main.i_rx_phy.bit_cnt_64_0)))) (= Verilog__main.i_rx_phy.rx_valid1_64_1 (ite (not Verilog__main.i_rx_phy.rst_64_0) false (ite (and (and Verilog__main.i_rx_phy.fs_ce_64_0 (not Verilog__main.i_rx_phy.drop_bit_64_0)) (= Verilog__main.i_rx_phy.bit_cnt_64_0 (_ bv7 3))) true (ite (and (and Verilog__main.i_rx_phy.rx_valid1_64_0 Verilog__main.i_rx_phy.fs_ce_64_0) (not Verilog__main.i_rx_phy.drop_bit_64_0)) false Verilog__main.i_rx_phy.rx_valid1_64_0)))) (= Verilog__main.i_rx_phy.rx_valid_64_1 (and (and (not Verilog__main.i_rx_phy.drop_bit_64_0) Verilog__main.i_rx_phy.rx_valid1_64_0) Verilog__main.i_rx_phy.fs_ce_64_0)) (= Verilog__main.i_rx_phy.shift_en_64_1 (ite Verilog__main.i_rx_phy.fs_ce_64_0 (or Verilog__main.i_rx_phy.synced_d_64_0 Verilog__main.i_rx_phy.rx_active_64_0) Verilog__main.i_rx_phy.shift_en_64_0)) (= Verilog__main.i_rx_phy.sd_r_64_1 (ite Verilog__main.i_rx_phy.fs_ce_64_0 Verilog__main.i_rx_phy.rxd_s_64_0 Verilog__main.i_rx_phy.sd_r_64_0)) (= Verilog__main.i_rx_phy.sd_nrzi_64_1 (ite (not Verilog__main.i_rx_phy.rst_64_0) false (ite (and Verilog__main.i_rx_phy.rx_active_64_0 Verilog__main.i_rx_phy.fs_ce_64_0) (not (xor Verilog__main.i_rx_phy.rxd_s_64_0 Verilog__main.i_rx_phy.sd_r_64_0)) Verilog__main.i_rx_phy.sd_nrzi_64_0))) (= Verilog__main.i_rx_phy.hold_reg_64_1 (ite (and (and Verilog__main.i_rx_phy.fs_ce_64_0 Verilog__main.i_rx_phy.shift_en_64_0) (not Verilog__main.i_rx_phy.drop_bit_64_0)) (concat (ite Verilog__main.i_rx_phy.sd_nrzi_64_0 (_ bv1 1) (_ bv0 1)) ((_ extract 7 1) Verilog__main.i_rx_phy.hold_reg_64_0)) Verilog__main.i_rx_phy.hold_reg_64_0)) (= Verilog__main.i_rx_phy.one_cnt_64_1 (ite (not Verilog__main.i_rx_phy.rst_64_0) (_ bv0 3) (ite (not Verilog__main.i_rx_phy.shift_en_64_0) (_ bv0 3) (ite Verilog__main.i_rx_phy.fs_ce_64_0 (ite (or (not Verilog__main.i_rx_phy.sd_nrzi_64_0) Verilog__main.i_rx_phy.drop_bit_64_0) (_ bv0 3) (bvadd Verilog__main.i_rx_phy.one_cnt_64_0 (_ bv1 3))) Verilog__main.i_rx_phy.one_cnt_64_0)))) (= Verilog__main.i_rx_phy.dpll_state_64_1 (ite (not Verilog__main.i_rx_phy.rst_64_0) (_ bv1 2) (ite (= Verilog__main.i_rx_phy.dpll_state_64_0 (_ bv0 2)) (ite (and Verilog__main.i_rx_phy.lock_en_64_0 Verilog__main.i_rx_phy.change_64_0) (_ bv0 2) (_ bv1 2)) (ite (= Verilog__main.i_rx_phy.dpll_state_64_0 (_ bv1 2)) (ite (and Verilog__main.i_rx_phy.lock_en_64_0 Verilog__main.i_rx_phy.change_64_0) (_ bv3 2) (_ bv2 2)) (ite (= Verilog__main.i_rx_phy.dpll_state_64_0 (_ bv2 2)) (ite (and Verilog__main.i_rx_phy.lock_en_64_0 Verilog__main.i_rx_phy.change_64_0) (_ bv0 2) (_ bv3 2)) (ite (= Verilog__main.i_rx_phy.dpll_state_64_0 (_ bv3 2)) (ite (and Verilog__main.i_rx_phy.lock_en_64_0 Verilog__main.i_rx_phy.change_64_0) (_ bv0 2) (_ bv0 2)) Verilog__main.i_rx_phy.dpll_state_64_0)))))) (= Verilog__main.i_rx_phy.fs_ce_d_64_1 (ite (not Verilog__main.i_rx_phy.rst_64_0) Verilog__main.i_rx_phy.fs_ce_d_64_0 (ite (= Verilog__main.i_rx_phy.dpll_state_64_0 (_ bv0 2)) false (ite (= Verilog__main.i_rx_phy.dpll_state_64_0 (_ bv1 2)) true false)))) (= Verilog__main.i_rx_phy.rxdp_s1r_64_1 Verilog__main.i_rx_phy.rxdp_s1_64_0) (= Verilog__main.i_rx_phy.rxdn_s1r_64_1 Verilog__main.i_rx_phy.rxdn_s1_64_0) (= Verilog__main.i_rx_phy.fs_ce_r1_64_1 Verilog__main.i_rx_phy.fs_ce_d_64_0) (= Verilog__main.i_rx_phy.fs_ce_r2_64_1 Verilog__main.i_rx_phy.fs_ce_r1_64_0) (= Verilog__main.i_rx_phy.fs_ce_r3_64_1 Verilog__main.i_rx_phy.fs_ce_r2_64_0) (= Verilog__main.i_rx_phy.fs_state_64_1 (ite (not Verilog__main.i_rx_phy.rst_64_0) (_ bv0 3) (ite Verilog__main.i_rx_phy.fs_ce_64_0 (ite (= Verilog__main.i_rx_phy.fs_state_64_0 (_ bv0 3)) (ite (and Verilog__main.i_rx_phy.k_64_0 Verilog__main.i_rx_phy.rx_en_64_0) (_ bv1 3) Verilog__main.i_rx_phy.fs_state_64_0) (ite (= Verilog__main.i_rx_phy.fs_state_64_0 (_ bv1 3)) (ite (and Verilog__main.i_rx_phy.j_64_0 Verilog__main.i_rx_phy.rx_en_64_0) (_ bv2 3) (_ bv0 3)) (ite (= Verilog__main.i_rx_phy.fs_state_64_0 (_ bv2 3)) (ite (and Verilog__main.i_rx_phy.k_64_0 Verilog__main.i_rx_phy.rx_en_64_0) (_ bv3 3) (_ bv0 3)) (ite (= Verilog__main.i_rx_phy.fs_state_64_0 (_ bv3 3)) (ite (and Verilog__main.i_rx_phy.j_64_0 Verilog__main.i_rx_phy.rx_en_64_0) (_ bv4 3) (_ bv0 3)) (ite (= Verilog__main.i_rx_phy.fs_state_64_0 (_ bv4 3)) (ite (and Verilog__main.i_rx_phy.k_64_0 Verilog__main.i_rx_phy.rx_en_64_0) (_ bv5 3) (_ bv0 3)) (ite (= Verilog__main.i_rx_phy.fs_state_64_0 (_ bv5 3)) (ite (and Verilog__main.i_rx_phy.j_64_0 Verilog__main.i_rx_phy.rx_en_64_0) (_ bv6 3) (ite (and Verilog__main.i_rx_phy.k_64_0 Verilog__main.i_rx_phy.rx_en_64_0) (_ bv7 3) (_ bv0 3))) (ite (= Verilog__main.i_rx_phy.fs_state_64_0 (_ bv6 3)) (ite (and Verilog__main.i_rx_phy.k_64_0 Verilog__main.i_rx_phy.rx_en_64_0) (_ bv7 3) (_ bv0 3)) (ite (= Verilog__main.i_rx_phy.fs_state_64_0 (_ bv7 3)) (_ bv0 3) Verilog__main.i_rx_phy.fs_state_64_0)))))))) Verilog__main.i_rx_phy.fs_state_64_0))) (= Verilog__main.i_rx_phy.rx_valid_r_64_1 (ite Verilog__main.i_rx_phy.rx_valid_64_0 true (ite Verilog__main.i_rx_phy.fs_ce_64_0 false Verilog__main.i_rx_phy.rx_valid_r_64_0)))) (= Verilog__main.usb_rst_64_1 (= Verilog__main.rst_cnt_64_0 (_ bv31 5))) (= Verilog__main.rst_cnt_64_1 (ite (not Verilog__main.rst_64_0) (_ bv0 5) (ite (not (= Verilog__main.LineState_o_64_0 (_ bv0 2))) (_ bv0 5) (ite (and (not Verilog__main.usb_rst_64_0) Verilog__main.fs_ce_64_0) (bvadd Verilog__main.rst_cnt_64_0 (_ bv1 5)) Verilog__main.rst_cnt_64_0))))) (and (and (= Verilog__main.i_tx_phy.sd_bs_o_64_2 (ite (not Verilog__main.i_tx_phy.rst_64_1) false (ite Verilog__main.i_tx_phy.fs_ce_64_1 (ite (not Verilog__main.i_tx_phy.tx_ip_sync_64_1) false (ite Verilog__main.i_tx_phy.stuff_64_1 false (= ((_ extract 0 0) (ite Verilog__main.i_tx_phy.sd_raw_o_64_1 (_ bv1 1) (_ bv0 1))) (_ bv1 1)))) Verilog__main.i_tx_phy.sd_bs_o_64_1))) (= Verilog__main.i_tx_phy.sd_nrzi_o_64_2 (ite (not Verilog__main.i_tx_phy.rst_64_1) true (ite (or (not Verilog__main.i_tx_phy.tx_ip_sync_64_1) (not Verilog__main.i_tx_phy.txoe_r1_64_1)) true (ite Verilog__main.i_tx_phy.fs_ce_64_1 (ite Verilog__main.i_tx_phy.sd_bs_o_64_1 Verilog__main.i_tx_phy.sd_nrzi_o_64_1 (not Verilog__main.i_tx_phy.sd_nrzi_o_64_1)) Verilog__main.i_tx_phy.sd_nrzi_o_64_1)))) (= Verilog__main.i_tx_phy.append_eop_64_2 (ite (not Verilog__main.i_tx_phy.rst_64_1) false (ite Verilog__main.i_tx_phy.ld_eop_d_64_1 true (ite Verilog__main.i_tx_phy.append_eop_sync2_64_1 false Verilog__main.i_tx_phy.append_eop_64_1)))) (= Verilog__main.i_tx_phy.append_eop_sync1_64_2 (ite (not Verilog__main.i_tx_phy.rst_64_1) false (ite Verilog__main.i_tx_phy.fs_ce_64_1 Verilog__main.i_tx_phy.append_eop_64_1 Verilog__main.i_tx_phy.append_eop_sync1_64_1))) (= Verilog__main.i_tx_phy.append_eop_sync2_64_2 (ite (not Verilog__main.i_tx_phy.rst_64_1) false (ite Verilog__main.i_tx_phy.fs_ce_64_1 Verilog__main.i_tx_phy.append_eop_sync1_64_1 Verilog__main.i_tx_phy.append_eop_sync2_64_1))) (= Verilog__main.i_tx_phy.append_eop_sync3_64_2 (ite (not Verilog__main.i_tx_phy.rst_64_1) false (ite Verilog__main.i_tx_phy.fs_ce_64_1 Verilog__main.i_tx_phy.append_eop_sync2_64_1 Verilog__main.i_tx_phy.append_eop_sync3_64_1))) (= Verilog__main.i_tx_phy.txoe_r1_64_2 (ite (not Verilog__main.i_tx_phy.rst_64_1) false (ite Verilog__main.i_tx_phy.fs_ce_64_1 Verilog__main.i_tx_phy.tx_ip_sync_64_1 Verilog__main.i_tx_phy.txoe_r1_64_1))) (= Verilog__main.i_tx_phy.txoe_r2_64_2 (ite (not Verilog__main.i_tx_phy.rst_64_1) false (ite Verilog__main.i_tx_phy.fs_ce_64_1 Verilog__main.i_tx_phy.txoe_r1_64_1 Verilog__main.i_tx_phy.txoe_r2_64_1))) (= Verilog__main.i_tx_phy.txdp_64_2 (ite (not Verilog__main.i_tx_phy.rst_64_1) true (ite Verilog__main.i_tx_phy.fs_ce_64_1 (ite Verilog__main.i_tx_phy.phy_mode_64_1 (and (not Verilog__main.i_tx_phy.append_eop_sync3_64_1) Verilog__main.i_tx_phy.sd_nrzi_o_64_1) Verilog__main.i_tx_phy.sd_nrzi_o_64_1) Verilog__main.i_tx_phy.txdp_64_1))) (= Verilog__main.i_tx_phy.txdn_64_2 (ite (not Verilog__main.i_tx_phy.rst_64_1) false (ite Verilog__main.i_tx_phy.fs_ce_64_1 (ite Verilog__main.i_tx_phy.phy_mode_64_1 (and (not Verilog__main.i_tx_phy.append_eop_sync3_64_1) (not Verilog__main.i_tx_phy.sd_nrzi_o_64_1)) Verilog__main.i_tx_phy.append_eop_sync3_64_1) Verilog__main.i_tx_phy.txdn_64_1))) (= Verilog__main.i_tx_phy.txoe_64_2 (ite (not Verilog__main.i_tx_phy.rst_64_1) true (ite Verilog__main.i_tx_phy.fs_ce_64_1 (not (or Verilog__main.i_tx_phy.txoe_r1_64_1 Verilog__main.i_tx_phy.txoe_r2_64_1)) Verilog__main.i_tx_phy.txoe_64_1))) (= Verilog__main.i_tx_phy.TxReady_o_64_2 (ite (not Verilog__main.i_tx_phy.rst_64_1) false (and Verilog__main.i_tx_phy.tx_ready_d_64_1 Verilog__main.i_tx_phy.TxValid_i_64_1))) (= Verilog__main.i_tx_phy.state_64_2 (ite (not Verilog__main.i_tx_phy.rst_64_1) (_ bv0 3) (ite (= Verilog__main.i_tx_phy.state_64_1 (_ bv0 3)) (ite Verilog__main.i_tx_phy.TxValid_i_64_1 (_ bv1 3) Verilog__main.i_tx_phy.state_64_1) (ite (= Verilog__main.i_tx_phy.state_64_1 (_ bv1 3)) (ite Verilog__main.i_tx_phy.sft_done_e_64_1 (_ bv3 3) Verilog__main.i_tx_phy.state_64_1) (ite (= Verilog__main.i_tx_phy.state_64_1 (_ bv3 3)) (ite (and (not Verilog__main.i_tx_phy.data_done_64_1) Verilog__main.i_tx_phy.sft_done_e_64_1) (_ bv4 3) Verilog__main.i_tx_phy.state_64_1) (ite (= Verilog__main.i_tx_phy.state_64_1 (_ bv4 3)) (ite Verilog__main.i_tx_phy.eop_done_64_1 (_ bv5 3) Verilog__main.i_tx_phy.state_64_1) (ite (= Verilog__main.i_tx_phy.state_64_1 (_ bv5 3)) (ite (and (not Verilog__main.i_tx_phy.eop_done_64_1) Verilog__main.i_tx_phy.fs_ce_64_1) (_ bv6 3) Verilog__main.i_tx_phy.state_64_1) (ite (= Verilog__main.i_tx_phy.state_64_1 (_ bv6 3)) (ite Verilog__main.i_tx_phy.fs_ce_64_1 (_ bv0 3) Verilog__main.i_tx_phy.state_64_1) Verilog__main.i_tx_phy.state_64_1)))))))) (= Verilog__main.i_tx_phy.tx_ready_64_2 Verilog__main.i_tx_phy.tx_ready_d_64_1) (= Verilog__main.i_tx_phy.tx_ready_d_64_2 (ite (not Verilog__main.i_tx_phy.rst_64_1) Verilog__main.i_tx_phy.tx_ready_d_64_1 (ite (= Verilog__main.i_tx_phy.state_64_1 (_ bv0 3)) false (ite (= Verilog__main.i_tx_phy.state_64_1 (_ bv1 3)) (ite Verilog__main.i_tx_phy.sft_done_e_64_1 true false) (ite (= Verilog__main.i_tx_phy.state_64_1 (_ bv3 3)) (ite (and Verilog__main.i_tx_phy.data_done_64_1 Verilog__main.i_tx_phy.sft_done_e_64_1) true false) false))))) (= Verilog__main.i_tx_phy.ld_sop_d_64_2 (ite (not Verilog__main.i_tx_phy.rst_64_1) Verilog__main.i_tx_phy.ld_sop_d_64_1 (ite (= Verilog__main.i_tx_phy.state_64_1 (_ bv0 3)) (ite Verilog__main.i_tx_phy.TxValid_i_64_1 true false) false))) (= Verilog__main.i_tx_phy.ld_data_d_64_2 (ite (not Verilog__main.i_tx_phy.rst_64_1) Verilog__main.i_tx_phy.ld_data_d_64_1 (ite (= Verilog__main.i_tx_phy.state_64_1 (_ bv0 3)) false (ite (= Verilog__main.i_tx_phy.state_64_1 (_ bv1 3)) (ite Verilog__main.i_tx_phy.sft_done_e_64_1 true false) (ite (= Verilog__main.i_tx_phy.state_64_1 (_ bv3 3)) (ite (and Verilog__main.i_tx_phy.data_done_64_1 Verilog__main.i_tx_phy.sft_done_e_64_1) true false) false))))) (= Verilog__main.i_tx_phy.ld_eop_d_64_2 (ite (not Verilog__main.i_tx_phy.rst_64_1) Verilog__main.i_tx_phy.ld_eop_d_64_1 (ite (= Verilog__main.i_tx_phy.state_64_1 (_ bv0 3)) false (ite (= Verilog__main.i_tx_phy.state_64_1 (_ bv1 3)) false (ite (= Verilog__main.i_tx_phy.state_64_1 (_ bv3 3)) (ite (and (not Verilog__main.i_tx_phy.data_done_64_1) Verilog__main.i_tx_phy.sft_done_e_64_1) true false) false))))) (= Verilog__main.i_tx_phy.tx_ip_64_2 (ite (not Verilog__main.i_tx_phy.rst_64_1) false (ite Verilog__main.i_tx_phy.ld_sop_d_64_1 true (ite Verilog__main.i_tx_phy.eop_done_64_1 false Verilog__main.i_tx_phy.tx_ip_64_1)))) (= Verilog__main.i_tx_phy.tx_ip_sync_64_2 (ite (not Verilog__main.i_tx_phy.rst_64_1) false (ite Verilog__main.i_tx_phy.fs_ce_64_1 Verilog__main.i_tx_phy.tx_ip_64_1 Verilog__main.i_tx_phy.tx_ip_sync_64_1))) (= Verilog__main.i_tx_phy.bit_cnt_64_2 (ite (not Verilog__main.i_tx_phy.rst_64_1) (_ bv0 3) (ite (not Verilog__main.i_tx_phy.tx_ip_sync_64_1) (_ bv0 3) (ite (and Verilog__main.i_tx_phy.fs_ce_64_1 (not Verilog__main.i_tx_phy.hold_64_1)) (bvadd Verilog__main.i_tx_phy.bit_cnt_64_1 (_ bv1 3)) Verilog__main.i_tx_phy.bit_cnt_64_1)))) (= Verilog__main.i_tx_phy.hold_reg_64_2 (ite Verilog__main.i_tx_phy.ld_sop_d_64_1 (_ bv128 8) (ite Verilog__main.i_tx_phy.ld_data_64_1 Verilog__main.i_tx_phy.DataOut_i_64_1 Verilog__main.i_tx_phy.hold_reg_64_1))) (= Verilog__main.i_tx_phy.sd_raw_o_64_2 (ite (not Verilog__main.i_tx_phy.tx_ip_sync_64_1) false (ite (= Verilog__main.i_tx_phy.bit_cnt_64_1 (_ bv0 3)) (= ((_ extract 0 0) Verilog__main.i_tx_phy.hold_reg_64_1) (_ bv1 1)) (ite (= Verilog__main.i_tx_phy.bit_cnt_64_1 (_ bv1 3)) (= ((_ extract 1 1) Verilog__main.i_tx_phy.hold_reg_64_1) (_ bv1 1)) (ite (= Verilog__main.i_tx_phy.bit_cnt_64_1 (_ bv2 3)) (= ((_ extract 2 2) Verilog__main.i_tx_phy.hold_reg_64_1) (_ bv1 1)) (ite (= Verilog__main.i_tx_phy.bit_cnt_64_1 (_ bv3 3)) (= ((_ extract 3 3) Verilog__main.i_tx_phy.hold_reg_64_1) (_ bv1 1)) (ite (= Verilog__main.i_tx_phy.bit_cnt_64_1 (_ bv4 3)) (= ((_ extract 4 4) Verilog__main.i_tx_phy.hold_reg_64_1) (_ bv1 1)) (ite (= Verilog__main.i_tx_phy.bit_cnt_64_1 (_ bv5 3)) (= ((_ extract 5 5) Verilog__main.i_tx_phy.hold_reg_64_1) (_ bv1 1)) (ite (= Verilog__main.i_tx_phy.bit_cnt_64_1 (_ bv6 3)) (= ((_ extract 6 6) Verilog__main.i_tx_phy.hold_reg_64_1) (_ bv1 1)) (ite (= Verilog__main.i_tx_phy.bit_cnt_64_1 (_ bv7 3)) (= ((_ extract 7 7) Verilog__main.i_tx_phy.hold_reg_64_1) (_ bv1 1)) Verilog__main.i_tx_phy.sd_raw_o_64_1)))))))))) (= Verilog__main.i_tx_phy.data_done_64_2 (ite (not Verilog__main.i_tx_phy.rst_64_1) false (ite (and Verilog__main.i_tx_phy.TxValid_i_64_1 (not Verilog__main.i_tx_phy.tx_ip_64_1)) true (ite (not Verilog__main.i_tx_phy.TxValid_i_64_1) false Verilog__main.i_tx_phy.data_done_64_1)))) (= Verilog__main.i_tx_phy.sft_done_64_2 (and (not Verilog__main.i_tx_phy.hold_64_1) (= Verilog__main.i_tx_phy.bit_cnt_64_1 (_ bv7 3)))) (= Verilog__main.i_tx_phy.sft_done_r_64_2 Verilog__main.i_tx_phy.sft_done_64_1) (= Verilog__main.i_tx_phy.ld_data_64_2 Verilog__main.i_tx_phy.ld_data_d_64_1) (= Verilog__main.i_tx_phy.one_cnt_64_2 (ite (not Verilog__main.i_tx_phy.rst_64_1) (_ bv0 3) (ite (not Verilog__main.i_tx_phy.tx_ip_sync_64_1) (_ bv0 3) (ite Verilog__main.i_tx_phy.fs_ce_64_1 (ite (or (not Verilog__main.i_tx_phy.sd_raw_o_64_1) Verilog__main.i_tx_phy.stuff_64_1) (_ bv0 3) (bvadd Verilog__main.i_tx_phy.one_cnt_64_1 (_ bv1 3))) Verilog__main.i_tx_phy.one_cnt_64_1))))) (and (= Verilog__main.i_rx_phy.fs_ce_64_2 Verilog__main.i_rx_phy.fs_ce_r3_64_1) (= Verilog__main.i_rx_phy.rxd_t1_64_2 Verilog__main.i_rx_phy.rxd_64_1) (= Verilog__main.i_rx_phy.rxd_s1_64_2 Verilog__main.i_rx_phy.rxd_t1_64_1) (= Verilog__main.i_rx_phy.rxd_s_64_2 Verilog__main.i_rx_phy.rxd_s1_64_1) (= Verilog__main.i_rx_phy.rxdp_t1_64_2 Verilog__main.i_rx_phy.rxdp_64_1) (= Verilog__main.i_rx_phy.rxdp_s1_64_2 Verilog__main.i_rx_phy.rxdp_t1_64_1) (= Verilog__main.i_rx_phy.rxdp_s_64_2 Verilog__main.i_rx_phy.rxdp_s1_64_1) (= Verilog__main.i_rx_phy.rxdn_t1_64_2 Verilog__main.i_rx_phy.rxdn_64_1) (= Verilog__main.i_rx_phy.rxdn_s1_64_2 Verilog__main.i_rx_phy.rxdn_t1_64_1) (= Verilog__main.i_rx_phy.rxdn_s_64_2 Verilog__main.i_rx_phy.rxdn_s1_64_1) (= Verilog__main.i_rx_phy.synced_d_64_2 (ite (not Verilog__main.i_rx_phy.rst_64_1) Verilog__main.i_rx_phy.synced_d_64_1 (ite Verilog__main.i_rx_phy.fs_ce_64_1 (ite (= Verilog__main.i_rx_phy.fs_state_64_1 (_ bv0 3)) false (ite (= Verilog__main.i_rx_phy.fs_state_64_1 (_ bv1 3)) false (ite (= Verilog__main.i_rx_phy.fs_state_64_1 (_ bv2 3)) false (ite (= Verilog__main.i_rx_phy.fs_state_64_1 (_ bv3 3)) false (ite (= Verilog__main.i_rx_phy.fs_state_64_1 (_ bv4 3)) false (ite (= Verilog__main.i_rx_phy.fs_state_64_1 (_ bv5 3)) false (ite (= Verilog__main.i_rx_phy.fs_state_64_1 (_ bv6 3)) false (ite (= Verilog__main.i_rx_phy.fs_state_64_1 (_ bv7 3)) (ite Verilog__main.i_rx_phy.k_64_1 true false) false)))))))) false))) (= Verilog__main.i_rx_phy.rx_en_64_2 Verilog__main.i_rx_phy.RxEn_i_64_1) (= Verilog__main.i_rx_phy.rx_active_64_2 (ite (not Verilog__main.i_rx_phy.rst_64_1) false (ite (and Verilog__main.i_rx_phy.synced_d_64_1 Verilog__main.i_rx_phy.rx_en_64_1) true (ite (and Verilog__main.i_rx_phy.se0_64_1 Verilog__main.i_rx_phy.rx_valid_r_64_1) false Verilog__main.i_rx_phy.rx_active_64_1)))) (= Verilog__main.i_rx_phy.bit_cnt_64_2 (ite (not Verilog__main.i_rx_phy.rst_64_1) (_ bv0 3) (ite (not Verilog__main.i_rx_phy.shift_en_64_1) (_ bv0 3) (ite (and Verilog__main.i_rx_phy.fs_ce_64_1 (not Verilog__main.i_rx_phy.drop_bit_64_1)) (bvadd Verilog__main.i_rx_phy.bit_cnt_64_1 (_ bv1 3)) Verilog__main.i_rx_phy.bit_cnt_64_1)))) (= Verilog__main.i_rx_phy.rx_valid1_64_2 (ite (not Verilog__main.i_rx_phy.rst_64_1) false (ite (and (and Verilog__main.i_rx_phy.fs_ce_64_1 (not Verilog__main.i_rx_phy.drop_bit_64_1)) (= Verilog__main.i_rx_phy.bit_cnt_64_1 (_ bv7 3))) true (ite (and (and Verilog__main.i_rx_phy.rx_valid1_64_1 Verilog__main.i_rx_phy.fs_ce_64_1) (not Verilog__main.i_rx_phy.drop_bit_64_1)) false Verilog__main.i_rx_phy.rx_valid1_64_1)))) (= Verilog__main.i_rx_phy.rx_valid_64_2 (and (and (not Verilog__main.i_rx_phy.drop_bit_64_1) Verilog__main.i_rx_phy.rx_valid1_64_1) Verilog__main.i_rx_phy.fs_ce_64_1)) (= Verilog__main.i_rx_phy.shift_en_64_2 (ite Verilog__main.i_rx_phy.fs_ce_64_1 (or Verilog__main.i_rx_phy.synced_d_64_1 Verilog__main.i_rx_phy.rx_active_64_1) Verilog__main.i_rx_phy.shift_en_64_1)) (= Verilog__main.i_rx_phy.sd_r_64_2 (ite Verilog__main.i_rx_phy.fs_ce_64_1 Verilog__main.i_rx_phy.rxd_s_64_1 Verilog__main.i_rx_phy.sd_r_64_1)) (= Verilog__main.i_rx_phy.sd_nrzi_64_2 (ite (not Verilog__main.i_rx_phy.rst_64_1) false (ite (and Verilog__main.i_rx_phy.rx_active_64_1 Verilog__main.i_rx_phy.fs_ce_64_1) (not (xor Verilog__main.i_rx_phy.rxd_s_64_1 Verilog__main.i_rx_phy.sd_r_64_1)) Verilog__main.i_rx_phy.sd_nrzi_64_1))) (= Verilog__main.i_rx_phy.hold_reg_64_2 (ite (and (and Verilog__main.i_rx_phy.fs_ce_64_1 Verilog__main.i_rx_phy.shift_en_64_1) (not Verilog__main.i_rx_phy.drop_bit_64_1)) (concat (ite Verilog__main.i_rx_phy.sd_nrzi_64_1 (_ bv1 1) (_ bv0 1)) ((_ extract 7 1) Verilog__main.i_rx_phy.hold_reg_64_1)) Verilog__main.i_rx_phy.hold_reg_64_1)) (= Verilog__main.i_rx_phy.one_cnt_64_2 (ite (not Verilog__main.i_rx_phy.rst_64_1) (_ bv0 3) (ite (not Verilog__main.i_rx_phy.shift_en_64_1) (_ bv0 3) (ite Verilog__main.i_rx_phy.fs_ce_64_1 (ite (or (not Verilog__main.i_rx_phy.sd_nrzi_64_1) Verilog__main.i_rx_phy.drop_bit_64_1) (_ bv0 3) (bvadd Verilog__main.i_rx_phy.one_cnt_64_1 (_ bv1 3))) Verilog__main.i_rx_phy.one_cnt_64_1)))) (= Verilog__main.i_rx_phy.dpll_state_64_2 (ite (not Verilog__main.i_rx_phy.rst_64_1) (_ bv1 2) (ite (= Verilog__main.i_rx_phy.dpll_state_64_1 (_ bv0 2)) (ite (and Verilog__main.i_rx_phy.lock_en_64_1 Verilog__main.i_rx_phy.change_64_1) (_ bv0 2) (_ bv1 2)) (ite (= Verilog__main.i_rx_phy.dpll_state_64_1 (_ bv1 2)) (ite (and Verilog__main.i_rx_phy.lock_en_64_1 Verilog__main.i_rx_phy.change_64_1) (_ bv3 2) (_ bv2 2)) (ite (= Verilog__main.i_rx_phy.dpll_state_64_1 (_ bv2 2)) (ite (and Verilog__main.i_rx_phy.lock_en_64_1 Verilog__main.i_rx_phy.change_64_1) (_ bv0 2) (_ bv3 2)) (ite (= Verilog__main.i_rx_phy.dpll_state_64_1 (_ bv3 2)) (ite (and Verilog__main.i_rx_phy.lock_en_64_1 Verilog__main.i_rx_phy.change_64_1) (_ bv0 2) (_ bv0 2)) Verilog__main.i_rx_phy.dpll_state_64_1)))))) (= Verilog__main.i_rx_phy.fs_ce_d_64_2 (ite (not Verilog__main.i_rx_phy.rst_64_1) Verilog__main.i_rx_phy.fs_ce_d_64_1 (ite (= Verilog__main.i_rx_phy.dpll_state_64_1 (_ bv0 2)) false (ite (= Verilog__main.i_rx_phy.dpll_state_64_1 (_ bv1 2)) true false)))) (= Verilog__main.i_rx_phy.rxdp_s1r_64_2 Verilog__main.i_rx_phy.rxdp_s1_64_1) (= Verilog__main.i_rx_phy.rxdn_s1r_64_2 Verilog__main.i_rx_phy.rxdn_s1_64_1) (= Verilog__main.i_rx_phy.fs_ce_r1_64_2 Verilog__main.i_rx_phy.fs_ce_d_64_1) (= Verilog__main.i_rx_phy.fs_ce_r2_64_2 Verilog__main.i_rx_phy.fs_ce_r1_64_1) (= Verilog__main.i_rx_phy.fs_ce_r3_64_2 Verilog__main.i_rx_phy.fs_ce_r2_64_1) (= Verilog__main.i_rx_phy.fs_state_64_2 (ite (not Verilog__main.i_rx_phy.rst_64_1) (_ bv0 3) (ite Verilog__main.i_rx_phy.fs_ce_64_1 (ite (= Verilog__main.i_rx_phy.fs_state_64_1 (_ bv0 3)) (ite (and Verilog__main.i_rx_phy.k_64_1 Verilog__main.i_rx_phy.rx_en_64_1) (_ bv1 3) Verilog__main.i_rx_phy.fs_state_64_1) (ite (= Verilog__main.i_rx_phy.fs_state_64_1 (_ bv1 3)) (ite (and Verilog__main.i_rx_phy.j_64_1 Verilog__main.i_rx_phy.rx_en_64_1) (_ bv2 3) (_ bv0 3)) (ite (= Verilog__main.i_rx_phy.fs_state_64_1 (_ bv2 3)) (ite (and Verilog__main.i_rx_phy.k_64_1 Verilog__main.i_rx_phy.rx_en_64_1) (_ bv3 3) (_ bv0 3)) (ite (= Verilog__main.i_rx_phy.fs_state_64_1 (_ bv3 3)) (ite (and Verilog__main.i_rx_phy.j_64_1 Verilog__main.i_rx_phy.rx_en_64_1) (_ bv4 3) (_ bv0 3)) (ite (= Verilog__main.i_rx_phy.fs_state_64_1 (_ bv4 3)) (ite (and Verilog__main.i_rx_phy.k_64_1 Verilog__main.i_rx_phy.rx_en_64_1) (_ bv5 3) (_ bv0 3)) (ite (= Verilog__main.i_rx_phy.fs_state_64_1 (_ bv5 3)) (ite (and Verilog__main.i_rx_phy.j_64_1 Verilog__main.i_rx_phy.rx_en_64_1) (_ bv6 3) (ite (and Verilog__main.i_rx_phy.k_64_1 Verilog__main.i_rx_phy.rx_en_64_1) (_ bv7 3) (_ bv0 3))) (ite (= Verilog__main.i_rx_phy.fs_state_64_1 (_ bv6 3)) (ite (and Verilog__main.i_rx_phy.k_64_1 Verilog__main.i_rx_phy.rx_en_64_1) (_ bv7 3) (_ bv0 3)) (ite (= Verilog__main.i_rx_phy.fs_state_64_1 (_ bv7 3)) (_ bv0 3) Verilog__main.i_rx_phy.fs_state_64_1)))))))) Verilog__main.i_rx_phy.fs_state_64_1))) (= Verilog__main.i_rx_phy.rx_valid_r_64_2 (ite Verilog__main.i_rx_phy.rx_valid_64_1 true (ite Verilog__main.i_rx_phy.fs_ce_64_1 false Verilog__main.i_rx_phy.rx_valid_r_64_1)))) (= Verilog__main.usb_rst_64_2 (= Verilog__main.rst_cnt_64_1 (_ bv31 5))) (= Verilog__main.rst_cnt_64_2 (ite (not Verilog__main.rst_64_1) (_ bv0 5) (ite (not (= Verilog__main.LineState_o_64_1 (_ bv0 2))) (_ bv0 5) (ite (and (not Verilog__main.usb_rst_64_1) Verilog__main.fs_ce_64_1) (bvadd Verilog__main.rst_cnt_64_1 (_ bv1 5)) Verilog__main.rst_cnt_64_1)))))) (and (and (and (= Verilog__main.reset_64_0_39_ (and Verilog__main.rst_64_0_39_ (not Verilog__main.usb_rst_64_0_39_))) (and (= Verilog__main.i_tx_phy.hold_64_0_39_ Verilog__main.i_tx_phy.stuff_64_0_39_) (= Verilog__main.i_tx_phy.sft_done_e_64_0_39_ (and Verilog__main.i_tx_phy.sft_done_64_0_39_ (not Verilog__main.i_tx_phy.sft_done_r_64_0_39_))) (= Verilog__main.i_tx_phy.stuff_64_0_39_ (= Verilog__main.i_tx_phy.one_cnt_64_0_39_ (_ bv6 3))) (= Verilog__main.i_tx_phy.eop_done_64_0_39_ Verilog__main.i_tx_phy.append_eop_sync3_64_0_39_)) (= Verilog__main.i_tx_phy.clk_64_0_39_ Verilog__main.clk_64_0_39_) (= Verilog__main.i_tx_phy.rst_64_0_39_ Verilog__main.reset_64_0_39_) (= Verilog__main.i_tx_phy.fs_ce_64_0_39_ Verilog__main.fs_ce_64_0_39_) (= Verilog__main.i_tx_phy.phy_mode_64_0_39_ Verilog__main.phy_tx_mode_64_0_39_) (= Verilog__main.i_tx_phy.txdp_64_0_39_ Verilog__main.txdp_64_0_39_) (= Verilog__main.i_tx_phy.txdn_64_0_39_ Verilog__main.txdn_64_0_39_) (= Verilog__main.i_tx_phy.txoe_64_0_39_ Verilog__main.txoe_64_0_39_) (= Verilog__main.i_tx_phy.DataOut_i_64_0_39_ Verilog__main.DataOut_i_64_0_39_) (= Verilog__main.i_tx_phy.TxValid_i_64_0_39_ Verilog__main.TxValid_i_64_0_39_) (= Verilog__main.i_tx_phy.TxReady_o_64_0_39_ Verilog__main.TxReady_o_64_0_39_) (and (= Verilog__main.i_rx_phy.RxActive_o_64_0_39_ Verilog__main.i_rx_phy.rx_active_64_0_39_) (= Verilog__main.i_rx_phy.RxValid_o_64_0_39_ Verilog__main.i_rx_phy.rx_valid_64_0_39_) (= Verilog__main.i_rx_phy.RxError_o_64_0_39_ false) (= Verilog__main.i_rx_phy.DataIn_o_64_0_39_ Verilog__main.i_rx_phy.hold_reg_64_0_39_) (= Verilog__main.i_rx_phy.LineState_64_0_39_ (concat (ite Verilog__main.i_rx_phy.rxdp_s1_64_0_39_ (_ bv1 1) (_ bv0 1)) (ite Verilog__main.i_rx_phy.rxdn_s1_64_0_39_ (_ bv1 1) (_ bv0 1)))) (= Verilog__main.i_rx_phy.k_64_0_39_ (and (not Verilog__main.i_rx_phy.rxdp_s_64_0_39_) Verilog__main.i_rx_phy.rxdn_s_64_0_39_)) (= Verilog__main.i_rx_phy.j_64_0_39_ (and Verilog__main.i_rx_phy.rxdp_s_64_0_39_ (not Verilog__main.i_rx_phy.rxdn_s_64_0_39_))) (= Verilog__main.i_rx_phy.se0_64_0_39_ (and (not Verilog__main.i_rx_phy.rxdp_s_64_0_39_) (not Verilog__main.i_rx_phy.rxdn_s_64_0_39_))) (= Verilog__main.i_rx_phy.lock_en_64_0_39_ Verilog__main.i_rx_phy.rx_en_64_0_39_) (= Verilog__main.i_rx_phy.change_64_0_39_ (or (xor Verilog__main.i_rx_phy.rxdp_s1r_64_0_39_ Verilog__main.i_rx_phy.rxdp_s1_64_0_39_) (xor Verilog__main.i_rx_phy.rxdn_s1r_64_0_39_ Verilog__main.i_rx_phy.rxdn_s1_64_0_39_))) (= Verilog__main.i_rx_phy.drop_bit_64_0_39_ (= Verilog__main.i_rx_phy.one_cnt_64_0_39_ (_ bv6 3)))) (= Verilog__main.i_rx_phy.clk_64_0_39_ Verilog__main.clk_64_0_39_) (= Verilog__main.i_rx_phy.rst_64_0_39_ Verilog__main.reset_64_0_39_) (= Verilog__main.i_rx_phy.fs_ce_64_0_39_ Verilog__main.fs_ce_64_0_39_) (= Verilog__main.i_rx_phy.rxd_64_0_39_ Verilog__main.rxd_64_0_39_) (= Verilog__main.i_rx_phy.rxdp_64_0_39_ Verilog__main.rxdp_64_0_39_) (= Verilog__main.i_rx_phy.rxdn_64_0_39_ Verilog__main.rxdn_64_0_39_) (= Verilog__main.i_rx_phy.DataIn_o_64_0_39_ Verilog__main.DataIn_o_64_0_39_) (= Verilog__main.i_rx_phy.RxValid_o_64_0_39_ Verilog__main.RxValid_o_64_0_39_) (= Verilog__main.i_rx_phy.RxActive_o_64_0_39_ Verilog__main.RxActive_o_64_0_39_) (= Verilog__main.i_rx_phy.RxError_o_64_0_39_ Verilog__main.RxError_o_64_0_39_) (= Verilog__main.i_rx_phy.RxEn_i_64_0_39_ Verilog__main.txoe_64_0_39_) (= Verilog__main.i_rx_phy.LineState_64_0_39_ Verilog__main.LineState_o_64_0_39_)) (and (= Verilog__main.reset_64_1_39_ (and Verilog__main.rst_64_1_39_ (not Verilog__main.usb_rst_64_1_39_))) (and (= Verilog__main.i_tx_phy.hold_64_1_39_ Verilog__main.i_tx_phy.stuff_64_1_39_) (= Verilog__main.i_tx_phy.sft_done_e_64_1_39_ (and Verilog__main.i_tx_phy.sft_done_64_1_39_ (not Verilog__main.i_tx_phy.sft_done_r_64_1_39_))) (= Verilog__main.i_tx_phy.stuff_64_1_39_ (= Verilog__main.i_tx_phy.one_cnt_64_1_39_ (_ bv6 3))) (= Verilog__main.i_tx_phy.eop_done_64_1_39_ Verilog__main.i_tx_phy.append_eop_sync3_64_1_39_)) (= Verilog__main.i_tx_phy.clk_64_1_39_ Verilog__main.clk_64_1_39_) (= Verilog__main.i_tx_phy.rst_64_1_39_ Verilog__main.reset_64_1_39_) (= Verilog__main.i_tx_phy.fs_ce_64_1_39_ Verilog__main.fs_ce_64_1_39_) (= Verilog__main.i_tx_phy.phy_mode_64_1_39_ Verilog__main.phy_tx_mode_64_1_39_) (= Verilog__main.i_tx_phy.txdp_64_1_39_ Verilog__main.txdp_64_1_39_) (= Verilog__main.i_tx_phy.txdn_64_1_39_ Verilog__main.txdn_64_1_39_) (= Verilog__main.i_tx_phy.txoe_64_1_39_ Verilog__main.txoe_64_1_39_) (= Verilog__main.i_tx_phy.DataOut_i_64_1_39_ Verilog__main.DataOut_i_64_1_39_) (= Verilog__main.i_tx_phy.TxValid_i_64_1_39_ Verilog__main.TxValid_i_64_1_39_) (= Verilog__main.i_tx_phy.TxReady_o_64_1_39_ Verilog__main.TxReady_o_64_1_39_) (and (= Verilog__main.i_rx_phy.RxActive_o_64_1_39_ Verilog__main.i_rx_phy.rx_active_64_1_39_) (= Verilog__main.i_rx_phy.RxValid_o_64_1_39_ Verilog__main.i_rx_phy.rx_valid_64_1_39_) (= Verilog__main.i_rx_phy.RxError_o_64_1_39_ false) (= Verilog__main.i_rx_phy.DataIn_o_64_1_39_ Verilog__main.i_rx_phy.hold_reg_64_1_39_) (= Verilog__main.i_rx_phy.LineState_64_1_39_ (concat (ite Verilog__main.i_rx_phy.rxdp_s1_64_1_39_ (_ bv1 1) (_ bv0 1)) (ite Verilog__main.i_rx_phy.rxdn_s1_64_1_39_ (_ bv1 1) (_ bv0 1)))) (= Verilog__main.i_rx_phy.k_64_1_39_ (and (not Verilog__main.i_rx_phy.rxdp_s_64_1_39_) Verilog__main.i_rx_phy.rxdn_s_64_1_39_)) (= Verilog__main.i_rx_phy.j_64_1_39_ (and Verilog__main.i_rx_phy.rxdp_s_64_1_39_ (not Verilog__main.i_rx_phy.rxdn_s_64_1_39_))) (= Verilog__main.i_rx_phy.se0_64_1_39_ (and (not Verilog__main.i_rx_phy.rxdp_s_64_1_39_) (not Verilog__main.i_rx_phy.rxdn_s_64_1_39_))) (= Verilog__main.i_rx_phy.lock_en_64_1_39_ Verilog__main.i_rx_phy.rx_en_64_1_39_) (= Verilog__main.i_rx_phy.change_64_1_39_ (or (xor Verilog__main.i_rx_phy.rxdp_s1r_64_1_39_ Verilog__main.i_rx_phy.rxdp_s1_64_1_39_) (xor Verilog__main.i_rx_phy.rxdn_s1r_64_1_39_ Verilog__main.i_rx_phy.rxdn_s1_64_1_39_))) (= Verilog__main.i_rx_phy.drop_bit_64_1_39_ (= Verilog__main.i_rx_phy.one_cnt_64_1_39_ (_ bv6 3)))) (= Verilog__main.i_rx_phy.clk_64_1_39_ Verilog__main.clk_64_1_39_) (= Verilog__main.i_rx_phy.rst_64_1_39_ Verilog__main.reset_64_1_39_) (= Verilog__main.i_rx_phy.fs_ce_64_1_39_ Verilog__main.fs_ce_64_1_39_) (= Verilog__main.i_rx_phy.rxd_64_1_39_ Verilog__main.rxd_64_1_39_) (= Verilog__main.i_rx_phy.rxdp_64_1_39_ Verilog__main.rxdp_64_1_39_) (= Verilog__main.i_rx_phy.rxdn_64_1_39_ Verilog__main.rxdn_64_1_39_) (= Verilog__main.i_rx_phy.DataIn_o_64_1_39_ Verilog__main.DataIn_o_64_1_39_) (= Verilog__main.i_rx_phy.RxValid_o_64_1_39_ Verilog__main.RxValid_o_64_1_39_) (= Verilog__main.i_rx_phy.RxActive_o_64_1_39_ Verilog__main.RxActive_o_64_1_39_) (= Verilog__main.i_rx_phy.RxError_o_64_1_39_ Verilog__main.RxError_o_64_1_39_) (= Verilog__main.i_rx_phy.RxEn_i_64_1_39_ Verilog__main.txoe_64_1_39_) (= Verilog__main.i_rx_phy.LineState_64_1_39_ Verilog__main.LineState_o_64_1_39_)) (and (and (= Verilog__main.i_tx_phy.sd_bs_o_64_0_39_ false) (= Verilog__main.i_tx_phy.sd_nrzi_o_64_0_39_ true) (= Verilog__main.i_tx_phy.append_eop_64_0_39_ false) (= Verilog__main.i_tx_phy.append_eop_sync1_64_0_39_ false) (= Verilog__main.i_tx_phy.append_eop_sync2_64_0_39_ false) (= Verilog__main.i_tx_phy.append_eop_sync3_64_0_39_ false) (= Verilog__main.i_tx_phy.txoe_r1_64_0_39_ false) (= Verilog__main.i_tx_phy.txoe_r2_64_0_39_ false) (= Verilog__main.i_tx_phy.txdp_64_0_39_ true) (= Verilog__main.i_tx_phy.txdn_64_0_39_ false) (= Verilog__main.i_tx_phy.txoe_64_0_39_ true) (= Verilog__main.i_tx_phy.TxReady_o_64_0_39_ false) (= Verilog__main.i_tx_phy.state_64_0_39_ (_ bv0 3)) (= Verilog__main.i_tx_phy.tx_ready_64_0_39_ false) (= Verilog__main.i_tx_phy.tx_ready_d_64_0_39_ false) (= Verilog__main.i_tx_phy.ld_sop_d_64_0_39_ false) (= Verilog__main.i_tx_phy.ld_data_d_64_0_39_ false) (= Verilog__main.i_tx_phy.ld_eop_d_64_0_39_ false) (= Verilog__main.i_tx_phy.tx_ip_64_0_39_ false) (= Verilog__main.i_tx_phy.tx_ip_sync_64_0_39_ false) (= Verilog__main.i_tx_phy.bit_cnt_64_0_39_ (_ bv0 3)) (= Verilog__main.i_tx_phy.hold_reg_64_0_39_ (_ bv0 8)) (= Verilog__main.i_tx_phy.sd_raw_o_64_0_39_ false) (= Verilog__main.i_tx_phy.data_done_64_0_39_ false) (= Verilog__main.i_tx_phy.sft_done_64_0_39_ false) (= Verilog__main.i_tx_phy.sft_done_r_64_0_39_ false) (= Verilog__main.i_tx_phy.ld_data_64_0_39_ false) (= Verilog__main.i_tx_phy.one_cnt_64_0_39_ (_ bv0 3))) (and (= Verilog__main.i_rx_phy.fs_ce_64_0_39_ false) (= Verilog__main.i_rx_phy.rxd_t1_64_0_39_ false) (= Verilog__main.i_rx_phy.rxd_s1_64_0_39_ false) (= Verilog__main.i_rx_phy.rxd_s_64_0_39_ false) (= Verilog__main.i_rx_phy.rxdp_t1_64_0_39_ false) (= Verilog__main.i_rx_phy.rxdp_s1_64_0_39_ false) (= Verilog__main.i_rx_phy.rxdp_s_64_0_39_ false) (= Verilog__main.i_rx_phy.rxdn_t1_64_0_39_ false) (= Verilog__main.i_rx_phy.rxdn_s1_64_0_39_ false) (= Verilog__main.i_rx_phy.rxdn_s_64_0_39_ false) (= Verilog__main.i_rx_phy.synced_d_64_0_39_ false) (= Verilog__main.i_rx_phy.rx_en_64_0_39_ false) (= Verilog__main.i_rx_phy.rx_active_64_0_39_ false) (= Verilog__main.i_rx_phy.bit_cnt_64_0_39_ (_ bv0 3)) (= Verilog__main.i_rx_phy.rx_valid1_64_0_39_ false) (= Verilog__main.i_rx_phy.rx_valid_64_0_39_ false) (= Verilog__main.i_rx_phy.shift_en_64_0_39_ false) (= Verilog__main.i_rx_phy.sd_r_64_0_39_ false) (= Verilog__main.i_rx_phy.sd_nrzi_64_0_39_ false) (= Verilog__main.i_rx_phy.hold_reg_64_0_39_ (_ bv0 8)) (= Verilog__main.i_rx_phy.one_cnt_64_0_39_ (_ bv0 3)) (= Verilog__main.i_rx_phy.dpll_state_64_0_39_ (_ bv1 2)) (= Verilog__main.i_rx_phy.fs_ce_d_64_0_39_ false) (= Verilog__main.i_rx_phy.rxdp_s1r_64_0_39_ false) (= Verilog__main.i_rx_phy.rxdn_s1r_64_0_39_ false) (= Verilog__main.i_rx_phy.fs_ce_r1_64_0_39_ false) (= Verilog__main.i_rx_phy.fs_ce_r2_64_0_39_ false) (= Verilog__main.i_rx_phy.fs_ce_r3_64_0_39_ false) (= Verilog__main.i_rx_phy.fs_state_64_0_39_ (_ bv0 3)) (= Verilog__main.i_rx_phy.rx_valid_r_64_0_39_ false)) (= Verilog__main.usb_rst_64_0_39_ false) (= Verilog__main.rst_cnt_64_0_39_ (_ bv0 5))) (and (and (= Verilog__main.i_tx_phy.sd_bs_o_64_1_39_ (ite (not Verilog__main.i_tx_phy.rst_64_0_39_) false (ite Verilog__main.i_tx_phy.fs_ce_64_0_39_ (ite (not Verilog__main.i_tx_phy.tx_ip_sync_64_0_39_) false (ite Verilog__main.i_tx_phy.stuff_64_0_39_ false (= ((_ extract 0 0) (ite Verilog__main.i_tx_phy.sd_raw_o_64_0_39_ (_ bv1 1) (_ bv0 1))) (_ bv1 1)))) Verilog__main.i_tx_phy.sd_bs_o_64_0_39_))) (= Verilog__main.i_tx_phy.sd_nrzi_o_64_1_39_ (ite (not Verilog__main.i_tx_phy.rst_64_0_39_) true (ite (or (not Verilog__main.i_tx_phy.tx_ip_sync_64_0_39_) (not Verilog__main.i_tx_phy.txoe_r1_64_0_39_)) true (ite Verilog__main.i_tx_phy.fs_ce_64_0_39_ (ite Verilog__main.i_tx_phy.sd_bs_o_64_0_39_ Verilog__main.i_tx_phy.sd_nrzi_o_64_0_39_ (not Verilog__main.i_tx_phy.sd_nrzi_o_64_0_39_)) Verilog__main.i_tx_phy.sd_nrzi_o_64_0_39_)))) (= Verilog__main.i_tx_phy.append_eop_64_1_39_ (ite (not Verilog__main.i_tx_phy.rst_64_0_39_) false (ite Verilog__main.i_tx_phy.ld_eop_d_64_0_39_ true (ite Verilog__main.i_tx_phy.append_eop_sync2_64_0_39_ false Verilog__main.i_tx_phy.append_eop_64_0_39_)))) (= Verilog__main.i_tx_phy.append_eop_sync1_64_1_39_ (ite (not Verilog__main.i_tx_phy.rst_64_0_39_) false (ite Verilog__main.i_tx_phy.fs_ce_64_0_39_ Verilog__main.i_tx_phy.append_eop_64_0_39_ Verilog__main.i_tx_phy.append_eop_sync1_64_0_39_))) (= Verilog__main.i_tx_phy.append_eop_sync2_64_1_39_ (ite (not Verilog__main.i_tx_phy.rst_64_0_39_) false (ite Verilog__main.i_tx_phy.fs_ce_64_0_39_ Verilog__main.i_tx_phy.append_eop_sync1_64_0_39_ Verilog__main.i_tx_phy.append_eop_sync2_64_0_39_))) (= Verilog__main.i_tx_phy.append_eop_sync3_64_1_39_ (ite (not Verilog__main.i_tx_phy.rst_64_0_39_) false (ite Verilog__main.i_tx_phy.fs_ce_64_0_39_ Verilog__main.i_tx_phy.append_eop_sync2_64_0_39_ Verilog__main.i_tx_phy.append_eop_sync3_64_0_39_))) (= Verilog__main.i_tx_phy.txoe_r1_64_1_39_ (ite (not Verilog__main.i_tx_phy.rst_64_0_39_) false (ite Verilog__main.i_tx_phy.fs_ce_64_0_39_ Verilog__main.i_tx_phy.tx_ip_sync_64_0_39_ Verilog__main.i_tx_phy.txoe_r1_64_0_39_))) (= Verilog__main.i_tx_phy.txoe_r2_64_1_39_ (ite (not Verilog__main.i_tx_phy.rst_64_0_39_) false (ite Verilog__main.i_tx_phy.fs_ce_64_0_39_ Verilog__main.i_tx_phy.txoe_r1_64_0_39_ Verilog__main.i_tx_phy.txoe_r2_64_0_39_))) (= Verilog__main.i_tx_phy.txdp_64_1_39_ (ite (not Verilog__main.i_tx_phy.rst_64_0_39_) true (ite Verilog__main.i_tx_phy.fs_ce_64_0_39_ (ite Verilog__main.i_tx_phy.phy_mode_64_0_39_ (and (not Verilog__main.i_tx_phy.append_eop_sync3_64_0_39_) Verilog__main.i_tx_phy.sd_nrzi_o_64_0_39_) Verilog__main.i_tx_phy.sd_nrzi_o_64_0_39_) Verilog__main.i_tx_phy.txdp_64_0_39_))) (= Verilog__main.i_tx_phy.txdn_64_1_39_ (ite (not Verilog__main.i_tx_phy.rst_64_0_39_) false (ite Verilog__main.i_tx_phy.fs_ce_64_0_39_ (ite Verilog__main.i_tx_phy.phy_mode_64_0_39_ (and (not Verilog__main.i_tx_phy.append_eop_sync3_64_0_39_) (not Verilog__main.i_tx_phy.sd_nrzi_o_64_0_39_)) Verilog__main.i_tx_phy.append_eop_sync3_64_0_39_) Verilog__main.i_tx_phy.txdn_64_0_39_))) (= Verilog__main.i_tx_phy.txoe_64_1_39_ (ite (not Verilog__main.i_tx_phy.rst_64_0_39_) true (ite Verilog__main.i_tx_phy.fs_ce_64_0_39_ (not (or Verilog__main.i_tx_phy.txoe_r1_64_0_39_ Verilog__main.i_tx_phy.txoe_r2_64_0_39_)) Verilog__main.i_tx_phy.txoe_64_0_39_))) (= Verilog__main.i_tx_phy.TxReady_o_64_1_39_ (ite (not Verilog__main.i_tx_phy.rst_64_0_39_) false (and Verilog__main.i_tx_phy.tx_ready_d_64_0_39_ Verilog__main.i_tx_phy.TxValid_i_64_0_39_))) (= Verilog__main.i_tx_phy.state_64_1_39_ (ite (not Verilog__main.i_tx_phy.rst_64_0_39_) (_ bv0 3) (ite (= Verilog__main.i_tx_phy.state_64_0_39_ (_ bv0 3)) (ite Verilog__main.i_tx_phy.TxValid_i_64_0_39_ (_ bv1 3) Verilog__main.i_tx_phy.state_64_0_39_) (ite (= Verilog__main.i_tx_phy.state_64_0_39_ (_ bv1 3)) (ite Verilog__main.i_tx_phy.sft_done_e_64_0_39_ (_ bv3 3) Verilog__main.i_tx_phy.state_64_0_39_) (ite (= Verilog__main.i_tx_phy.state_64_0_39_ (_ bv3 3)) (ite (and (not Verilog__main.i_tx_phy.data_done_64_0_39_) Verilog__main.i_tx_phy.sft_done_e_64_0_39_) (_ bv4 3) Verilog__main.i_tx_phy.state_64_0_39_) (ite (= Verilog__main.i_tx_phy.state_64_0_39_ (_ bv4 3)) (ite Verilog__main.i_tx_phy.eop_done_64_0_39_ (_ bv5 3) Verilog__main.i_tx_phy.state_64_0_39_) (ite (= Verilog__main.i_tx_phy.state_64_0_39_ (_ bv5 3)) (ite (and (not Verilog__main.i_tx_phy.eop_done_64_0_39_) Verilog__main.i_tx_phy.fs_ce_64_0_39_) (_ bv6 3) Verilog__main.i_tx_phy.state_64_0_39_) (ite (= Verilog__main.i_tx_phy.state_64_0_39_ (_ bv6 3)) (ite Verilog__main.i_tx_phy.fs_ce_64_0_39_ (_ bv0 3) Verilog__main.i_tx_phy.state_64_0_39_) Verilog__main.i_tx_phy.state_64_0_39_)))))))) (= Verilog__main.i_tx_phy.tx_ready_64_1_39_ Verilog__main.i_tx_phy.tx_ready_d_64_0_39_) (= Verilog__main.i_tx_phy.tx_ready_d_64_1_39_ (ite (not Verilog__main.i_tx_phy.rst_64_0_39_) Verilog__main.i_tx_phy.tx_ready_d_64_0_39_ (ite (= Verilog__main.i_tx_phy.state_64_0_39_ (_ bv0 3)) false (ite (= Verilog__main.i_tx_phy.state_64_0_39_ (_ bv1 3)) (ite Verilog__main.i_tx_phy.sft_done_e_64_0_39_ true false) (ite (= Verilog__main.i_tx_phy.state_64_0_39_ (_ bv3 3)) (ite (and Verilog__main.i_tx_phy.data_done_64_0_39_ Verilog__main.i_tx_phy.sft_done_e_64_0_39_) true false) false))))) (= Verilog__main.i_tx_phy.ld_sop_d_64_1_39_ (ite (not Verilog__main.i_tx_phy.rst_64_0_39_) Verilog__main.i_tx_phy.ld_sop_d_64_0_39_ (ite (= Verilog__main.i_tx_phy.state_64_0_39_ (_ bv0 3)) (ite Verilog__main.i_tx_phy.TxValid_i_64_0_39_ true false) false))) (= Verilog__main.i_tx_phy.ld_data_d_64_1_39_ (ite (not Verilog__main.i_tx_phy.rst_64_0_39_) Verilog__main.i_tx_phy.ld_data_d_64_0_39_ (ite (= Verilog__main.i_tx_phy.state_64_0_39_ (_ bv0 3)) false (ite (= Verilog__main.i_tx_phy.state_64_0_39_ (_ bv1 3)) (ite Verilog__main.i_tx_phy.sft_done_e_64_0_39_ true false) (ite (= Verilog__main.i_tx_phy.state_64_0_39_ (_ bv3 3)) (ite (and Verilog__main.i_tx_phy.data_done_64_0_39_ Verilog__main.i_tx_phy.sft_done_e_64_0_39_) true false) false))))) (= Verilog__main.i_tx_phy.ld_eop_d_64_1_39_ (ite (not Verilog__main.i_tx_phy.rst_64_0_39_) Verilog__main.i_tx_phy.ld_eop_d_64_0_39_ (ite (= Verilog__main.i_tx_phy.state_64_0_39_ (_ bv0 3)) false (ite (= Verilog__main.i_tx_phy.state_64_0_39_ (_ bv1 3)) false (ite (= Verilog__main.i_tx_phy.state_64_0_39_ (_ bv3 3)) (ite (and (not Verilog__main.i_tx_phy.data_done_64_0_39_) Verilog__main.i_tx_phy.sft_done_e_64_0_39_) true false) false))))) (= Verilog__main.i_tx_phy.tx_ip_64_1_39_ (ite (not Verilog__main.i_tx_phy.rst_64_0_39_) false (ite Verilog__main.i_tx_phy.ld_sop_d_64_0_39_ true (ite Verilog__main.i_tx_phy.eop_done_64_0_39_ false Verilog__main.i_tx_phy.tx_ip_64_0_39_)))) (= Verilog__main.i_tx_phy.tx_ip_sync_64_1_39_ (ite (not Verilog__main.i_tx_phy.rst_64_0_39_) false (ite Verilog__main.i_tx_phy.fs_ce_64_0_39_ Verilog__main.i_tx_phy.tx_ip_64_0_39_ Verilog__main.i_tx_phy.tx_ip_sync_64_0_39_))) (= Verilog__main.i_tx_phy.bit_cnt_64_1_39_ (ite (not Verilog__main.i_tx_phy.rst_64_0_39_) (_ bv0 3) (ite (not Verilog__main.i_tx_phy.tx_ip_sync_64_0_39_) (_ bv0 3) (ite (and Verilog__main.i_tx_phy.fs_ce_64_0_39_ (not Verilog__main.i_tx_phy.hold_64_0_39_)) (bvadd Verilog__main.i_tx_phy.bit_cnt_64_0_39_ (_ bv1 3)) Verilog__main.i_tx_phy.bit_cnt_64_0_39_)))) (= Verilog__main.i_tx_phy.hold_reg_64_1_39_ (ite Verilog__main.i_tx_phy.ld_sop_d_64_0_39_ (_ bv128 8) (ite Verilog__main.i_tx_phy.ld_data_64_0_39_ Verilog__main.i_tx_phy.DataOut_i_64_0_39_ Verilog__main.i_tx_phy.hold_reg_64_0_39_))) (= Verilog__main.i_tx_phy.sd_raw_o_64_1_39_ (ite (not Verilog__main.i_tx_phy.tx_ip_sync_64_0_39_) false (ite (= Verilog__main.i_tx_phy.bit_cnt_64_0_39_ (_ bv0 3)) (= ((_ extract 0 0) Verilog__main.i_tx_phy.hold_reg_64_0_39_) (_ bv1 1)) (ite (= Verilog__main.i_tx_phy.bit_cnt_64_0_39_ (_ bv1 3)) (= ((_ extract 1 1) Verilog__main.i_tx_phy.hold_reg_64_0_39_) (_ bv1 1)) (ite (= Verilog__main.i_tx_phy.bit_cnt_64_0_39_ (_ bv2 3)) (= ((_ extract 2 2) Verilog__main.i_tx_phy.hold_reg_64_0_39_) (_ bv1 1)) (ite (= Verilog__main.i_tx_phy.bit_cnt_64_0_39_ (_ bv3 3)) (= ((_ extract 3 3) Verilog__main.i_tx_phy.hold_reg_64_0_39_) (_ bv1 1)) (ite (= Verilog__main.i_tx_phy.bit_cnt_64_0_39_ (_ bv4 3)) (= ((_ extract 4 4) Verilog__main.i_tx_phy.hold_reg_64_0_39_) (_ bv1 1)) (ite (= Verilog__main.i_tx_phy.bit_cnt_64_0_39_ (_ bv5 3)) (= ((_ extract 5 5) Verilog__main.i_tx_phy.hold_reg_64_0_39_) (_ bv1 1)) (ite (= Verilog__main.i_tx_phy.bit_cnt_64_0_39_ (_ bv6 3)) (= ((_ extract 6 6) Verilog__main.i_tx_phy.hold_reg_64_0_39_) (_ bv1 1)) (ite (= Verilog__main.i_tx_phy.bit_cnt_64_0_39_ (_ bv7 3)) (= ((_ extract 7 7) Verilog__main.i_tx_phy.hold_reg_64_0_39_) (_ bv1 1)) Verilog__main.i_tx_phy.sd_raw_o_64_0_39_)))))))))) (= Verilog__main.i_tx_phy.data_done_64_1_39_ (ite (not Verilog__main.i_tx_phy.rst_64_0_39_) false (ite (and Verilog__main.i_tx_phy.TxValid_i_64_0_39_ (not Verilog__main.i_tx_phy.tx_ip_64_0_39_)) true (ite (not Verilog__main.i_tx_phy.TxValid_i_64_0_39_) false Verilog__main.i_tx_phy.data_done_64_0_39_)))) (= Verilog__main.i_tx_phy.sft_done_64_1_39_ (and (not Verilog__main.i_tx_phy.hold_64_0_39_) (= Verilog__main.i_tx_phy.bit_cnt_64_0_39_ (_ bv7 3)))) (= Verilog__main.i_tx_phy.sft_done_r_64_1_39_ Verilog__main.i_tx_phy.sft_done_64_0_39_) (= Verilog__main.i_tx_phy.ld_data_64_1_39_ Verilog__main.i_tx_phy.ld_data_d_64_0_39_) (= Verilog__main.i_tx_phy.one_cnt_64_1_39_ (ite (not Verilog__main.i_tx_phy.rst_64_0_39_) (_ bv0 3) (ite (not Verilog__main.i_tx_phy.tx_ip_sync_64_0_39_) (_ bv0 3) (ite Verilog__main.i_tx_phy.fs_ce_64_0_39_ (ite (or (not Verilog__main.i_tx_phy.sd_raw_o_64_0_39_) Verilog__main.i_tx_phy.stuff_64_0_39_) (_ bv0 3) (bvadd Verilog__main.i_tx_phy.one_cnt_64_0_39_ (_ bv1 3))) Verilog__main.i_tx_phy.one_cnt_64_0_39_))))) (and (= Verilog__main.i_rx_phy.fs_ce_64_1_39_ Verilog__main.i_rx_phy.fs_ce_r3_64_0_39_) (= Verilog__main.i_rx_phy.rxd_t1_64_1_39_ Verilog__main.i_rx_phy.rxd_64_0_39_) (= Verilog__main.i_rx_phy.rxd_s1_64_1_39_ Verilog__main.i_rx_phy.rxd_t1_64_0_39_) (= Verilog__main.i_rx_phy.rxd_s_64_1_39_ Verilog__main.i_rx_phy.rxd_s1_64_0_39_) (= Verilog__main.i_rx_phy.rxdp_t1_64_1_39_ Verilog__main.i_rx_phy.rxdp_64_0_39_) (= Verilog__main.i_rx_phy.rxdp_s1_64_1_39_ Verilog__main.i_rx_phy.rxdp_t1_64_0_39_) (= Verilog__main.i_rx_phy.rxdp_s_64_1_39_ Verilog__main.i_rx_phy.rxdp_s1_64_0_39_) (= Verilog__main.i_rx_phy.rxdn_t1_64_1_39_ Verilog__main.i_rx_phy.rxdn_64_0_39_) (= Verilog__main.i_rx_phy.rxdn_s1_64_1_39_ Verilog__main.i_rx_phy.rxdn_t1_64_0_39_) (= Verilog__main.i_rx_phy.rxdn_s_64_1_39_ Verilog__main.i_rx_phy.rxdn_s1_64_0_39_) (= Verilog__main.i_rx_phy.synced_d_64_1_39_ (ite (not Verilog__main.i_rx_phy.rst_64_0_39_) Verilog__main.i_rx_phy.synced_d_64_0_39_ (ite Verilog__main.i_rx_phy.fs_ce_64_0_39_ (ite (= Verilog__main.i_rx_phy.fs_state_64_0_39_ (_ bv0 3)) false (ite (= Verilog__main.i_rx_phy.fs_state_64_0_39_ (_ bv1 3)) false (ite (= Verilog__main.i_rx_phy.fs_state_64_0_39_ (_ bv2 3)) false (ite (= Verilog__main.i_rx_phy.fs_state_64_0_39_ (_ bv3 3)) false (ite (= Verilog__main.i_rx_phy.fs_state_64_0_39_ (_ bv4 3)) false (ite (= Verilog__main.i_rx_phy.fs_state_64_0_39_ (_ bv5 3)) false (ite (= Verilog__main.i_rx_phy.fs_state_64_0_39_ (_ bv6 3)) false (ite (= Verilog__main.i_rx_phy.fs_state_64_0_39_ (_ bv7 3)) (ite Verilog__main.i_rx_phy.k_64_0_39_ true false) false)))))))) false))) (= Verilog__main.i_rx_phy.rx_en_64_1_39_ Verilog__main.i_rx_phy.RxEn_i_64_0_39_) (= Verilog__main.i_rx_phy.rx_active_64_1_39_ (ite (not Verilog__main.i_rx_phy.rst_64_0_39_) false (ite (and Verilog__main.i_rx_phy.synced_d_64_0_39_ Verilog__main.i_rx_phy.rx_en_64_0_39_) true (ite (and Verilog__main.i_rx_phy.se0_64_0_39_ Verilog__main.i_rx_phy.rx_valid_r_64_0_39_) false Verilog__main.i_rx_phy.rx_active_64_0_39_)))) (= Verilog__main.i_rx_phy.bit_cnt_64_1_39_ (ite (not Verilog__main.i_rx_phy.rst_64_0_39_) (_ bv0 3) (ite (not Verilog__main.i_rx_phy.shift_en_64_0_39_) (_ bv0 3) (ite (and Verilog__main.i_rx_phy.fs_ce_64_0_39_ (not Verilog__main.i_rx_phy.drop_bit_64_0_39_)) (bvadd Verilog__main.i_rx_phy.bit_cnt_64_0_39_ (_ bv1 3)) Verilog__main.i_rx_phy.bit_cnt_64_0_39_)))) (= Verilog__main.i_rx_phy.rx_valid1_64_1_39_ (ite (not Verilog__main.i_rx_phy.rst_64_0_39_) false (ite (and (and Verilog__main.i_rx_phy.fs_ce_64_0_39_ (not Verilog__main.i_rx_phy.drop_bit_64_0_39_)) (= Verilog__main.i_rx_phy.bit_cnt_64_0_39_ (_ bv7 3))) true (ite (and (and Verilog__main.i_rx_phy.rx_valid1_64_0_39_ Verilog__main.i_rx_phy.fs_ce_64_0_39_) (not Verilog__main.i_rx_phy.drop_bit_64_0_39_)) false Verilog__main.i_rx_phy.rx_valid1_64_0_39_)))) (= Verilog__main.i_rx_phy.rx_valid_64_1_39_ (and (and (not Verilog__main.i_rx_phy.drop_bit_64_0_39_) Verilog__main.i_rx_phy.rx_valid1_64_0_39_) Verilog__main.i_rx_phy.fs_ce_64_0_39_)) (= Verilog__main.i_rx_phy.shift_en_64_1_39_ (ite Verilog__main.i_rx_phy.fs_ce_64_0_39_ (or Verilog__main.i_rx_phy.synced_d_64_0_39_ Verilog__main.i_rx_phy.rx_active_64_0_39_) Verilog__main.i_rx_phy.shift_en_64_0_39_)) (= Verilog__main.i_rx_phy.sd_r_64_1_39_ (ite Verilog__main.i_rx_phy.fs_ce_64_0_39_ Verilog__main.i_rx_phy.rxd_s_64_0_39_ Verilog__main.i_rx_phy.sd_r_64_0_39_)) (= Verilog__main.i_rx_phy.sd_nrzi_64_1_39_ (ite (not Verilog__main.i_rx_phy.rst_64_0_39_) false (ite (and Verilog__main.i_rx_phy.rx_active_64_0_39_ Verilog__main.i_rx_phy.fs_ce_64_0_39_) (not (xor Verilog__main.i_rx_phy.rxd_s_64_0_39_ Verilog__main.i_rx_phy.sd_r_64_0_39_)) Verilog__main.i_rx_phy.sd_nrzi_64_0_39_))) (= Verilog__main.i_rx_phy.hold_reg_64_1_39_ (ite (and (and Verilog__main.i_rx_phy.fs_ce_64_0_39_ Verilog__main.i_rx_phy.shift_en_64_0_39_) (not Verilog__main.i_rx_phy.drop_bit_64_0_39_)) (concat (ite Verilog__main.i_rx_phy.sd_nrzi_64_0_39_ (_ bv1 1) (_ bv0 1)) ((_ extract 7 1) Verilog__main.i_rx_phy.hold_reg_64_0_39_)) Verilog__main.i_rx_phy.hold_reg_64_0_39_)) (= Verilog__main.i_rx_phy.one_cnt_64_1_39_ (ite (not Verilog__main.i_rx_phy.rst_64_0_39_) (_ bv0 3) (ite (not Verilog__main.i_rx_phy.shift_en_64_0_39_) (_ bv0 3) (ite Verilog__main.i_rx_phy.fs_ce_64_0_39_ (ite (or (not Verilog__main.i_rx_phy.sd_nrzi_64_0_39_) Verilog__main.i_rx_phy.drop_bit_64_0_39_) (_ bv0 3) (bvadd Verilog__main.i_rx_phy.one_cnt_64_0_39_ (_ bv1 3))) Verilog__main.i_rx_phy.one_cnt_64_0_39_)))) (= Verilog__main.i_rx_phy.dpll_state_64_1_39_ (ite (not Verilog__main.i_rx_phy.rst_64_0_39_) (_ bv1 2) (ite (= Verilog__main.i_rx_phy.dpll_state_64_0_39_ (_ bv0 2)) (ite (and Verilog__main.i_rx_phy.lock_en_64_0_39_ Verilog__main.i_rx_phy.change_64_0_39_) (_ bv0 2) (_ bv1 2)) (ite (= Verilog__main.i_rx_phy.dpll_state_64_0_39_ (_ bv1 2)) (ite (and Verilog__main.i_rx_phy.lock_en_64_0_39_ Verilog__main.i_rx_phy.change_64_0_39_) (_ bv3 2) (_ bv2 2)) (ite (= Verilog__main.i_rx_phy.dpll_state_64_0_39_ (_ bv2 2)) (ite (and Verilog__main.i_rx_phy.lock_en_64_0_39_ Verilog__main.i_rx_phy.change_64_0_39_) (_ bv0 2) (_ bv3 2)) (ite (= Verilog__main.i_rx_phy.dpll_state_64_0_39_ (_ bv3 2)) (ite (and Verilog__main.i_rx_phy.lock_en_64_0_39_ Verilog__main.i_rx_phy.change_64_0_39_) (_ bv0 2) (_ bv0 2)) Verilog__main.i_rx_phy.dpll_state_64_0_39_)))))) (= Verilog__main.i_rx_phy.fs_ce_d_64_1_39_ (ite (not Verilog__main.i_rx_phy.rst_64_0_39_) Verilog__main.i_rx_phy.fs_ce_d_64_0_39_ (ite (= Verilog__main.i_rx_phy.dpll_state_64_0_39_ (_ bv0 2)) false (ite (= Verilog__main.i_rx_phy.dpll_state_64_0_39_ (_ bv1 2)) true false)))) (= Verilog__main.i_rx_phy.rxdp_s1r_64_1_39_ Verilog__main.i_rx_phy.rxdp_s1_64_0_39_) (= Verilog__main.i_rx_phy.rxdn_s1r_64_1_39_ Verilog__main.i_rx_phy.rxdn_s1_64_0_39_) (= Verilog__main.i_rx_phy.fs_ce_r1_64_1_39_ Verilog__main.i_rx_phy.fs_ce_d_64_0_39_) (= Verilog__main.i_rx_phy.fs_ce_r2_64_1_39_ Verilog__main.i_rx_phy.fs_ce_r1_64_0_39_) (= Verilog__main.i_rx_phy.fs_ce_r3_64_1_39_ Verilog__main.i_rx_phy.fs_ce_r2_64_0_39_) (= Verilog__main.i_rx_phy.fs_state_64_1_39_ (ite (not Verilog__main.i_rx_phy.rst_64_0_39_) (_ bv0 3) (ite Verilog__main.i_rx_phy.fs_ce_64_0_39_ (ite (= Verilog__main.i_rx_phy.fs_state_64_0_39_ (_ bv0 3)) (ite (and Verilog__main.i_rx_phy.k_64_0_39_ Verilog__main.i_rx_phy.rx_en_64_0_39_) (_ bv1 3) Verilog__main.i_rx_phy.fs_state_64_0_39_) (ite (= Verilog__main.i_rx_phy.fs_state_64_0_39_ (_ bv1 3)) (ite (and Verilog__main.i_rx_phy.j_64_0_39_ Verilog__main.i_rx_phy.rx_en_64_0_39_) (_ bv2 3) (_ bv0 3)) (ite (= Verilog__main.i_rx_phy.fs_state_64_0_39_ (_ bv2 3)) (ite (and Verilog__main.i_rx_phy.k_64_0_39_ Verilog__main.i_rx_phy.rx_en_64_0_39_) (_ bv3 3) (_ bv0 3)) (ite (= Verilog__main.i_rx_phy.fs_state_64_0_39_ (_ bv3 3)) (ite (and Verilog__main.i_rx_phy.j_64_0_39_ Verilog__main.i_rx_phy.rx_en_64_0_39_) (_ bv4 3) (_ bv0 3)) (ite (= Verilog__main.i_rx_phy.fs_state_64_0_39_ (_ bv4 3)) (ite (and Verilog__main.i_rx_phy.k_64_0_39_ Verilog__main.i_rx_phy.rx_en_64_0_39_) (_ bv5 3) (_ bv0 3)) (ite (= Verilog__main.i_rx_phy.fs_state_64_0_39_ (_ bv5 3)) (ite (and Verilog__main.i_rx_phy.j_64_0_39_ Verilog__main.i_rx_phy.rx_en_64_0_39_) (_ bv6 3) (ite (and Verilog__main.i_rx_phy.k_64_0_39_ Verilog__main.i_rx_phy.rx_en_64_0_39_) (_ bv7 3) (_ bv0 3))) (ite (= Verilog__main.i_rx_phy.fs_state_64_0_39_ (_ bv6 3)) (ite (and Verilog__main.i_rx_phy.k_64_0_39_ Verilog__main.i_rx_phy.rx_en_64_0_39_) (_ bv7 3) (_ bv0 3)) (ite (= Verilog__main.i_rx_phy.fs_state_64_0_39_ (_ bv7 3)) (_ bv0 3) Verilog__main.i_rx_phy.fs_state_64_0_39_)))))))) Verilog__main.i_rx_phy.fs_state_64_0_39_))) (= Verilog__main.i_rx_phy.rx_valid_r_64_1_39_ (ite Verilog__main.i_rx_phy.rx_valid_64_0_39_ true (ite Verilog__main.i_rx_phy.fs_ce_64_0_39_ false Verilog__main.i_rx_phy.rx_valid_r_64_0_39_)))) (= Verilog__main.usb_rst_64_1_39_ (= Verilog__main.rst_cnt_64_0_39_ (_ bv31 5))) (= Verilog__main.rst_cnt_64_1_39_ (ite (not Verilog__main.rst_64_0_39_) (_ bv0 5) (ite (not (= Verilog__main.LineState_o_64_0_39_ (_ bv0 2))) (_ bv0 5) (ite (and (not Verilog__main.usb_rst_64_0_39_) Verilog__main.fs_ce_64_0_39_) (bvadd Verilog__main.rst_cnt_64_0_39_ (_ bv1 5)) Verilog__main.rst_cnt_64_0_39_)))))) (or (and (= Verilog__main.reset_64_2 Verilog__main.reset_64_0_39_) (= Verilog__main.rst_64_2 Verilog__main.rst_64_0_39_) (= Verilog__main.usb_rst_64_2 Verilog__main.usb_rst_64_0_39_) (= Verilog__main.i_tx_phy.hold_64_2 Verilog__main.i_tx_phy.hold_64_0_39_) (= Verilog__main.i_tx_phy.stuff_64_2 Verilog__main.i_tx_phy.stuff_64_0_39_) (= Verilog__main.i_tx_phy.sft_done_e_64_2 Verilog__main.i_tx_phy.sft_done_e_64_0_39_) (= Verilog__main.i_tx_phy.sft_done_64_2 Verilog__main.i_tx_phy.sft_done_64_0_39_) (= Verilog__main.i_tx_phy.sft_done_r_64_2 Verilog__main.i_tx_phy.sft_done_r_64_0_39_) (= Verilog__main.i_tx_phy.one_cnt_64_2 Verilog__main.i_tx_phy.one_cnt_64_0_39_) (= Verilog__main.i_tx_phy.eop_done_64_2 Verilog__main.i_tx_phy.eop_done_64_0_39_) (= Verilog__main.i_tx_phy.append_eop_sync3_64_2 Verilog__main.i_tx_phy.append_eop_sync3_64_0_39_) (= Verilog__main.i_tx_phy.clk_64_2 Verilog__main.i_tx_phy.clk_64_0_39_) (= Verilog__main.clk_64_2 Verilog__main.clk_64_0_39_) (= Verilog__main.i_tx_phy.rst_64_2 Verilog__main.i_tx_phy.rst_64_0_39_) (= Verilog__main.i_tx_phy.fs_ce_64_2 Verilog__main.i_tx_phy.fs_ce_64_0_39_) (= Verilog__main.fs_ce_64_2 Verilog__main.fs_ce_64_0_39_) (= Verilog__main.i_tx_phy.phy_mode_64_2 Verilog__main.i_tx_phy.phy_mode_64_0_39_) (= Verilog__main.phy_tx_mode_64_2 Verilog__main.phy_tx_mode_64_0_39_) (= Verilog__main.i_tx_phy.txdp_64_2 Verilog__main.i_tx_phy.txdp_64_0_39_) (= Verilog__main.txdp_64_2 Verilog__main.txdp_64_0_39_) (= Verilog__main.i_tx_phy.txdn_64_2 Verilog__main.i_tx_phy.txdn_64_0_39_) (= Verilog__main.txdn_64_2 Verilog__main.txdn_64_0_39_) (= Verilog__main.i_tx_phy.txoe_64_2 Verilog__main.i_tx_phy.txoe_64_0_39_) (= Verilog__main.txoe_64_2 Verilog__main.txoe_64_0_39_) (= Verilog__main.i_tx_phy.DataOut_i_64_2 Verilog__main.i_tx_phy.DataOut_i_64_0_39_) (= Verilog__main.DataOut_i_64_2 Verilog__main.DataOut_i_64_0_39_) (= Verilog__main.i_tx_phy.TxValid_i_64_2 Verilog__main.i_tx_phy.TxValid_i_64_0_39_) (= Verilog__main.TxValid_i_64_2 Verilog__main.TxValid_i_64_0_39_) (= Verilog__main.i_tx_phy.TxReady_o_64_2 Verilog__main.i_tx_phy.TxReady_o_64_0_39_) (= Verilog__main.TxReady_o_64_2 Verilog__main.TxReady_o_64_0_39_) (= Verilog__main.i_rx_phy.RxActive_o_64_2 Verilog__main.i_rx_phy.RxActive_o_64_0_39_) (= Verilog__main.i_rx_phy.rx_active_64_2 Verilog__main.i_rx_phy.rx_active_64_0_39_) (= Verilog__main.i_rx_phy.RxValid_o_64_2 Verilog__main.i_rx_phy.RxValid_o_64_0_39_) (= Verilog__main.i_rx_phy.rx_valid_64_2 Verilog__main.i_rx_phy.rx_valid_64_0_39_) (= Verilog__main.i_rx_phy.RxError_o_64_2 Verilog__main.i_rx_phy.RxError_o_64_0_39_) (= Verilog__main.i_rx_phy.DataIn_o_64_2 Verilog__main.i_rx_phy.DataIn_o_64_0_39_) (= Verilog__main.i_rx_phy.hold_reg_64_2 Verilog__main.i_rx_phy.hold_reg_64_0_39_) (= Verilog__main.i_rx_phy.LineState_64_2 Verilog__main.i_rx_phy.LineState_64_0_39_) (= Verilog__main.i_rx_phy.rxdp_s1_64_2 Verilog__main.i_rx_phy.rxdp_s1_64_0_39_) (= Verilog__main.i_rx_phy.rxdn_s1_64_2 Verilog__main.i_rx_phy.rxdn_s1_64_0_39_) (= Verilog__main.i_rx_phy.k_64_2 Verilog__main.i_rx_phy.k_64_0_39_) (= Verilog__main.i_rx_phy.rxdp_s_64_2 Verilog__main.i_rx_phy.rxdp_s_64_0_39_) (= Verilog__main.i_rx_phy.rxdn_s_64_2 Verilog__main.i_rx_phy.rxdn_s_64_0_39_) (= Verilog__main.i_rx_phy.j_64_2 Verilog__main.i_rx_phy.j_64_0_39_) (= Verilog__main.i_rx_phy.se0_64_2 Verilog__main.i_rx_phy.se0_64_0_39_) (= Verilog__main.i_rx_phy.lock_en_64_2 Verilog__main.i_rx_phy.lock_en_64_0_39_) (= Verilog__main.i_rx_phy.rx_en_64_2 Verilog__main.i_rx_phy.rx_en_64_0_39_) (= Verilog__main.i_rx_phy.change_64_2 Verilog__main.i_rx_phy.change_64_0_39_) (= Verilog__main.i_rx_phy.rxdp_s1r_64_2 Verilog__main.i_rx_phy.rxdp_s1r_64_0_39_) (= Verilog__main.i_rx_phy.rxdn_s1r_64_2 Verilog__main.i_rx_phy.rxdn_s1r_64_0_39_) (= Verilog__main.i_rx_phy.drop_bit_64_2 Verilog__main.i_rx_phy.drop_bit_64_0_39_) (= Verilog__main.i_rx_phy.one_cnt_64_2 Verilog__main.i_rx_phy.one_cnt_64_0_39_) (= Verilog__main.i_rx_phy.clk_64_2 Verilog__main.i_rx_phy.clk_64_0_39_) (= Verilog__main.i_rx_phy.rst_64_2 Verilog__main.i_rx_phy.rst_64_0_39_) (= Verilog__main.i_rx_phy.fs_ce_64_2 Verilog__main.i_rx_phy.fs_ce_64_0_39_) (= Verilog__main.i_rx_phy.rxd_64_2 Verilog__main.i_rx_phy.rxd_64_0_39_) (= Verilog__main.rxd_64_2 Verilog__main.rxd_64_0_39_) (= Verilog__main.i_rx_phy.rxdp_64_2 Verilog__main.i_rx_phy.rxdp_64_0_39_) (= Verilog__main.rxdp_64_2 Verilog__main.rxdp_64_0_39_) (= Verilog__main.i_rx_phy.rxdn_64_2 Verilog__main.i_rx_phy.rxdn_64_0_39_) (= Verilog__main.rxdn_64_2 Verilog__main.rxdn_64_0_39_) (= Verilog__main.DataIn_o_64_2 Verilog__main.DataIn_o_64_0_39_) (= Verilog__main.RxValid_o_64_2 Verilog__main.RxValid_o_64_0_39_) (= Verilog__main.RxActive_o_64_2 Verilog__main.RxActive_o_64_0_39_) (= Verilog__main.RxError_o_64_2 Verilog__main.RxError_o_64_0_39_) (= Verilog__main.i_rx_phy.RxEn_i_64_2 Verilog__main.i_rx_phy.RxEn_i_64_0_39_) (= Verilog__main.LineState_o_64_2 Verilog__main.LineState_o_64_0_39_) (= Verilog__main.i_tx_phy.sd_bs_o_64_2 Verilog__main.i_tx_phy.sd_bs_o_64_0_39_) (= Verilog__main.i_tx_phy.sd_nrzi_o_64_2 Verilog__main.i_tx_phy.sd_nrzi_o_64_0_39_) (= Verilog__main.i_tx_phy.append_eop_64_2 Verilog__main.i_tx_phy.append_eop_64_0_39_) (= Verilog__main.i_tx_phy.append_eop_sync1_64_2 Verilog__main.i_tx_phy.append_eop_sync1_64_0_39_) (= Verilog__main.i_tx_phy.append_eop_sync2_64_2 Verilog__main.i_tx_phy.append_eop_sync2_64_0_39_) (= Verilog__main.i_tx_phy.txoe_r1_64_2 Verilog__main.i_tx_phy.txoe_r1_64_0_39_) (= Verilog__main.i_tx_phy.txoe_r2_64_2 Verilog__main.i_tx_phy.txoe_r2_64_0_39_) (= Verilog__main.i_tx_phy.state_64_2 Verilog__main.i_tx_phy.state_64_0_39_) (= Verilog__main.i_tx_phy.tx_ready_64_2 Verilog__main.i_tx_phy.tx_ready_64_0_39_) (= Verilog__main.i_tx_phy.tx_ready_d_64_2 Verilog__main.i_tx_phy.tx_ready_d_64_0_39_) (= Verilog__main.i_tx_phy.ld_sop_d_64_2 Verilog__main.i_tx_phy.ld_sop_d_64_0_39_) (= Verilog__main.i_tx_phy.ld_data_d_64_2 Verilog__main.i_tx_phy.ld_data_d_64_0_39_) (= Verilog__main.i_tx_phy.ld_eop_d_64_2 Verilog__main.i_tx_phy.ld_eop_d_64_0_39_) (= Verilog__main.i_tx_phy.tx_ip_64_2 Verilog__main.i_tx_phy.tx_ip_64_0_39_) (= Verilog__main.i_tx_phy.tx_ip_sync_64_2 Verilog__main.i_tx_phy.tx_ip_sync_64_0_39_) (= Verilog__main.i_tx_phy.bit_cnt_64_2 Verilog__main.i_tx_phy.bit_cnt_64_0_39_) (= Verilog__main.i_tx_phy.hold_reg_64_2 Verilog__main.i_tx_phy.hold_reg_64_0_39_) (= Verilog__main.i_tx_phy.sd_raw_o_64_2 Verilog__main.i_tx_phy.sd_raw_o_64_0_39_) (= Verilog__main.i_tx_phy.data_done_64_2 Verilog__main.i_tx_phy.data_done_64_0_39_) (= Verilog__main.i_tx_phy.ld_data_64_2 Verilog__main.i_tx_phy.ld_data_64_0_39_) (= Verilog__main.i_rx_phy.rxd_t1_64_2 Verilog__main.i_rx_phy.rxd_t1_64_0_39_) (= Verilog__main.i_rx_phy.rxd_s1_64_2 Verilog__main.i_rx_phy.rxd_s1_64_0_39_) (= Verilog__main.i_rx_phy.rxd_s_64_2 Verilog__main.i_rx_phy.rxd_s_64_0_39_) (= Verilog__main.i_rx_phy.rxdp_t1_64_2 Verilog__main.i_rx_phy.rxdp_t1_64_0_39_) (= Verilog__main.i_rx_phy.rxdn_t1_64_2 Verilog__main.i_rx_phy.rxdn_t1_64_0_39_) (= Verilog__main.i_rx_phy.synced_d_64_2 Verilog__main.i_rx_phy.synced_d_64_0_39_) (= Verilog__main.i_rx_phy.bit_cnt_64_2 Verilog__main.i_rx_phy.bit_cnt_64_0_39_) (= Verilog__main.i_rx_phy.rx_valid1_64_2 Verilog__main.i_rx_phy.rx_valid1_64_0_39_) (= Verilog__main.i_rx_phy.shift_en_64_2 Verilog__main.i_rx_phy.shift_en_64_0_39_) (= Verilog__main.i_rx_phy.sd_r_64_2 Verilog__main.i_rx_phy.sd_r_64_0_39_) (= Verilog__main.i_rx_phy.sd_nrzi_64_2 Verilog__main.i_rx_phy.sd_nrzi_64_0_39_) (= Verilog__main.i_rx_phy.dpll_state_64_2 Verilog__main.i_rx_phy.dpll_state_64_0_39_) (= Verilog__main.i_rx_phy.fs_ce_d_64_2 Verilog__main.i_rx_phy.fs_ce_d_64_0_39_) (= Verilog__main.i_rx_phy.fs_ce_r1_64_2 Verilog__main.i_rx_phy.fs_ce_r1_64_0_39_) (= Verilog__main.i_rx_phy.fs_ce_r2_64_2 Verilog__main.i_rx_phy.fs_ce_r2_64_0_39_) (= Verilog__main.i_rx_phy.fs_ce_r3_64_2 Verilog__main.i_rx_phy.fs_ce_r3_64_0_39_) (= Verilog__main.i_rx_phy.fs_state_64_2 Verilog__main.i_rx_phy.fs_state_64_0_39_) (= Verilog__main.i_rx_phy.rx_valid_r_64_2 Verilog__main.i_rx_phy.rx_valid_r_64_0_39_) (= Verilog__main.rst_cnt_64_2 Verilog__main.rst_cnt_64_0_39_)) (and (= Verilog__main.reset_64_2 Verilog__main.reset_64_1_39_) (= Verilog__main.rst_64_2 Verilog__main.rst_64_1_39_) (= Verilog__main.usb_rst_64_2 Verilog__main.usb_rst_64_1_39_) (= Verilog__main.i_tx_phy.hold_64_2 Verilog__main.i_tx_phy.hold_64_1_39_) (= Verilog__main.i_tx_phy.stuff_64_2 Verilog__main.i_tx_phy.stuff_64_1_39_) (= Verilog__main.i_tx_phy.sft_done_e_64_2 Verilog__main.i_tx_phy.sft_done_e_64_1_39_) (= Verilog__main.i_tx_phy.sft_done_64_2 Verilog__main.i_tx_phy.sft_done_64_1_39_) (= Verilog__main.i_tx_phy.sft_done_r_64_2 Verilog__main.i_tx_phy.sft_done_r_64_1_39_) (= Verilog__main.i_tx_phy.one_cnt_64_2 Verilog__main.i_tx_phy.one_cnt_64_1_39_) (= Verilog__main.i_tx_phy.eop_done_64_2 Verilog__main.i_tx_phy.eop_done_64_1_39_) (= Verilog__main.i_tx_phy.append_eop_sync3_64_2 Verilog__main.i_tx_phy.append_eop_sync3_64_1_39_) (= Verilog__main.i_tx_phy.clk_64_2 Verilog__main.i_tx_phy.clk_64_1_39_) (= Verilog__main.clk_64_2 Verilog__main.clk_64_1_39_) (= Verilog__main.i_tx_phy.rst_64_2 Verilog__main.i_tx_phy.rst_64_1_39_) (= Verilog__main.i_tx_phy.fs_ce_64_2 Verilog__main.i_tx_phy.fs_ce_64_1_39_) (= Verilog__main.fs_ce_64_2 Verilog__main.fs_ce_64_1_39_) (= Verilog__main.i_tx_phy.phy_mode_64_2 Verilog__main.i_tx_phy.phy_mode_64_1_39_) (= Verilog__main.phy_tx_mode_64_2 Verilog__main.phy_tx_mode_64_1_39_) (= Verilog__main.i_tx_phy.txdp_64_2 Verilog__main.i_tx_phy.txdp_64_1_39_) (= Verilog__main.txdp_64_2 Verilog__main.txdp_64_1_39_) (= Verilog__main.i_tx_phy.txdn_64_2 Verilog__main.i_tx_phy.txdn_64_1_39_) (= Verilog__main.txdn_64_2 Verilog__main.txdn_64_1_39_) (= Verilog__main.i_tx_phy.txoe_64_2 Verilog__main.i_tx_phy.txoe_64_1_39_) (= Verilog__main.txoe_64_2 Verilog__main.txoe_64_1_39_) (= Verilog__main.i_tx_phy.DataOut_i_64_2 Verilog__main.i_tx_phy.DataOut_i_64_1_39_) (= Verilog__main.DataOut_i_64_2 Verilog__main.DataOut_i_64_1_39_) (= Verilog__main.i_tx_phy.TxValid_i_64_2 Verilog__main.i_tx_phy.TxValid_i_64_1_39_) (= Verilog__main.TxValid_i_64_2 Verilog__main.TxValid_i_64_1_39_) (= Verilog__main.i_tx_phy.TxReady_o_64_2 Verilog__main.i_tx_phy.TxReady_o_64_1_39_) (= Verilog__main.TxReady_o_64_2 Verilog__main.TxReady_o_64_1_39_) (= Verilog__main.i_rx_phy.RxActive_o_64_2 Verilog__main.i_rx_phy.RxActive_o_64_1_39_) (= Verilog__main.i_rx_phy.rx_active_64_2 Verilog__main.i_rx_phy.rx_active_64_1_39_) (= Verilog__main.i_rx_phy.RxValid_o_64_2 Verilog__main.i_rx_phy.RxValid_o_64_1_39_) (= Verilog__main.i_rx_phy.rx_valid_64_2 Verilog__main.i_rx_phy.rx_valid_64_1_39_) (= Verilog__main.i_rx_phy.RxError_o_64_2 Verilog__main.i_rx_phy.RxError_o_64_1_39_) (= Verilog__main.i_rx_phy.DataIn_o_64_2 Verilog__main.i_rx_phy.DataIn_o_64_1_39_) (= Verilog__main.i_rx_phy.hold_reg_64_2 Verilog__main.i_rx_phy.hold_reg_64_1_39_) (= Verilog__main.i_rx_phy.LineState_64_2 Verilog__main.i_rx_phy.LineState_64_1_39_) (= Verilog__main.i_rx_phy.rxdp_s1_64_2 Verilog__main.i_rx_phy.rxdp_s1_64_1_39_) (= Verilog__main.i_rx_phy.rxdn_s1_64_2 Verilog__main.i_rx_phy.rxdn_s1_64_1_39_) (= Verilog__main.i_rx_phy.k_64_2 Verilog__main.i_rx_phy.k_64_1_39_) (= Verilog__main.i_rx_phy.rxdp_s_64_2 Verilog__main.i_rx_phy.rxdp_s_64_1_39_) (= Verilog__main.i_rx_phy.rxdn_s_64_2 Verilog__main.i_rx_phy.rxdn_s_64_1_39_) (= Verilog__main.i_rx_phy.j_64_2 Verilog__main.i_rx_phy.j_64_1_39_) (= Verilog__main.i_rx_phy.se0_64_2 Verilog__main.i_rx_phy.se0_64_1_39_) (= Verilog__main.i_rx_phy.lock_en_64_2 Verilog__main.i_rx_phy.lock_en_64_1_39_) (= Verilog__main.i_rx_phy.rx_en_64_2 Verilog__main.i_rx_phy.rx_en_64_1_39_) (= Verilog__main.i_rx_phy.change_64_2 Verilog__main.i_rx_phy.change_64_1_39_) (= Verilog__main.i_rx_phy.rxdp_s1r_64_2 Verilog__main.i_rx_phy.rxdp_s1r_64_1_39_) (= Verilog__main.i_rx_phy.rxdn_s1r_64_2 Verilog__main.i_rx_phy.rxdn_s1r_64_1_39_) (= Verilog__main.i_rx_phy.drop_bit_64_2 Verilog__main.i_rx_phy.drop_bit_64_1_39_) (= Verilog__main.i_rx_phy.one_cnt_64_2 Verilog__main.i_rx_phy.one_cnt_64_1_39_) (= Verilog__main.i_rx_phy.clk_64_2 Verilog__main.i_rx_phy.clk_64_1_39_) (= Verilog__main.i_rx_phy.rst_64_2 Verilog__main.i_rx_phy.rst_64_1_39_) (= Verilog__main.i_rx_phy.fs_ce_64_2 Verilog__main.i_rx_phy.fs_ce_64_1_39_) (= Verilog__main.i_rx_phy.rxd_64_2 Verilog__main.i_rx_phy.rxd_64_1_39_) (= Verilog__main.rxd_64_2 Verilog__main.rxd_64_1_39_) (= Verilog__main.i_rx_phy.rxdp_64_2 Verilog__main.i_rx_phy.rxdp_64_1_39_) (= Verilog__main.rxdp_64_2 Verilog__main.rxdp_64_1_39_) (= Verilog__main.i_rx_phy.rxdn_64_2 Verilog__main.i_rx_phy.rxdn_64_1_39_) (= Verilog__main.rxdn_64_2 Verilog__main.rxdn_64_1_39_) (= Verilog__main.DataIn_o_64_2 Verilog__main.DataIn_o_64_1_39_) (= Verilog__main.RxValid_o_64_2 Verilog__main.RxValid_o_64_1_39_) (= Verilog__main.RxActive_o_64_2 Verilog__main.RxActive_o_64_1_39_) (= Verilog__main.RxError_o_64_2 Verilog__main.RxError_o_64_1_39_) (= Verilog__main.i_rx_phy.RxEn_i_64_2 Verilog__main.i_rx_phy.RxEn_i_64_1_39_) (= Verilog__main.LineState_o_64_2 Verilog__main.LineState_o_64_1_39_) (= Verilog__main.i_tx_phy.sd_bs_o_64_2 Verilog__main.i_tx_phy.sd_bs_o_64_1_39_) (= Verilog__main.i_tx_phy.sd_nrzi_o_64_2 Verilog__main.i_tx_phy.sd_nrzi_o_64_1_39_) (= Verilog__main.i_tx_phy.append_eop_64_2 Verilog__main.i_tx_phy.append_eop_64_1_39_) (= Verilog__main.i_tx_phy.append_eop_sync1_64_2 Verilog__main.i_tx_phy.append_eop_sync1_64_1_39_) (= Verilog__main.i_tx_phy.append_eop_sync2_64_2 Verilog__main.i_tx_phy.append_eop_sync2_64_1_39_) (= Verilog__main.i_tx_phy.txoe_r1_64_2 Verilog__main.i_tx_phy.txoe_r1_64_1_39_) (= Verilog__main.i_tx_phy.txoe_r2_64_2 Verilog__main.i_tx_phy.txoe_r2_64_1_39_) (= Verilog__main.i_tx_phy.state_64_2 Verilog__main.i_tx_phy.state_64_1_39_) (= Verilog__main.i_tx_phy.tx_ready_64_2 Verilog__main.i_tx_phy.tx_ready_64_1_39_) (= Verilog__main.i_tx_phy.tx_ready_d_64_2 Verilog__main.i_tx_phy.tx_ready_d_64_1_39_) (= Verilog__main.i_tx_phy.ld_sop_d_64_2 Verilog__main.i_tx_phy.ld_sop_d_64_1_39_) (= Verilog__main.i_tx_phy.ld_data_d_64_2 Verilog__main.i_tx_phy.ld_data_d_64_1_39_) (= Verilog__main.i_tx_phy.ld_eop_d_64_2 Verilog__main.i_tx_phy.ld_eop_d_64_1_39_) (= Verilog__main.i_tx_phy.tx_ip_64_2 Verilog__main.i_tx_phy.tx_ip_64_1_39_) (= Verilog__main.i_tx_phy.tx_ip_sync_64_2 Verilog__main.i_tx_phy.tx_ip_sync_64_1_39_) (= Verilog__main.i_tx_phy.bit_cnt_64_2 Verilog__main.i_tx_phy.bit_cnt_64_1_39_) (= Verilog__main.i_tx_phy.hold_reg_64_2 Verilog__main.i_tx_phy.hold_reg_64_1_39_) (= Verilog__main.i_tx_phy.sd_raw_o_64_2 Verilog__main.i_tx_phy.sd_raw_o_64_1_39_) (= Verilog__main.i_tx_phy.data_done_64_2 Verilog__main.i_tx_phy.data_done_64_1_39_) (= Verilog__main.i_tx_phy.ld_data_64_2 Verilog__main.i_tx_phy.ld_data_64_1_39_) (= Verilog__main.i_rx_phy.rxd_t1_64_2 Verilog__main.i_rx_phy.rxd_t1_64_1_39_) (= Verilog__main.i_rx_phy.rxd_s1_64_2 Verilog__main.i_rx_phy.rxd_s1_64_1_39_) (= Verilog__main.i_rx_phy.rxd_s_64_2 Verilog__main.i_rx_phy.rxd_s_64_1_39_) (= Verilog__main.i_rx_phy.rxdp_t1_64_2 Verilog__main.i_rx_phy.rxdp_t1_64_1_39_) (= Verilog__main.i_rx_phy.rxdn_t1_64_2 Verilog__main.i_rx_phy.rxdn_t1_64_1_39_) (= Verilog__main.i_rx_phy.synced_d_64_2 Verilog__main.i_rx_phy.synced_d_64_1_39_) (= Verilog__main.i_rx_phy.bit_cnt_64_2 Verilog__main.i_rx_phy.bit_cnt_64_1_39_) (= Verilog__main.i_rx_phy.rx_valid1_64_2 Verilog__main.i_rx_phy.rx_valid1_64_1_39_) (= Verilog__main.i_rx_phy.shift_en_64_2 Verilog__main.i_rx_phy.shift_en_64_1_39_) (= Verilog__main.i_rx_phy.sd_r_64_2 Verilog__main.i_rx_phy.sd_r_64_1_39_) (= Verilog__main.i_rx_phy.sd_nrzi_64_2 Verilog__main.i_rx_phy.sd_nrzi_64_1_39_) (= Verilog__main.i_rx_phy.dpll_state_64_2 Verilog__main.i_rx_phy.dpll_state_64_1_39_) (= Verilog__main.i_rx_phy.fs_ce_d_64_2 Verilog__main.i_rx_phy.fs_ce_d_64_1_39_) (= Verilog__main.i_rx_phy.fs_ce_r1_64_2 Verilog__main.i_rx_phy.fs_ce_r1_64_1_39_) (= Verilog__main.i_rx_phy.fs_ce_r2_64_2 Verilog__main.i_rx_phy.fs_ce_r2_64_1_39_) (= Verilog__main.i_rx_phy.fs_ce_r3_64_2 Verilog__main.i_rx_phy.fs_ce_r3_64_1_39_) (= Verilog__main.i_rx_phy.fs_state_64_2 Verilog__main.i_rx_phy.fs_state_64_1_39_) (= Verilog__main.i_rx_phy.rx_valid_r_64_2 Verilog__main.i_rx_phy.rx_valid_r_64_1_39_) (= Verilog__main.rst_cnt_64_2 Verilog__main.rst_cnt_64_1_39_))))) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ))
;; produced by cvc4_14.drv ;;
(set-logic AUFBVDTNIRA)
(set-info :source |VC generated by SPARK 2014|)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category industrial)
(set-info :status unsat)
;;; generated by SMT-LIB2 driver
; EXPECT: unsat
(set-logic AUFLIA)
(set-info :source | Burns mutual exclusion protocol. This is a benchmark of the haRVey theorem prover. It was translated to SMT-LIB by Leonardo de Moura |)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "industrial")
(set-info :status unsat)
(declare-fun s_0 (Int) Bool)
; EXPECT: unsat
(set-logic AUFLIA)
(set-info :source | Burns mutual exclusion protocol. This is a benchmark of the haRVey theorem prover. It was translated to SMT-LIB by Leonardo de Moura |)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "industrial")
(set-info :status unsat)
(declare-fun s_0 (Int) Bool)
Clark Barrett
|)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "industrial")
(set-info :status unsat)
(declare-fun def () Real)
; COMMAND-LINE: --fmf-fun-rlv --no-check-models
; EXPECT: sat
-(set-info :smt-lib-version 2.5)
+(set-info :smt-lib-version 2.6)
(set-option :produce-models true)
(set-logic ALL)
-(declare-datatypes () ((a0(c0$0)(c0$1(c0$1$0 String)(c0$1$1 Int))(c0$2(c0$2$0 Bool)(c0$2$1 Int)(c0$2$2 String)))
- (a1(c1$0)(c1$1)(c1$2))
- (a2(c2$0(c2$0$0 Int)(c2$0$1 a0)(c2$0$2 String)(c2$0$3 a3)(c2$0$4 String)(c2$0$5 Bool)))
- (a3(c3$0(c3$0$0 a7)(c3$0$1 a1)(c3$0$2 a5)(c3$0$3 a6)(c3$0$4 Int)(c3$0$5 Bool)(c3$0$6 Bool))(c3$1(c3$1$0 String)))
- (a4(c4$0(c4$0$0 String)(c4$0$1 a2)(c4$0$2 String))(c4$1(c4$1$0 a0)(c4$1$1 a4)(c4$1$2 a4)(c4$1$3 a7))(c4$2))
- (a5(c5$0(c5$0$0 a2))(c5$1)(c5$2)(c5$3(c5$3$0 a0))(c5$4)(c5$5(c5$5$0 a4)(c5$5$1 Int))(c5$6))
- (a6(c6$0(c6$0$0 a7)(c6$0$1 a7)(c6$0$2 String))(c6$1)(c6$2)(c6$3)(c6$4)(c6$5)(c6$6))
- (a7(c7$0(c7$0$0 a2)(c7$0$1 Int))(c7$1(c7$1$0 a4)(c7$1$1 Int)(c7$1$2 Bool)))))
+(declare-datatypes ((a0 0)(a1 0)(a2 0)(a3 0)(a4 0)(a5 0)(a6 0)(a7 0)) (((c0$0) (c0$1 (c0$1$0 String) (c0$1$1 Int)) (c0$2 (c0$2$0 Bool) (c0$2$1 Int) (c0$2$2 String)))((c1$0) (c1$1) (c1$2))((c2$0 (c2$0$0 Int) (c2$0$1 a0) (c2$0$2 String) (c2$0$3 a3) (c2$0$4 String) (c2$0$5 Bool)))((c3$0 (c3$0$0 a7) (c3$0$1 a1) (c3$0$2 a5) (c3$0$3 a6) (c3$0$4 Int) (c3$0$5 Bool) (c3$0$6 Bool)) (c3$1 (c3$1$0 String)))((c4$0 (c4$0$0 String) (c4$0$1 a2) (c4$0$2 String)) (c4$1 (c4$1$0 a0) (c4$1$1 a4) (c4$1$2 a4) (c4$1$3 a7)) (c4$2))((c5$0 (c5$0$0 a2)) (c5$1) (c5$2) (c5$3 (c5$3$0 a0)) (c5$4) (c5$5 (c5$5$0 a4) (c5$5$1 Int)) (c5$6))((c6$0 (c6$0$0 a7) (c6$0$1 a7) (c6$0$2 String)) (c6$1) (c6$2) (c6$3) (c6$4) (c6$5) (c6$6))((c7$0 (c7$0$0 a2) (c7$0$1 Int)) (c7$1 (c7$1$0 a4) (c7$1$1 Int) (c7$1$2 Bool)))))
(define-funs-rec ((f3((v4 Bool))a7)
(f2()a6)
(f1((v1 a3)(v2 a1)(v3 Bool))String)
; COMMAND-LINE: --fmf-fun-rlv --no-check-models
; EXPECT: sat
-(set-info :smt-lib-version 2.5)
+(set-info :smt-lib-version 2.6)
(set-option :produce-models true)
(set-logic ALL)
-(declare-datatypes () ((a0(c0$0(c0$0$0 a4)(c0$0$1 Bool)(c0$0$2 a4)(c0$0$3 Int)(c0$0$4 a5)(c0$0$5 a7)(c0$0$6 a7)))(a1(c1$0(c1$0$0 Bool)(c1$0$1 Bool)(c1$0$2 Int))(c1$1)(c1$2(c1$2$0 a3)(c1$2$1 a5)(c1$2$2 a1)(c1$2$3 a7))(c1$3)(c1$4)(c1$5)(c1$6)(c1$7)(c1$8)(c1$9(c1$9$0 a4))(c1$a))(a2(c2$0(c2$0$0 String)(c2$0$1 a4)(c2$0$2 a0)(c2$0$3 Bool)(c2$0$4 a5)(c2$0$5 a4))(c2$1)(c2$2)(c2$3)(c2$4)(c2$5))(a3(c3$0)(c3$1)(c3$2)(c3$3)(c3$4(c3$4$0 a6))(c3$5)(c3$6)(c3$7))(a4(c4$0)(c4$1(c4$1$0 a3))(c4$2(c4$2$0 a5))(c4$3)(c4$4)(c4$5(c4$5$0 String)(c4$5$1 a4))(c4$6)(c4$7)(c4$8)(c4$9(c4$9$0 String))(c4$a)(c4$b))(a5(c5$0)(c5$1(c5$1$0 a7)(c5$1$1 a0)(c5$1$2 Bool)(c5$1$3 a1)(c5$1$4 a3)(c5$1$5 a7)(c5$1$6 Int)(c5$1$7 Bool))(c5$2)(c5$3)(c5$4)(c5$5)(c5$6)(c5$7))(a6(c6$0(c6$0$0 Bool))(c6$1)(c6$2(c6$2$0 Bool)(c6$2$1 a3)(c6$2$2 Int)(c6$2$3 a3)(c6$2$4 a6)(c6$2$5 a7)(c6$2$6 a0)(c6$2$7 a6)))(a7(c7$0)(c7$1)(c7$2(c7$2$0 a6))(c7$3)(c7$4)(c7$5(c7$5$0 a2)(c7$5$1 a2)(c7$5$2 Int)(c7$5$3 a6))(c7$6)(c7$7))))
+(declare-datatypes ((a0 0)(a1 0)(a2 0)(a3 0)(a4 0)(a5 0)(a6 0)(a7 0)) (((c0$0 (c0$0$0 a4) (c0$0$1 Bool) (c0$0$2 a4) (c0$0$3 Int) (c0$0$4 a5) (c0$0$5 a7) (c0$0$6 a7)))((c1$0 (c1$0$0 Bool) (c1$0$1 Bool) (c1$0$2 Int)) (c1$1) (c1$2 (c1$2$0 a3) (c1$2$1 a5) (c1$2$2 a1) (c1$2$3 a7)) (c1$3) (c1$4) (c1$5) (c1$6) (c1$7) (c1$8) (c1$9 (c1$9$0 a4)) (c1$a))((c2$0 (c2$0$0 String) (c2$0$1 a4) (c2$0$2 a0) (c2$0$3 Bool) (c2$0$4 a5) (c2$0$5 a4)) (c2$1) (c2$2) (c2$3) (c2$4) (c2$5))((c3$0) (c3$1) (c3$2) (c3$3) (c3$4 (c3$4$0 a6)) (c3$5) (c3$6) (c3$7))((c4$0) (c4$1 (c4$1$0 a3)) (c4$2 (c4$2$0 a5)) (c4$3) (c4$4) (c4$5 (c4$5$0 String) (c4$5$1 a4)) (c4$6) (c4$7) (c4$8) (c4$9 (c4$9$0 String)) (c4$a) (c4$b))((c5$0) (c5$1 (c5$1$0 a7) (c5$1$1 a0) (c5$1$2 Bool) (c5$1$3 a1) (c5$1$4 a3) (c5$1$5 a7) (c5$1$6 Int) (c5$1$7 Bool)) (c5$2) (c5$3) (c5$4) (c5$5) (c5$6) (c5$7))((c6$0 (c6$0$0 Bool)) (c6$1) (c6$2 (c6$2$0 Bool) (c6$2$1 a3) (c6$2$2 Int) (c6$2$3 a3) (c6$2$4 a6) (c6$2$5 a7) (c6$2$6 a0) (c6$2$7 a6)))((c7$0) (c7$1) (c7$2 (c7$2$0 a6)) (c7$3) (c7$4) (c7$5 (c7$5$0 a2) (c7$5$1 a2) (c7$5$2 Int) (c7$5$3 a6)) (c7$6) (c7$7))))
(define-funs-rec ( (f9((v38 Int)(v39 a2)(v3a a5)(v3b a0)(v3c a7)(v3d a3))Bool)
(f8((v33 String)(v34 Int)(v35 a1)(v36 a7)(v37 a4))a6)
(f7((v29 a1)(v2a Bool)(v2b a3)(v2c String)(v2d Bool)(v2e String)(v2f a7)(v30 a5)(v31 a2)(v32 a2))Int)
; COMMAND-LINE: --fmf-fun --no-check-models\r
; EXPECT: sat\r
\r
-(set-info :smt-lib-version 2.5)\r
+(set-info :smt-lib-version 2.6)\r
(set-option :produce-models true)\r
(set-logic ALL)\r
(define-funs-rec (\r
(set-logic AUFBVDTNIRA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :status unsat)
(declare-sort us_private 0)
(declare-fun to_rep1 (integer) Int)
-(declare-datatypes ()
-((us_split_fields
- (mk___split_fields (rec__unit1__t1__c1 integer)(rec__ext__ us_private)))))
+(declare-datatypes ((us_split_fields 0)) (((mk___split_fields (rec__unit1__t1__c1 integer) (rec__ext__ us_private)))))
+(declare-datatypes ((us_split_fields__ref 0)) (((mk___split_fields__ref (us_split_fields__content us_split_fields)))))
-(declare-datatypes ()
-((us_split_fields__ref
- (mk___split_fields__ref (us_split_fields__content us_split_fields)))))
(define-fun us_split_fields__ref___projection ((a us_split_fields__ref)) us_split_fields
(us_split_fields__content a))
-(declare-datatypes ()
-((us_rep (mk___rep (us_split_fields1 us_split_fields)(attr__tag Int)))))
+(declare-datatypes ((us_rep 0)) (((mk___rep (us_split_fields1 us_split_fields) (attr__tag Int)))))
(define-fun us_rep___projection ((a us_rep)) us_split_fields (us_split_fields1
a))
(= (to_rep1 (rec__unit1__t1__c1 (us_split_fields1 x))) 0))) :pattern (
(is_zero x)) )))
-(declare-datatypes ()
-((us_split_fields2
- (mk___split_fields1
- (rec__unit2__t2__c2 integer)(rec__unit1__t1__c11 integer)(rec__ext__1 us_private)))))
+(declare-datatypes ((us_split_fields2 0)) (((mk___split_fields1 (rec__unit2__t2__c2 integer) (rec__unit1__t1__c11 integer) (rec__ext__1 us_private)))))
+(declare-datatypes ((us_split_fields__ref1 0)) (((mk___split_fields__ref1 (us_split_fields__content1 us_split_fields2)))))
-(declare-datatypes ()
-((us_split_fields__ref1
- (mk___split_fields__ref1 (us_split_fields__content1 us_split_fields2)))))
(define-fun us_split_fields__ref_2__projection ((a us_split_fields__ref1)) us_split_fields2
(us_split_fields__content1 a))
-(declare-datatypes ()
-((us_rep1 (mk___rep1 (us_split_fields3 us_split_fields2)(attr__tag1 Int)))))
+(declare-datatypes ((us_rep1 0)) (((mk___rep1 (us_split_fields3 us_split_fields2) (attr__tag1 Int)))))
(define-fun us_rep_3__projection ((a us_rep1)) us_split_fields2 (us_split_fields3
a))
Simplify front end test suite.
This benchmark was translated by Michal Moskal.
|)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "industrial")
(set-info :status unsat)
(declare-fun after_133.8_133.8 () Int)
(set-info :source |
Tokeneer case study <http://www.adacore.com/home/products/gnatpro/tokeneer/>
|)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "industrial")
(set-info :status unsat)
(declare-fun field.datat.length () Int)
Simplify front end test suite.
This benchmark was translated by Michal Moskal.
|)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "industrial")
(set-info :status unsat)
(declare-fun EC_134.22_134.22 () Int)
; EXPECT: unsat
(set-logic AUFLIRA)
(set-info :source |http://proval.lri.fr/why-benchmarks |)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "industrial")
(set-info :status unsat)
(declare-sort Unit 0)
(set-logic UFLIA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "industrial")
(set-info :status unsat)
(declare-fun boolIff (Int Int) Int)
(set-logic AUFLIA)
(set-info :source | An Optimal Algorithm for Mutual Exclusion in Computer Networks. Glenn Ricart and Ashok K. Agrawala. Communications of the ACM Vol.: 24 Number: 1. This is a benchmark of the haRVey theorem prover. It was translated to SMT-LIB by Leonardo de Moura |)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "industrial")
(set-info :status unsat)
(declare-fun p () Int)
; COMMAND-LINE: --full-saturate-quant
(set-logic AUFLIA)
(set-info :source | Assertion verification of simple set manipulation programs. |)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status unsat)
(declare-sort Set 0)
(set-logic AUFLIA)
(set-info :source | Set theory. |)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status unsat)
(declare-sort Set 0)
(set-logic AUFLIRA)
(set-info :source |http://proval.lri.fr/why-benchmarks |)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "industrial")
(set-info :status unsat)
(declare-sort Unit 0)
(set-logic AUFLIRA)
(set-info :source |http://proval.lri.fr/why-benchmarks |)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "industrial")
(set-info :status unsat)
(declare-sort Unit 0)
(set-logic AUFLIRA)
(set-info :source |http://proval.lri.fr/why-benchmarks |)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "industrial")
(set-info :status unsat)
(declare-sort Unit 0)
(set-info :source | Example extracted from Peter Baumgartner's talk at CADE-21: Logical Engineering with Instance-Based Methods.
It was translated to SMT-LIB by Leonardo de Moura |)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status unsat)
(declare-fun symmetric ((Array Int (Array Int Real)) Int) Bool)
; EXPECT: unsat
(set-logic UFNIA)
(set-info :source |Benchmarks from the paper: "Extending Sledgehammer with SMT Solvers" by Jasmin Blanchette, Sascha Bohme, and Lawrence C. Paulson, CADE 2011. Translated to SMT2 by Andrew Reynolds and Morgan Deters.|)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "industrial")
(set-info :status unsat)
(declare-sort S1 0)
;
; sat
(set-info :source |fuzzsmt|)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "random")
(set-info :status sat)
(set-logic QF_UFLIAFS)
; symptom: unsat instead of sat
; issue/fix: buggy rewriter for setminus
(set-info :source |fuzzsmt|)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "random")
(set-info :status sat)
(set-logic QF_UFLIAFS)
; stop.
;
(set-info :source |fuzzsmt|)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "random")
(set-info :status sat)
(set-logic QF_UFLIAFS)
(set-info :source |fuzzsmt|)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "random")
(set-info :status sat)
(set-logic QF_UFLIAFS)
-(set-info :smt-lib-version 2.5)
(set-logic UFDTSLIA)
(set-info :status sat)
-(declare-datatypes () ((T (TC (TCb String)))))
+(declare-datatype T ((TC (TCb String))))
(declare-fun root5 () String)
(declare-fun root6 () T)
(assert (and
-(str.in.re root5 ((_ re.loop 4 4) (re.range "0" "9")) )
-(str.in.re (TCb root6) ((_ re.loop 4 4) (re.range "0" "9")) )
+(str.in_re root5 ((_ re.loop 4 4) (re.range "0" "9")) )
+(str.in_re (TCb root6) ((_ re.loop 4 4) (re.range "0" "9")) )
) )
(check-sat)
-(set-info :smt-lib-version 2.5)
(set-logic ALL)
(set-option :strings-exp true)
(set-info :status sat)
-(declare-datatypes () ((Val
- (Str (str String))
- (Num (num Int)))))
+(declare-datatype Val
+ ((Str (str String))
+ (Num (num Int))))
(declare-const var0 Val)
-(assert (=> (is-Str var0) (distinct (str.to.int (str var0)) (- 1))))
+(assert (=> (is-Str var0) (distinct (str.to_int (str var0)) (- 1))))
(check-sat)
-(set-info :smt-lib-version 2.5)
+(set-info :smt-lib-version 2.6)
(set-logic QF_S)
(set-info :status sat)
(set-option :strings-exp true)
(declare-const s String)
-(assert (str.in.re s (re.* (re.range "\x00" "\xFF"))))
-(assert (str.in.re s (re.range "\x00" "\xFF")))
+(assert (str.in_re s (re.* (re.range "\u{0}" "\u{ff}"))))
+(assert (str.in_re s (re.range "\u{0}" "\u{ff}")))
(check-sat)
-(set-info :smt-lib-version 2.5)
+(set-info :smt-lib-version 2.6)
(set-logic ALL_SUPPORTED)
(set-option :strings-exp true)
(set-info :status sat)
(and
(and
(and
- (not (= (ite (= (str.at (str.substr c 1 (- (str.len (str.substr c 0 (- (str.len c) 1))) 1)) (- (str.len (str.substr (str.substr c 1 (- (str.len (str.replace a b "")) 1)) 0 (- (str.len (str.substr (str.replace a b "") 1 (- (str.len (str.replace a b "")) 1))) 1))) 1)) "\t") 1 0) 0))
+ (not (= (ite (= (str.at (str.substr c 1 (- (str.len (str.substr c 0 (- (str.len c) 1))) 1)) (- (str.len (str.substr (str.substr c 1 (- (str.len (str.replace a b "")) 1)) 0 (- (str.len (str.substr (str.replace a b "") 1 (- (str.len (str.replace a b "")) 1))) 1))) 1)) "\u{9}") 1 0) 0))
(= (ite (= (str.at (str.substr (str.substr c 1 (- (str.len (str.replace a b "")) 1)) 0 (- (str.len (str.substr (str.replace a b "") 1 (- (str.len (str.replace a b "")) 1))) 1)) 0) "B") 1 0) 0)
)
(= (ite (= (str.at (str.substr (str.substr c 1 (- (str.len c) 1)) 0 (- (str.len (str.substr (str.replace a b "") 1 (- (str.len (str.replace a b "")) 1))) 1)) 0) " ") 1 0) 0)
- (not (= (ite (= (str.at (str.substr (str.replace a b "") 1 (- (str.len c) 1)) (- (str.len (str.substr c 1 (- (str.len c) 1))) 1)) "\v") 1 0) 0))
+ (not (= (ite (= (str.at (str.substr (str.replace a b "") 1 (- (str.len c) 1)) (- (str.len (str.substr c 1 (- (str.len c) 1))) 1)) "\u{b}") 1 0) 0))
)
(= (ite (= (str.at (str.substr c 1 (- (str.len (str.replace a b "")) 1)) 0) " ") 1 0) 0)
)
; EXPECT: sat\r
; EXPECT: sat\r
; EXPECT: sat\r
-(set-info :smt-lib-version 2.5)\r
+(set-info :smt-lib-version 2.6)\r
(set-option :produce-models true)\r
(set-logic ALL)\r
-(declare-datatypes () ((a0(c0$0)(c0$1)(c0$2)(c0$3(c0$3$0 a1)(c0$3$1 Int)(c0$3$2 String)(c0$3$3 Int))(c0$4(c0$4$0 Int))(c0$5))(a1(c1$0(c1$0$0 a0)(c1$0$1 a0)(c1$0$2 String)(c1$0$3 Int))(c1$1(c1$1$0 Int))(c1$2)(c1$3(c1$3$0 Int))(c1$4)(c1$5))(a2(c2$0(c2$0$0 Int)(c2$0$1 a0))(c2$1(c2$1$0 String)(c2$1$1 a0)(c2$1$2 a1)))))\r
+(declare-datatypes ((a0 0)(a1 0)(a2 0)) (((c0$0) (c0$1) (c0$2) (c0$3 (c0$3$0 a1) (c0$3$1 Int) (c0$3$2 String) (c0$3$3 Int)) (c0$4 (c0$4$0 Int)) (c0$5))((c1$0 (c1$0$0 a0) (c1$0$1 a0) (c1$0$2 String) (c1$0$3 Int)) (c1$1 (c1$1$0 Int)) (c1$2) (c1$3 (c1$3$0 Int)) (c1$4) (c1$5))((c2$0 (c2$0$0 Int) (c2$0$1 a0)) (c2$1 (c2$1$0 String) (c2$1$1 a0) (c2$1$2 a1)))))\r
(push 1)\r
(pop 1)\r
(push 1)\r
-(set-info :smt-lib-version 2.5)\r
-(set-logic SLIA)\r
-(set-info :status sat)\r
-(set-option :strings-exp true)\r
-(define-fun stringEval ((?s String)) Bool (str.in.re ?s \r
-(re.union \r
-(str.to.re "H")\r
-(re.++ ((_ re.loop 2 2) (str.to.re "{") ) ((_ re.loop 2 4) (re.union re.nostr (re.range "\1d" "]") (re.range "\ e" "^") ) ) ) ) ) )\r
-(declare-fun s0() String)\r
-(declare-fun s1() String)\r
-(declare-fun s2() String)\r
-(assert (and true (stringEval s0) (stringEval s1) (distinct s0 s1) (stringEval s2) (distinct s0 s2) (distinct s1 s2) ) )\r
-(check-sat)\r
+(set-info :smt-lib-version 2.6)
+(set-logic SLIA)
+(set-info :status sat)
+(set-option :strings-exp true)
+(define-fun stringEval ((?s String)) Bool (str.in_re ?s
+(re.union
+(str.to_re "H")
+(re.++ ((_ re.loop 2 2) (str.to_re "{") ) ((_ re.loop 2 4) (re.union re.none (re.range "\u{1d}" "]") (re.range "\u{e}" "^") ) ) ) ) ) )
+(declare-fun s0() String)
+(declare-fun s1() String)
+(declare-fun s2() String)
+(assert (and true (stringEval s0) (stringEval s1) (distinct s0 s1) (stringEval s2) (distinct s0 s2) (distinct s1 s2) ) )
+(check-sat)
(set-logic QF_AUFBVLIA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status unsat)
(declare-fun v1 () (_ BitVec 1))
; EXPECT: sat
(set-logic QF_UFLIA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(declare-fun _base () Int)
(declare-fun _n () Int)
(declare-fun ___z3z___ (Int) Bool)
(set-logic QF_UFLIA)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :status sat)
(declare-fun _base () Int)
(declare-fun _n () Int)
This benchmark was automatically translated into SMT-LIB format by Albert Oliveras.
|)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "industrial")
(set-info :status sat)
(declare-fun t.l () Int)
Translated into SMT-LIB format by Albert Oliveras.
|)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "random")
(set-info :status sat)
(declare-fun x10 () Int)
optimization problem opt1217 from the MIPLIB (http://miplib.zib.de/)
by Enric Rodriguez-Carbonell (erodri@lsi.upc.edu)
|)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "industrial")
(set-info :status unsat)
(declare-fun tmp766 () Real)
; EXPECT: sat
;(set-option :produce-unsat-cores true)
(set-option :print-success false)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
;(set-option :produce-models true)
(set-logic ALL_SUPPORTED)
; done setting options
VCC and HAVOC benchmarks. Contributed by Nikolaj Bjorner, Leonardo de Moura,\r
Michal Moskal, and Shaz Qadeer.\r
|)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "industrial")
(set-info :status unsat)
(declare-fun x (Int Int) Int)
(set-logic QF_UFLIA)
(set-info :source | MathSat group |)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status sat)
(declare-fun hash_1 (Int) Int)
(set-logic QF_UFLIA)
(set-info :source | MathSat group |)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status sat)
(declare-fun hash_1 (Int) Int)
(set-logic QF_UFLIA)
(set-info :source | MathSat group |)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status sat)
(declare-fun hash_1 (Int) Int)
(set-logic QF_UFLIA)
(set-info :source | MathSat group |)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "crafted")
(set-info :status sat)
(declare-fun hash_1 (Int) Int)
(set-logic QF_UFLIA)
(set-info :source | Simplify Theorem Prover Benchmark Suite |)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "industrial")
(set-info :status sat)
(declare-fun true_term () Int)
(set-logic QF_UFLIA)
(set-info :source | Simplify Theorem Prover Benchmark Suite |)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "industrial")
(set-info :status sat)
(declare-fun true_term () Int)
|)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "industrial")
(set-info :status unsat)
(declare-fun skoX () Real)
This benchmark was automatically translated into SMT-LIB format from
CVC format using CVC Lite
|)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "industrial")
(set-info :status unsat)
(declare-fun BOOOB_46_init_null_val () Int)
This benchmark was automatically translated into SMT-LIB format from
CVC format using CVC Lite
|)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "industrial")
(set-info :status unsat)
(declare-fun Br1 () Int)
(set-logic AUFLIA)
(set-info :source |piVC|)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "industrial")
(set-info :status unsat)
(declare-fun V_26 () Int)
Boogie/Spec# benchmarks.
This benchmark was translated by Michal Moskal.
|)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "industrial")
(set-info :status unsat)
(declare-fun boolIff (Int Int) Int)
(set-logic AUFLIA)
(set-info :source | Simplify Theorem Prover Benchmark Suite |)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "industrial")
(set-info :status unsat)
(declare-fun true_term () Int)
(set-logic AUFLIA)
(set-info :source | Simplify Theorem Prover Benchmark Suite |)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "industrial")
(set-info :status unsat)
(declare-fun true_term () Int)
(set-logic AUFLIA)
(set-info :source | Simplify Theorem Prover Benchmark Suite |)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "industrial")
(set-info :status unsat)
(declare-fun true_term () Int)
Simplify front end test suite.
This benchmark was translated by Michal Moskal.
|)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "industrial")
(set-info :status unsat)
(declare-fun L_102.5 () Int)
(set-logic AUFLIA)
(set-info :source | Simplify Theorem Prover Benchmark Suite |)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "industrial")
(set-info :status unsat)
(declare-fun true_term () Int)
(set-logic QF_UFLIA)
(set-info :source | Simplify Theorem Prover Benchmark Suite |)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "industrial")
(set-info :status sat)
(declare-fun true_term () Int)
-; COMMAND-LINE: --lang=smt2.0
; EXPECT: sat
(set-logic ALL_SUPPORTED)
(set-info :status sat)
+(set-info :smt-lib-version 2.6)
(set-option :strings-exp true)
(declare-fun value () String)
(declare-fun name () String)
(assert (not (not (= (ite (> (str.indexof value ":" 0) 0) 1 0) 0))))
(assert (not (= (ite (not (= (str.len value) 0)) 1 0) 0)))
(assert (not (not (= (ite (str.contains value "'") 1 0) 0))))
-(assert (not (not (= (ite (str.contains value "\"") 1 0) 0))))
+(assert (not (not (= (ite (str.contains value "\\""") 1 0) 0))))
(assert (not (not (= (ite (str.contains value ">") 1 0) 0))))
(assert (not (not (= (ite (str.contains value "<") 1 0) 0))))
(assert (not (not (= (ite (str.contains value "&") 1 0) 0))))
(assert (not (not (= (ite (str.contains name "'") 1 0) 0))))
-(assert (not (not (= (ite (str.contains name "\"") 1 0) 0))))
+(assert (not (not (= (ite (str.contains name "\\""") 1 0) 0))))
(assert (not (not (= (ite (str.contains name ">") 1 0) 0))))
(assert (not (not (= (ite (str.contains name "<") 1 0) 0))))
(assert (not (not (= (ite (str.contains name "&") 1 0) 0))))
; COMMAND-LINE: --strings-exp --re-elim
; EXPECT: sat
-(set-info :smt-lib-version 2.5)
+(set-info :smt-lib-version 2.6)
(set-option :produce-models true)
(set-logic UFDTSLIA)
-(declare-datatypes () (
- (StringRotation (StringRotation$C_StringRotation (StringRotation$C_StringRotation$sr String)))
- (StringRotation2 (StringRotation2$C_StringRotation2 (StringRotation2$C_StringRotation2$sr1 StringRotation) (StringRotation2$C_StringRotation2$sr2 StringRotation)))
-) )
+(declare-datatypes ((StringRotation 0)(StringRotation2 0)) (((StringRotation$C_StringRotation (StringRotation$C_StringRotation$sr String)))((StringRotation2$C_StringRotation2 (StringRotation2$C_StringRotation2$sr1 StringRotation) (StringRotation2$C_StringRotation2$sr2 StringRotation)))))
(define-fun f1005$isValid_string((x$$1008 String)) Bool true)
(define-fun f1035$isValid_StringRotation((x$$1038 StringRotation)) Bool (and (f1005$isValid_string (StringRotation$C_StringRotation$sr x$$1038)) (or (or (or (= (StringRotation$C_StringRotation$sr x$$1038) "0 deg") (= (StringRotation$C_StringRotation$sr x$$1038) "90 deg")) (= (StringRotation$C_StringRotation$sr x$$1038) "180 deg")) (= (StringRotation$C_StringRotation$sr x$$1038) "270 deg"))))
(declare-fun $OutSR$1356$3$1$() StringRotation2)
(assert (f1121$isValid_StringRotation2 $OutSR$1356$3$1$))
-(assert (and (is-StringRotation2$C_StringRotation2 $OutSR$1356$3$1$) (and (and
-(is-StringRotation$C_StringRotation (StringRotation2$C_StringRotation2$sr1 $OutSR$1356$3$1$)) (or
-(str.in.re
-(StringRotation$C_StringRotation$sr (StringRotation2$C_StringRotation2$sr1 $OutSR$1356$3$1$))
-(re.++ (re.union (re.range "u" "~") (re.range " " "t") ) (re.union (re.range "K" "~") (re.range " " "J") ) (re.union (re.range "L" "~") (re.range " " "K") ) (re.union (re.range "y" "~") (re.range " " "x") ) (re.union (re.range "{" "~") (re.range " " "z") ) )
-)
-(or
-(str.in.re (StringRotation$C_StringRotation$sr (StringRotation2$C_StringRotation2$sr1 $OutSR$1356$3$1$))
-(re.++ (re.union (re.range "s" "~") (re.range " " "r") ) (re.union (re.range "{" "~") (re.range " " "z") ) (re.union (re.range "u" "~") (re.range " " "t") ) ) )
+(assert (let ((_let_1 (re.* (re.union (re.range "\u{0}" "\u{9}") (re.range "\u{b}" "\u{c}") (re.range "\u{e}" "\u{7f}"))))) (let ((_let_2 (StringRotation2$C_StringRotation2$sr2 $OutSR$1356$3$1$))) (let ((_let_3 (StringRotation$C_StringRotation$sr _let_2))) (let ((_let_4 (re.union (re.range "n" "~") (re.range " " "m")))) (let ((_let_5 (re.union (re.range "u" "~") (re.range " " "t")))) (let ((_let_6 (re.union (re.range "<" "~") (re.range " " ";")))) (let ((_let_7 (StringRotation2$C_StringRotation2$sr1 $OutSR$1356$3$1$))) (let ((_let_8 (StringRotation$C_StringRotation$sr _let_7))) (let ((_let_9 (re.union (re.range "s" "~") (re.range " " "r")))) (let ((_let_10 (re.union (re.range "{" "~") (re.range " " "z")))) (and ((_ is StringRotation2$C_StringRotation2) $OutSR$1356$3$1$) (and (and ((_ is StringRotation$C_StringRotation) _let_7) (or (str.in_re _let_8 (re.++ _let_5 (re.union (re.range "K" "~") (re.range " " "J")) (re.union (re.range "L" "~") (re.range " " "K")) (re.union (re.range "y" "~") (re.range " " "x")) _let_10)) (or (str.in_re _let_8 (re.++ _let_9 _let_10 _let_5)) (or (str.in_re _let_8 _let_6) (or (str.in_re _let_8 (re.++ (re.union (re.range "&" "~") (re.range " " "%")) (re.range " " "~"))) (or (str.in_re _let_8 (re.++ (re.union (re.range "`" "~") (re.range " " "_")) _let_9 (re.union (re.range "1" "~") (re.range " " "0")) (re.union (re.range "_" "~") (re.range " " "^")))) (str.in_re _let_8 _let_1))))))) (and ((_ is StringRotation$C_StringRotation) _let_2) (or (str.in_re _let_3 (re.++ _let_6 (re.union (re.range "F" "~") (re.range " " "E")) _let_5 (re.union (re.range "P" "~") (re.range " " "O")))) (or (str.in_re _let_3 (re.union (re.range "E" "~") (re.range " " "D"))) (or (str.in_re _let_3 (re.++ (re.union (re.range "x" "~") (re.range " " "w")) _let_4 (re.union (re.range "d" "~") (re.range " " "c")) (re.union (re.range "]" "~") (re.range " " "\u{5c}")) (re.union (re.range "\u{5c}" "~") (re.range " " "[")))) (or (str.in_re _let_3 (re.++ (re.union (re.range ":" "~") (re.range " " "9")) (re.union (re.range "+" "~") (re.range " " "*")))) (or (str.in_re _let_3 (re.++ (re.union (re.range "." "~") (re.range " " "-")) _let_4 (re.union (re.range "|" "~") (re.range " " "{")))) (str.in_re _let_3 _let_1))))))))))))))))))))
-(or
-(str.in.re (StringRotation$C_StringRotation$sr (StringRotation2$C_StringRotation2$sr1 $OutSR$1356$3$1$)) (re.union (re.range "<" "~") (re.range " " ";") ) ) (or (str.in.re (StringRotation$C_StringRotation$sr (StringRotation2$C_StringRotation2$sr1 $OutSR$1356$3$1$)) (re.++ (re.union (re.range "&" "~") (re.range " " "%") ) (re.range " " "~") ) ) (or (str.in.re (StringRotation$C_StringRotation$sr (StringRotation2$C_StringRotation2$sr1 $OutSR$1356$3$1$)) (re.++ (re.union (re.range "`" "~") (re.range " " "_") ) (re.union (re.range "s" "~") (re.range " " "r") ) (re.union (re.range "1" "~") (re.range " " "0") ) (re.union (re.range "_" "~") (re.range " " "^") ) ) ) (str.in.re (StringRotation$C_StringRotation$sr (StringRotation2$C_StringRotation2$sr1 $OutSR$1356$3$1$)) (re.* (re.union (re.range "\x00" "\x09") (re.range "\x0B" "\x0C") (re.range "\x0E" "\x7F") ) ) ))))))) (and (is-StringRotation$C_StringRotation (StringRotation2$C_StringRotation2$sr2 $OutSR$1356$3$1$)) (or (str.in.re (StringRotation$C_StringRotation$sr (StringRotation2$C_StringRotation2$sr2 $OutSR$1356$3$1$)) (re.++ (re.union (re.range "<" "~") (re.range " " ";") ) (re.union (re.range "F" "~") (re.range " " "E") ) (re.union (re.range "u" "~") (re.range " " "t") ) (re.union (re.range "P" "~") (re.range " " "O") ) ) ) (or (str.in.re (StringRotation$C_StringRotation$sr (StringRotation2$C_StringRotation2$sr2 $OutSR$1356$3$1$)) (re.union (re.range "E" "~") (re.range " " "D") ) ) (or (str.in.re (StringRotation$C_StringRotation$sr (StringRotation2$C_StringRotation2$sr2 $OutSR$1356$3$1$)) (re.++ (re.union (re.range "x" "~") (re.range " " "w") ) (re.union (re.range "n" "~") (re.range " " "m") ) (re.union (re.range "d" "~") (re.range " " "c") ) (re.union (re.range "]" "~") (re.range " " "\\") ) (re.union (re.range "\\" "~") (re.range " " "[") ) ) ) (or (str.in.re (StringRotation$C_StringRotation$sr (StringRotation2$C_StringRotation2$sr2 $OutSR$1356$3$1$)) (re.++ (re.union (re.range ":" "~") (re.range " " "9") ) (re.union (re.range "+" "~") (re.range " " "*") ) ) ) (or (str.in.re (StringRotation$C_StringRotation$sr (StringRotation2$C_StringRotation2$sr2 $OutSR$1356$3$1$)) (re.++ (re.union (re.range "." "~") (re.range " " "-") ) (re.union (re.range "n" "~") (re.range " " "m") ) (re.union (re.range "|" "~") (re.range " " "{") ) ) ) (str.in.re (StringRotation$C_StringRotation$sr (StringRotation2$C_StringRotation2$sr2 $OutSR$1356$3$1$)) (re.* (re.union (re.range "\x00" "\x09") (re.range "\x0B" "\x0C") (re.range "\x0E" "\x7F") ) ) ))))))))))
(check-sat)
The logic is changed to QF_LIA.
The category is set as industrial.
The status (except 'large' cases) is assigned according to the 'outfile' on http://www.nec-labs.com/~fsoft/bench.html. |)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "industrial")
(set-info :status unsat)
(declare-fun i1430 () Int)
CVC format using CVC Lite
|)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "industrial")
(set-info :status unsat)
(declare-fun cvclZero () Int)
(set-info :source |\r
Spec# benchmarks. Contributed by Leonardo de Moura and Michal Moskal.\r
|)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "industrial")
(set-info :status unsat)
(declare-fun x (Int Int) Int)
|)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "industrial")
(set-info :status sat)
(declare-fun x_0 () Int)
; EXPECT: unsat
;(set-option :produce-unsat-cores true)
(set-option :print-success false)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
;(set-option :produce-models true)
(set-logic ALL_SUPPORTED)
; done setting options
optimization problem pp08a from the MIPLIB (http://miplib.zib.de/)
by Enric Rodriguez-Carbonell (erodri@lsi.upc.edu)
|)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "industrial")
(set-info :status unsat)
(declare-fun tmp75 () Real)
(set-logic QF_UFLIA)
(set-info :source | MathSat group |)
-(set-info :smt-lib-version 2.0)
+(set-info :smt-lib-version 2.6)
(set-info :category "industrial")
(set-info :status unsat)
(declare-fun fmt1 () Int)
projects / cvc5.git / commitdiff