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diff --git a/openpower/sv/overview.mdwn b/openpower/sv/overview.mdwn
index 232f1d40582e3d58c1251010a08505505d36131e..7acc0d3b79dfd8eaf6335d0aa5ad23e5161dba67 100644 (file)
--- a/openpower/sv/overview.mdwn
+++ b/openpower/sv/overview.mdwn
@@ -161,7 +161,7 @@ there is no separate Vector register file*: it's all the same instruction,
 on the standard register file, just with a loop.  Scalar happens to set
 that loop size to one.
 
-Also, it is important to note from the above that, strictly speaking, Simple-V is not really a Vectorisation scheme at all: it is more of a hardware instruction "Compression scheme", allowing as it does for what would normally require multiple sequential instructions to be replaced with one (and aome tags).  This is where the rule that Program Order must be preserved in Sub-OC execution derives from.  However in other ways, which will emerge below, the "tagging" concept presents an opportunity to include features definitely not common outside of Vector ISAs, and in that regard it's definitely a xlass of Vectorisation.
+Also, it is important to note from the above that, strictly speaking, Simple-V is not really a Vectorisation scheme at all: it is more of a hardware instruction "Compression scheme", allowing as it does for what would normally require multiple sequential instructions to be replaced with just one.  This is where the rule that Program Order must be preserved in Sub-OC execution derives from.  However in other ways, which will emerge below, the "tagging" concept presents an opportunity to include features definitely not common outside of Vector ISAs, and in that regard it's definitely a xlass of Vectorisation.
 
 ## Register "tagging"