power_insn: rename register operand class

diff --git a/src/openpower/decoder/power_insn.py b/src/openpower/decoder/power_insn.py
index fd7720248cbc9f5a386fe733329dd01ecc547f36..4e12ccd12a535803030f89af9ec81195f853763c 100644 (file)
--- a/src/openpower/decoder/power_insn.py
+++ b/src/openpower/decoder/power_insn.py
@@ -639,7 +639,7 @@ class NonZeroOperand(DynamicOperand):
             yield str(int(value) + 1)
 
 
-class RegisterOperand(DynamicOperand):
+class ExtendableOperand(DynamicOperand):
     def sv_spec_enter(self, value, span):
         return (value, span)
 
@@ -741,7 +741,7 @@ class RegisterOperand(DynamicOperand):
             yield f"{vector}{prefix}{int(value)}"
 
 
-class GPROperand(RegisterOperand):
+class GPROperand(ExtendableOperand):
     def assemble(self, value, insn, record):
         if isinstance(value, str):
             value = value.lower()
@@ -758,7 +758,7 @@ class GPROperand(RegisterOperand):
             verbosity=verbosity, indent=indent)
 
 
-class FPROperand(RegisterOperand):
+class FPROperand(ExtendableOperand):
     def assemble(self, value, insn, record):
         if isinstance(value, str):
             value = value.lower()
@@ -775,11 +775,11 @@ class FPROperand(RegisterOperand):
             verbosity=verbosity, indent=indent)
 
 
-class CR3Operand(RegisterOperand):
+class CR3Operand(ExtendableOperand):
     pass
 
 
-class CR5Operand(RegisterOperand):
+class CR5Operand(ExtendableOperand):
     def sv_spec_enter(self, value, span):
         value = _SelectableInt(value=(value.value >> 2), bits=3)
         return (value, span)