gowin: Use dfflegalize.

diff --git a/techlibs/gowin/cells_map.v b/techlibs/gowin/cells_map.v
index 5460274cacf4fabcb665e1862e8fc55472430071..851ef20b262f85ddf19a8252a14b0c9b2e63b115 100644 (file)
--- a/techlibs/gowin/cells_map.v
+++ b/techlibs/gowin/cells_map.v
@@ -3,228 +3,123 @@
 //value regardless. The parameter is ignored.
 
 // DFFN                         D Flip-Flop with Negative-Edge Clock
-module \$_DFF_N_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, output Q);
-       generate
-               if (_TECHMAP_WIREINIT_Q_ === 1'b1)
-                       DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(1'b0));
-               else
-                       DFFN _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C));
-       endgenerate
+module \$_DFF_N_ (input D, C, output Q);
+       DFFN _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C));
        wire _TECHMAP_REMOVEINIT_Q_ = 1;
 endmodule
 
 // DFF                  D Flip-Flop
-module \$_DFF_P_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, output Q);
-       generate
-               if (_TECHMAP_WIREINIT_Q_ === 1'b1)
-                       DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(1'b0));
-               else
-                       DFF _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C));
-       endgenerate
+module \$_DFF_P_ (input D, C, output Q);
+       DFF _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C));
        wire _TECHMAP_REMOVEINIT_Q_ = 1;
 endmodule
 
 // DFFE                         D Flip-Flop with Clock Enable
-module \$_DFFE_PP_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, E, output Q);
-       generate
-               if (_TECHMAP_WIREINIT_Q_ === 1'b1)
-                       DFFSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E), .SET(1'b0));
-               else
-                       DFFE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E));
-       endgenerate
-       wire _TECHMAP_REMOVEINIT_Q_ = 1;
-endmodule
-
-module \$_DFFE_PN_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, E, output Q);
-       generate
-               if (_TECHMAP_WIREINIT_Q_ === 1'b1)
-                       DFFSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(!E), .SET(1'b0));
-               else
-                       DFFE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(!E));
-       endgenerate
+module \$_DFFE_PP_ (input D, C, E, output Q);
+       DFFE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E));
        wire _TECHMAP_REMOVEINIT_Q_ = 1;
 endmodule
 
 // DFFNE                D Flip-Flop with Negative-Edge Clock and Clock Enable
-module \$_DFFE_NP_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, E, output Q);
-       generate
-               if (_TECHMAP_WIREINIT_Q_ === 1'b1)
-                       DFFNSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E), .SET(1'b0));
-               else
-                       DFFNE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E));
-       endgenerate
-       wire _TECHMAP_REMOVEINIT_Q_ = 1;
-endmodule
-
-module \$_DFFE_NN_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, E, output Q);
-       generate
-               if (_TECHMAP_WIREINIT_Q_ === 1'b1)
-                       DFFNSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(!E), .SET(1'b0));
-               else
-                       DFFNE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(!E));
-       endgenerate
+module \$_DFFE_NP_ (input D, C, E, output Q);
+       DFFNE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E));
        wire _TECHMAP_REMOVEINIT_Q_ = 1;
 endmodule
 
 // DFFR                         D Flip-Flop with Synchronous Reset
-module \$_SDFF_PN0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
-       DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R));
-       wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
-endmodule
-
-module \$_SDFF_PP0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
+module \$_SDFF_PP0_ (input D, C, R, output Q);
        DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R));
-       wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
+       wire _TECHMAP_REMOVEINIT_Q_ = 1;
 endmodule
 
 // DFFNR                D Flip-Flop with Negative-Edge Clock and Synchronous Reset
-module \$_SDFF_NN0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
-       DFFNR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R));
-       wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
-endmodule
-module \$_SDFF_NP0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
+module \$_SDFF_NP0_ (input D, C, R, output Q);
        DFFNR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R));
-       wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
+       wire _TECHMAP_REMOVEINIT_Q_ = 1;
 endmodule
 
 // DFFRE                D Flip-Flop with Clock Enable and Synchronous Reset
-module \$_SDFFE_PN0P_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
-       DFFRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R), .CE(E));
-       wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
-endmodule
-module \$_SDFFE_PP0P_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
+module \$_SDFFE_PP0P_ (input D, C, R, E, output Q);
        DFFRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R), .CE(E));
-       wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
+       wire _TECHMAP_REMOVEINIT_Q_ = 1;
 endmodule
 
 // DFFNRE               D Flip-Flop with Negative-Edge Clock,Clock Enable, and Synchronous Reset
-module \$_SDFFE_NN0P_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
-       DFFNRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R), .CE(E));
-       wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
-endmodule
-module \$_SDFFE_NP0P_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
+module \$_SDFFE_NP0P_ (input D, C, R, E, output Q);
        DFFNRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R), .CE(E));
-       wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
+       wire _TECHMAP_REMOVEINIT_Q_ = 1;
 endmodule
 
 // DFFS                         D Flip-Flop with Synchronous Set
-module \$_SDFF_PN1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
-       DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R));
-       wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
-endmodule
-module \$_SDFF_PP1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
+module \$_SDFF_PP1_ (input D, C, R, output Q);
        DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R));
-       wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
+       wire _TECHMAP_REMOVEINIT_Q_ = 1;
 endmodule
 
 // DFFNS                D Flip-Flop with Negative-Edge Clock and Synchronous Set
-module \$_SDFF_NN1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
-       DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R));
-       wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
-endmodule
-module \$_SDFF_NP1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
+module \$_SDFF_NP1_ (input D, C, R, output Q);
        DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R));
-       wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
+       wire _TECHMAP_REMOVEINIT_Q_ = 1;
 endmodule
 
 // DFFSE                D Flip-Flop with Clock Enable and Synchronous Set
-module \$_SDFFE_PN1P_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
-       DFFSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R), .CE(E));
-       wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
-endmodule
-module \$_SDFFE_PP1P_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
+module \$_SDFFE_PP1P_ (input D, C, R, E, output Q);
        DFFSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R), .CE(E));
-       wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
+       wire _TECHMAP_REMOVEINIT_Q_ = 1;
 endmodule
 
 // DFFNSE               D Flip-Flop with Negative-Edge Clock,Clock Enable,and Synchronous Set
-module \$_SDFFE_NN1P_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
-       DFFNSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R), .CE(E));
-       wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
-endmodule
-module \$_SDFFE_NP1P_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
+module \$_SDFFE_NP1P_ (input D, C, R, E, output Q);
        DFFNSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R), .CE(E));
-       wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
+       wire _TECHMAP_REMOVEINIT_Q_ = 1;
 endmodule
 
 // DFFP                         D Flip-Flop with Asynchronous Preset
-module \$_DFF_PP1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
+module \$_DFF_PP1_ (input D, C, R, output Q);
        DFFP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R));
-       wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
-endmodule
-module \$_DFF_PN1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
-       DFFP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R));
-       wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
+       wire _TECHMAP_REMOVEINIT_Q_ = 1;
 endmodule
 
 // DFFNP                D Flip-Flop with Negative-Edge Clock and Asynchronous Preset
-module \$_DFF_NP1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
+module \$_DFF_NP1_ (input D, C, R, output Q);
        DFFNP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R));
-       wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
-endmodule
-module \$_DFF_NN1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
-       DFFNP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R));
-       wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
+       wire _TECHMAP_REMOVEINIT_Q_ = 1;
 endmodule
 
 // DFFC                         D Flip-Flop with Asynchronous Clear
-module \$_DFF_PP0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
+module \$_DFF_PP0_ (input D, C, R, output Q);
        DFFC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R));
-       wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
-endmodule
-module \$_DFF_PN0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
-       DFFC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R));
-       wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
+       wire _TECHMAP_REMOVEINIT_Q_ = 1;
 endmodule
 
 // DFFNC                D Flip-Flop with Negative-Edge Clock and Asynchronous Clear
-module \$_DFF_NP0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
+module \$_DFF_NP0_ (input D, C, R, output Q);
        DFFNC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R));
-       wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
-endmodule
-module \$_DFF_NN0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
-       DFFNC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R));
-       wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
+       wire _TECHMAP_REMOVEINIT_Q_ = 1;
 endmodule
 
 // DFFPE                D Flip-Flop with Clock Enable and Asynchronous Preset
-module \$_DFFE_PP1P_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
+module \$_DFFE_PP1P_ (input D, C, R, E, output Q);
        DFFPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R), .CE(E));
-       wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
-endmodule
-module \$_DFFE_PN1P_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
-       DFFPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R), .CE(E));
-       wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
+       wire _TECHMAP_REMOVEINIT_Q_ = 1;
 endmodule
 
 // DFFNPE               D Flip-Flop with Negative-Edge Clock,Clock Enable, and Asynchronous Preset
-module \$_DFFE_NP1P_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
+module \$_DFFE_NP1P_ (input D, C, R, E, output Q);
        DFFNPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R), .CE(E));
-       wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
-endmodule
-module \$_DFFE_NN1P_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
-       DFFNPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R), .CE(E));
-       wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
+       wire _TECHMAP_REMOVEINIT_Q_ = 1;
 endmodule
 
 // DFFCE                D Flip-Flop with Clock Enable and Asynchronous Clear
-module \$_DFFE_PP0P_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
+module \$_DFFE_PP0P_ (input D, C, R, E, output Q);
        DFFCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R), .CE(E));
-       wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
-endmodule
-module \$_DFFE_PN0P_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
-       DFFCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R), .CE(E));
-       wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
+       wire _TECHMAP_REMOVEINIT_Q_ = 1;
 endmodule
 
 // DFFNCE               D Flip-Flop with Negative-Edge Clock,Clock Enable and Asynchronous Clear
-module \$_DFFE_NP0P_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
+module \$_DFFE_NP0P_ (input D, C, R, E, output Q);
        DFFNCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R), .CE(E));
-       wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
-endmodule
-module \$_DFFE_NN0P_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
-       DFFNCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R), .CE(E));
-       wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
+       wire _TECHMAP_REMOVEINIT_Q_ = 1;
 endmodule
 
 

diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc
index 987d318403302fc1d5fd7e8f42a9d5ce43e2d8a4..d7b11d4311f02de0afeac7443286284bca4c5b13 100644 (file)
--- a/techlibs/gowin/synth_gowin.cc
+++ b/techlibs/gowin/synth_gowin.cc
@@ -223,6 +223,7 @@ struct SynthGowinPass : public ScriptPass
                        run("opt_clean");
                        if (!nodffe)
                                run("dff2dffe -direct-match $_DFF_* -direct-match $_SDFF_*");
+                       run("dfflegalize -cell $_DFF_?_ 0 -cell $_DFFE_?P_ 0 -cell $_SDFF_?P?_ r -cell $_SDFFE_?P?P_ r -cell $_DFF_?P?_ r -cell $_DFFE_?P?P_ r");
                        run("techmap -map +/gowin/cells_map.v");
                        run("opt_expr -mux_undef");
                        run("simplemap");

diff --git a/tests/arch/gowin/init-error.ys b/tests/arch/gowin/init-error.ys
new file mode 100644 (file)
index 0000000..de3813d
--- /dev/null
+++ b/tests/arch/gowin/init-error.ys
@@ -0,0 +1,5 @@
+read_verilog init.v
+chparam -set INIT 0 myDFF*P*
+hierarchy -top myDFFP
+logger -expect error "unsupported initial value and async reset value combination" 1
+synth_gowin

diff --git a/tests/arch/gowin/init.ys b/tests/arch/gowin/init.ys
index 4d8e442ac7a41fb3a654ca08b55f9d3be7775f04..88e88c15ae25153795bf84487b7211bcfb2e6963 100644 (file)
--- a/tests/arch/gowin/init.ys
+++ b/tests/arch/gowin/init.ys
@@ -35,10 +35,10 @@ design -load read
 # these should synth to a flop with reset
 chparam -set INIT 1 myDFF myDFFN myDFFE myDFFNE
 
-# async should give a warning
+# async would give an error
 # sync should synth to a mux
-chparam -set INIT 0 myDFF*S* myDFF*P*
-chparam -set INIT 1 myDFF*R* myDFF*C*
+chparam -set INIT 0 myDFF*S*
+chparam -set INIT 1 myDFF*R*
 
 proc
 flatten
@@ -66,13 +66,3 @@ select -assert-count 0 t:DFFRE
 select -assert-count 2 t:DFFS
 select -assert-count 2 t:DFFSE
 select -assert-count 12 t:LUT2
-
-# Remove all whiteboxes so we don't inadvertently
-#   count init attributes inside them
-# Should be superseded by https://github.com/YosysHQ/yosys/pull/1949
-delete A:whitebox=1
-
-# check the expected leftover init values
-# this would happen if your reset value is not the initial value
-# which would be weird
-select -assert-count 8 a:init