vendor.xilinx: avoid using `/` for hierarchy in ISE constraint files.

diff --git a/nmigen/vendor/xilinx.py b/nmigen/vendor/xilinx.py
index be8d3776cd55a3645bdf46598596f8990d0c596c..f332a93230fd3c853e93322f6c11207e0181d94b 100644 (file)
--- a/nmigen/vendor/xilinx.py
+++ b/nmigen/vendor/xilinx.py
@@ -276,7 +276,7 @@ class XilinxPlatform(TemplatedPlatform):
             {% endfor %}
             {% for net_signal, port_signal, frequency in platform.iter_clock_constraints() -%}
                 NET "{{net_signal|hierarchy("/")}}" TNM_NET="PRD{{net_signal|hierarchy("/")}}";
-                TIMESPEC "TS{{net_signal|hierarchy("/")}}"=PERIOD "PRD{{net_signal|hierarchy("/")}}" {{1000000000/frequency}} ns HIGH 50%;
+                TIMESPEC "TS{{net_signal|hierarchy("__")}}"=PERIOD "PRD{{net_signal|hierarchy("/")}}" {{1000000000/frequency}} ns HIGH 50%;
             {% endfor %}
             {{get_override("add_constraints")|default("# (add_constraints placeholder)")}}
         """