* sparcl-tdep.c: Clean up formatting and indentation.

diff --git a/gdb/ChangeLog b/gdb/ChangeLog
index d9630b2545a1bd80118087c99b2a38577d84f790..9269843cb2c884c494350225c6720b72c47899bc 100644 (file)
--- a/gdb/ChangeLog
+++ b/gdb/ChangeLog
@@ -1,3 +1,7 @@
+Thu Jan 26 17:32:54 1995  Stu Grossman  (grossman@cygnus.com)
+
+       * sparcl-tdep.c:  Clean up formatting and indentation.
+
 Thu Jan 26 10:49:59 1995  Steve Chamberlain  <sac@splat>
 
        * remote-hms.c (hms_ops): Change ref of hr_load_image

diff --git a/gdb/sparcl-tdep.c b/gdb/sparcl-tdep.c
index b3af30b8b0b5fa43bc74c4bdd6859ac111887ca7..72a97be79c035221c3c48fe2cb21a7f1995025c2 100644 (file)
--- a/gdb/sparcl-tdep.c
+++ b/gdb/sparcl-tdep.c
@@ -42,65 +42,65 @@ Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.  */
 #define DDV_MASK               0x1
 
 int
-sparclite_insert_watchpoint(addr, len, type)
-    CORE_ADDR addr;
-    int len;
-    int type;
+sparclite_insert_watchpoint (addr, len, type)
+     CORE_ADDR addr;
+     int len;
+     int type;
 {
-CORE_ADDR dcr;
+  CORE_ADDR dcr;
 
   dcr = read_register (DCR_REGNUM);
 
   if (!(dcr & DDA1_ENABLE))
-  {
-    write_register (DDA1_REGNUM, addr);
-    dcr &= ~(DDA1_ASI_MASK | DDV_TYPE_MASK);
-    dcr |= (DDA1_SUP_ASI | DDA1_ENABLE);
-    if (type == 1)
     {
-      write_register (DDV1_REGNUM, 0);
-      write_register (DDV2_REGNUM, 0xffffffff);
-      dcr |= (DDV_TYPE_LOAD & (~DDV_COND & ~DDV_MASK));
-    }   
-    else if (type == 0)
-    {
-      write_register (DDV1_REGNUM, 0);
-      write_register (DDV2_REGNUM, 0xffffffff);
-      dcr |= (DDV_TYPE_STORE & (~DDV_COND & ~DDV_MASK));
-    }
-    else
-    {
-      write_register (DDV1_REGNUM, 0);
-      write_register (DDV2_REGNUM, 0xffffffff);
-      dcr |= (DDV_TYPE_ACCESS);
+      write_register (DDA1_REGNUM, addr);
+      dcr &= ~(DDA1_ASI_MASK | DDV_TYPE_MASK);
+      dcr |= (DDA1_SUP_ASI | DDA1_ENABLE);
+      if (type == 1)
+       {
+         write_register (DDV1_REGNUM, 0);
+         write_register (DDV2_REGNUM, 0xffffffff);
+         dcr |= (DDV_TYPE_LOAD & (~DDV_COND & ~DDV_MASK));
+       }   
+      else if (type == 0)
+       {
+         write_register (DDV1_REGNUM, 0);
+         write_register (DDV2_REGNUM, 0xffffffff);
+         dcr |= (DDV_TYPE_STORE & (~DDV_COND & ~DDV_MASK));
+       }
+      else
+       {
+         write_register (DDV1_REGNUM, 0);
+         write_register (DDV2_REGNUM, 0xffffffff);
+         dcr |= (DDV_TYPE_ACCESS);
+       }
+      write_register (DCR_REGNUM, dcr);
     }
-    write_register (DCR_REGNUM, dcr);
-  }
   else if (!(dcr & DDA2_ENABLE))
-  {
-    write_register (DDA2_REGNUM, addr);
-    dcr &= ~(DDA2_ASI_MASK & DDV_TYPE_MASK);
-    dcr |= (DDA2_SUP_ASI | DDA2_ENABLE);
-    if (type == 1)
-    {
-      write_register (DDV1_REGNUM, 0);
-      write_register (DDV2_REGNUM, 0xffffffff);
-      dcr |= (DDV_TYPE_LOAD & ~DDV_COND & ~DDV_MASK);
-    }
-    else if (type == 0)
-    {
-      write_register (DDV1_REGNUM, 0);
-      write_register (DDV2_REGNUM, 0xffffffff);
-      dcr |= (DDV_TYPE_STORE & ~DDV_COND & ~DDV_MASK);
-    }
-    else
     {
-      write_register (DDV1_REGNUM, 0);
-      write_register (DDV2_REGNUM, 0xffffffff);
-      dcr |= (DDV_TYPE_ACCESS);
+      write_register (DDA2_REGNUM, addr);
+      dcr &= ~(DDA2_ASI_MASK & DDV_TYPE_MASK);
+      dcr |= (DDA2_SUP_ASI | DDA2_ENABLE);
+      if (type == 1)
+       {
+         write_register (DDV1_REGNUM, 0);
+         write_register (DDV2_REGNUM, 0xffffffff);
+         dcr |= (DDV_TYPE_LOAD & ~DDV_COND & ~DDV_MASK);
+       }
+      else if (type == 0)
+       {
+         write_register (DDV1_REGNUM, 0);
+         write_register (DDV2_REGNUM, 0xffffffff);
+         dcr |= (DDV_TYPE_STORE & ~DDV_COND & ~DDV_MASK);
+       }
+      else
+       {
+         write_register (DDV1_REGNUM, 0);
+         write_register (DDV2_REGNUM, 0xffffffff);
+         dcr |= (DDV_TYPE_ACCESS);
+       }
+      write_register (DCR_REGNUM, dcr);
     }
-    write_register (DCR_REGNUM, dcr);
-  }
   else
     return -1;
 
@@ -108,23 +108,21 @@ CORE_ADDR dcr;
 } 
 
 int
-sparclite_remove_watchpoint(addr, len, type)
-    CORE_ADDR addr;
-    int len;
-    int type;
+sparclite_remove_watchpoint (addr, len, type)
+     CORE_ADDR addr;
+     int len;
+     int type;
 {
-CORE_ADDR dcr, dda1, dda2;
+  CORE_ADDR dcr, dda1, dda2;
 
   dcr = read_register (DCR_REGNUM);
   dda1 = read_register (DDA1_REGNUM);
   dda2 = read_register (DDA2_REGNUM);
 
-  if ((dcr & DDA1_ENABLE) && addr == dda1) {
+  if ((dcr & DDA1_ENABLE) && addr == dda1)
     write_register (DCR_REGNUM, (dcr & ~DDA1_ENABLE));
-  }
-  else if ((dcr & DDA2_ENABLE) && addr == dda2) {
+  else if ((dcr & DDA2_ENABLE) && addr == dda2)
     write_register (DCR_REGNUM, (dcr & ~DDA2_ENABLE));
-  }
   else
     return -1;
 
@@ -132,22 +130,24 @@ CORE_ADDR dcr, dda1, dda2;
 }
 
 int
-sparclite_insert_hw_breakpoint(addr, len)
-    CORE_ADDR addr;
-    int len;
+sparclite_insert_hw_breakpoint (addr, len)
+     CORE_ADDR addr;
+     int len;
 {
-CORE_ADDR dcr;
+  CORE_ADDR dcr;
 
   dcr = read_register (DCR_REGNUM);
   
-  if (!(dcr & DIA1_ENABLE)) {
-    write_register (DIA1_REGNUM, addr);
-    write_register (DCR_REGNUM, (dcr | DIA1_ENABLE | DIA1_SUP_MODE));
-  }
-  else if (!(dcr & DIA2_ENABLE)) {
-    write_register (DIA2_REGNUM, addr);
-    write_register (DCR_REGNUM, (dcr | DIA2_ENABLE | DIA2_SUP_MODE));
-  }
+  if (!(dcr & DIA1_ENABLE))
+    {
+      write_register (DIA1_REGNUM, addr);
+      write_register (DCR_REGNUM, (dcr | DIA1_ENABLE | DIA1_SUP_MODE));
+    }
+  else if (!(dcr & DIA2_ENABLE))
+    {
+      write_register (DIA2_REGNUM, addr);
+      write_register (DCR_REGNUM, (dcr | DIA2_ENABLE | DIA2_SUP_MODE));
+    }
   else
     return -1;
 
@@ -155,48 +155,49 @@ CORE_ADDR dcr;
 }
 
 int
-sparclite_remove_hw_breakpoint(addr, shadow)
-    CORE_ADDR addr;
-    int shadow;
+sparclite_remove_hw_breakpoint (addr, shadow)
+     CORE_ADDR addr;
+     int shadow;
 {
-CORE_ADDR dcr, dia1, dia2;
+  CORE_ADDR dcr, dia1, dia2;
 
   dcr = read_register (DCR_REGNUM);
   dia1 = read_register (DIA1_REGNUM);
   dia2 = read_register (DIA2_REGNUM);
   
-  if ((dcr & DIA1_ENABLE) && addr == dia1) {
+  if ((dcr & DIA1_ENABLE) && addr == dia1)
     write_register (DCR_REGNUM, (dcr & ~DIA1_ENABLE));
-  }
-  else if ((dcr & DIA2_ENABLE) && addr == dia2) {
+  else if ((dcr & DIA2_ENABLE) && addr == dia2)
     write_register (DCR_REGNUM, (dcr & ~DIA2_ENABLE));
-  }
   else
     return -1;
-   
+
   return 0;
 }
 
 int
-sparclite_check_watch_resources(type, cnt, ot)
-    int type;
-    int cnt;
-    int ot;
+sparclite_check_watch_resources (type, cnt, ot)
+     int type;
+     int cnt;
+     int ot;
 {
-  if (type == bp_hardware_breakpoint) {
-    if (TARGET_HW_BREAK_LIMIT == 0) return 0;
-    else if (cnt <= TARGET_HW_BREAK_LIMIT) return 1;
-  }
-  else {
-    if (TARGET_HW_WATCH_LIMIT == 0) return 0;
-    else if (ot) return -1;
-    else if (cnt <= TARGET_HW_WATCH_LIMIT) return 1;
-  }
+  if (type == bp_hardware_breakpoint)
+    if (TARGET_HW_BREAK_LIMIT == 0)
+      return 0;
+    else if (cnt <= TARGET_HW_BREAK_LIMIT)
+      return 1;
+  else
+    if (TARGET_HW_WATCH_LIMIT == 0)
+      return 0;
+    else if (ot)
+      return -1;
+    else if (cnt <= TARGET_HW_WATCH_LIMIT)
+      return 1;
   return -1;
 }
 
 CORE_ADDR
-sparclite_stopped_data_address()
+sparclite_stopped_data_address ()
 {
   CORE_ADDR dsr, dda1, dda2;
 
@@ -204,7 +205,10 @@ sparclite_stopped_data_address()
   dda1 = read_register (DDA1_REGNUM);
   dda2 = read_register (DDA2_REGNUM);
 
-  if (dsr & 0x10) return dda1;
-  else if (dsr & 0x20) return dda2;
-  else return 0;
+  if (dsr & 0x10)
+    return dda1;
+  else if (dsr & 0x20)
+    return dda2;
+  else
+    return 0;
 }