mem: Remove threadId from memory request class

In general, the ThreadID parameter is unnecessary in the memory system
as the ContextID is what is used for the purposes of locks/wakeups.
Since we allocate sequential ContextIDs for each thread on MT-enabled
CPUs, ThreadID is unnecessary as the CPUs can identify the requesting
thread through sideband info (SenderState / LSQ entries) or ContextID
offset from the base ContextID for a cpu.

This is a re-spin of 20264eb after the revert (bd1c6789) and includes
some fixes of that commit.

diff --git a/ext/sst/ExtMaster.cc b/ext/sst/ExtMaster.cc
index 26a6c4a09edf8e459e3a1a27c4b4d4f3755ff75a..ce6f8ab7baa0bbbeaa7bb32822be82ba1bccb588 100644 (file)
--- a/ext/sst/ExtMaster.cc
+++ b/ext/sst/ExtMaster.cc
@@ -177,7 +177,7 @@ ExtMaster::handleEvent(SST::Event* event)
     }
 
     auto req = new Request(ev->getAddr(), ev->getSize(), flags, 0);
-    req->setThreadContext(ev->getGroupId(), 0);
+    req->setContext(ev->getGroupId());
 
     auto pkt = new Packet(req, cmdO);
     pkt->allocate();

diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 6f66e5ae19a54f049690fa690b53571ab0f54661..d3286a6b0a288e8441be5c32594901a817827a47 100644 (file)
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -1521,8 +1521,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
               // with unexpected atomic snoop requests.
               warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg);
               Request req(0, val, 1, flags,  Request::funcMasterId,
-                          tc->pcState().pc(), tc->contextId(),
-                          tc->threadId());
+                          tc->pcState().pc(), tc->contextId());
               fault = tc->getDTBPtr()->translateFunctional(&req, tc, mode, tranType);
               TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
               HCR   hcr   = readMiscRegNoEffect(MISCREG_HCR);
@@ -1768,7 +1767,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
                 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg);
                 req->setVirt(0, val, 1, flags,  Request::funcMasterId,
                                tc->pcState().pc());
-                req->setThreadContext(tc->contextId(), tc->threadId());
+                req->setContext(tc->contextId());
                 fault = tc->getDTBPtr()->translateFunctional(req, tc, mode,
                                                              tranType);
 

diff --git a/src/arch/arm/vtophys.cc b/src/arch/arm/vtophys.cc
index 3aad35818b8459e7d02c61a42aa5b35c7f82d494..24fc5a5c7bac498e9b68ab15680520086976445b 100644 (file)
--- a/src/arch/arm/vtophys.cc
+++ b/src/arch/arm/vtophys.cc
@@ -69,7 +69,7 @@ try_translate(ThreadContext *tc, Addr addr)
     Fault fault;
     // Set up a functional memory Request to pass to the TLB
     // to get it to translate the vaddr to a paddr
-    Request req(0, addr, 64, 0x40, -1, 0, 0, 0);
+    Request req(0, addr, 64, 0x40, -1, 0, 0);
     ArmISA::TLB *tlb;
 
     // Check the TLBs for a translation

diff --git a/src/arch/hsail/insts/mem.hh b/src/arch/hsail/insts/mem.hh
index 29091f9d141e2f9bbfb300e3a25d928550dec3a7..f2792cd49c13eeee7c16f5753f69ba6e61f9ce0e 100644 (file)
--- a/src/arch/hsail/insts/mem.hh
+++ b/src/arch/hsail/insts/mem.hh
@@ -479,7 +479,7 @@ namespace HsailISA
                         } else {
                             Request *req = new Request(0, vaddr, sizeof(c0), 0,
                                           gpuDynInst->computeUnit()->masterId(),
-                                          0, gpuDynInst->wfDynId, i);
+                                          0, gpuDynInst->wfDynId);
 
                             gpuDynInst->setRequestFlags(req);
                             PacketPtr pkt = new Packet(req, MemCmd::ReadReq);
@@ -528,7 +528,7 @@ namespace HsailISA
                     // create request
                     Request *req = new Request(0, 0, 0, 0,
                                   gpuDynInst->computeUnit()->masterId(),
-                                  0, gpuDynInst->wfDynId, -1);
+                                  0, gpuDynInst->wfDynId);
                     req->setFlags(Request::ACQUIRE);
                     gpuDynInst->computeUnit()->injectGlobalMemFence(gpuDynInst, false, req);
                 }
@@ -974,7 +974,7 @@ namespace HsailISA
                     // create request
                     Request *req = new Request(0, 0, 0, 0,
                                   gpuDynInst->computeUnit()->masterId(),
-                                  0, gpuDynInst->wfDynId, -1);
+                                  0, gpuDynInst->wfDynId);
                     req->setFlags(Request::RELEASE);
                     gpuDynInst->computeUnit()->injectGlobalMemFence(gpuDynInst, false, req);
 
@@ -1026,7 +1026,7 @@ namespace HsailISA
                             Request *req =
                               new Request(0, vaddr, sizeof(c0), 0,
                                           gpuDynInst->computeUnit()->masterId(),
-                                          0, gpuDynInst->wfDynId, i);
+                                          0, gpuDynInst->wfDynId);
 
                             gpuDynInst->setRequestFlags(req);
                             PacketPtr pkt = new Packet(req, MemCmd::WriteReq);
@@ -1366,7 +1366,7 @@ namespace HsailISA
                     // create request
                     Request *req = new Request(0, 0, 0, 0,
                                   gpuDynInst->computeUnit()->masterId(),
-                                  0, gpuDynInst->wfDynId, -1);
+                                  0, gpuDynInst->wfDynId);
                     req->setFlags(Request::RELEASE);
                     gpuDynInst->computeUnit()->injectGlobalMemFence(gpuDynInst, false, req);
 
@@ -1477,7 +1477,7 @@ namespace HsailISA
                         Request *req =
                             new Request(0, vaddr, sizeof(c0), 0,
                                         gpuDynInst->computeUnit()->masterId(),
-                                        0, gpuDynInst->wfDynId, i,
+                                        0, gpuDynInst->wfDynId,
                                         gpuDynInst->makeAtomicOpFunctor<c0>(e,
                                         f, this->opType));
 
@@ -1533,7 +1533,7 @@ namespace HsailISA
                     // create request
                     Request *req = new Request(0, 0, 0, 0,
                                   gpuDynInst->computeUnit()->masterId(),
-                                  0, gpuDynInst->wfDynId, -1);
+                                  0, gpuDynInst->wfDynId);
                     req->setFlags(Request::ACQUIRE);
                     gpuDynInst->computeUnit()->injectGlobalMemFence(gpuDynInst, false, req);
                 }

diff --git a/src/arch/mips/locked_mem.hh b/src/arch/mips/locked_mem.hh
index a5ff467b3eb63d41ca5f19d18e13b72e35be63ed..a1d89de9988643c15fabb91cc8fe064c1d642eb9 100644 (file)
--- a/src/arch/mips/locked_mem.hh
+++ b/src/arch/mips/locked_mem.hh
@@ -79,9 +79,9 @@ handleLockedRead(XC *xc, Request *req)
 {
     xc->setMiscReg(MISCREG_LLADDR, req->getPaddr() & ~0xf);
     xc->setMiscReg(MISCREG_LLFLAG, true);
-    DPRINTF(LLSC, "[tid:%i]: Load-Link Flag Set & Load-Link"
+    DPRINTF(LLSC, "[cid:%i]: Load-Link Flag Set & Load-Link"
                   " Address set to %x.\n",
-            req->threadId(), req->getPaddr() & ~0xf);
+            req->contextId(), req->getPaddr() & ~0xf);
 }
 
 template <class XC>
@@ -123,13 +123,13 @@ handleLockedWrite(XC *xc, Request *req, Addr cacheBlockMask)
             }
 
             if (!lock_flag){
-                DPRINTF(LLSC, "[tid:%i]: Lock Flag Set, "
+                DPRINTF(LLSC, "[cid:%i]: Lock Flag Set, "
                               "Store Conditional Failed.\n",
-                        req->threadId());
+                        req->contextId());
             } else if ((req->getPaddr() & ~0xf) != lock_addr) {
-                DPRINTF(LLSC, "[tid:%i]: Load-Link Address Mismatch, "
+                DPRINTF(LLSC, "[cid:%i]: Load-Link Address Mismatch, "
                               "Store Conditional Failed.\n",
-                        req->threadId());
+                        req->contextId());
             }
             // store conditional failed already, so don't issue it to mem
             return false;

diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index 438c38812fa790083daca49634a10a542d62a03e..748602c257f5f19352105529ccbd6a3f78292211 100644 (file)
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -296,6 +296,10 @@ class BaseCPU : public MemObject
    /// Get the number of thread contexts available
    unsigned numContexts() { return threadContexts.size(); }
 
+    /// Convert ContextID to threadID
+    ThreadID contextToThread(ContextID cid)
+    { return static_cast<ThreadID>(cid - threadContexts[0]->contextId()); }
+
   public:
     typedef BaseCPUParams Params;
     const Params *params() const

diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index 031337aec32595800e31b817e52b48e4ed91981f..e846f679018a9df5bf1b0b4631abdcf80fcf5f8d 100644 (file)
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -886,7 +886,7 @@ BaseDynInst<Impl>::initiateMemRead(Addr addr, unsigned size, unsigned flags)
         sreqHigh = savedSreqHigh;
     } else {
         req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(),
-                          thread->contextId(), threadNumber);
+                          thread->contextId());
 
         req->taskId(cpu->taskId());
 
@@ -942,7 +942,7 @@ BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size,
         sreqHigh = savedSreqHigh;
     } else {
         req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(),
-                          thread->contextId(), threadNumber);
+                          thread->contextId());
 
         req->taskId(cpu->taskId());
 

diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc
index ac476e5f460f28f9735b503f7d090b792e158247..4d5919cdf88dbec16008f87252553f093b2a643a 100644 (file)
--- a/src/cpu/checker/cpu.cc
+++ b/src/cpu/checker/cpu.cc
@@ -155,7 +155,7 @@ CheckerCPU::readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags)
     // Need to account for multiple accesses like the Atomic and TimingSimple
     while (1) {
         memReq = new Request(0, addr, size, flags, masterId,
-                             thread->pcState().instAddr(), tc->contextId(), 0);
+                             thread->pcState().instAddr(), tc->contextId());
 
         // translate to physical address
         fault = dtb->translateFunctional(memReq, tc, BaseTLB::Read);
@@ -243,7 +243,7 @@ CheckerCPU::writeMem(uint8_t *data, unsigned size,
     // Need to account for a multiple access like Atomic and Timing CPUs
     while (1) {
         memReq = new Request(0, addr, size, flags, masterId,
-                             thread->pcState().instAddr(), tc->contextId(), 0);
+                             thread->pcState().instAddr(), tc->contextId());
 
         // translate to physical address
         fault = dtb->translateFunctional(memReq, tc, BaseTLB::Write);

diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh
index 289861521508bfe89f3b5026c1b763db6ffd3808..5d5900aaec667f0ef072dee596b9ba2a9593aba5 100644 (file)
--- a/src/cpu/checker/cpu_impl.hh
+++ b/src/cpu/checker/cpu_impl.hh
@@ -248,8 +248,7 @@ Checker<Impl>::verify(DynInstPtr &completed_inst)
                                      sizeof(MachInst),
                                      0,
                                      masterId,
-                                     fetch_PC, thread->contextId(),
-                                     unverifiedInst->threadNumber);
+                                     fetch_PC, thread->contextId());
                 memReq->setVirt(0, fetch_PC, sizeof(MachInst),
                                 Request::INST_FETCH, masterId, thread->instAddr());
 

diff --git a/src/cpu/kvm/base.cc b/src/cpu/kvm/base.cc
index bf4d686030fd9cc1ea722d4249914b659a857701..0670f61c684b04fefce1210cd67a508f1ee5329c 100644 (file)
--- a/src/cpu/kvm/base.cc
+++ b/src/cpu/kvm/base.cc
@@ -1027,7 +1027,7 @@ BaseKvmCPU::doMMIOAccess(Addr paddr, void *data, int size, bool write)
     syncThreadContext();
 
     Request mmio_req(paddr, size, Request::UNCACHEABLE, dataMasterId());
-    mmio_req.setThreadContext(tc->contextId(), 0);
+    mmio_req.setContext(tc->contextId());
     // Some architectures do need to massage physical addresses a bit
     // before they are inserted into the memory system. This enables
     // APIC accesses on x86 and m5ops where supported through a MMIO

diff --git a/src/cpu/kvm/x86_cpu.cc b/src/cpu/kvm/x86_cpu.cc
index c6c874dc49d41b666b69e18140e4be8b36365984..9e9115ef51f6f4b5f0497771d4f0d92bc33c2392 100644 (file)
--- a/src/cpu/kvm/x86_cpu.cc
+++ b/src/cpu/kvm/x86_cpu.cc
@@ -1346,7 +1346,7 @@ X86KvmCPU::handleKvmExitIO()
 
     Request io_req(pAddr, kvm_run.io.size, Request::UNCACHEABLE,
                    dataMasterId());
-    io_req.setThreadContext(tc->contextId(), 0);
+    io_req.setContext(tc->contextId());
 
     const MemCmd cmd(isWrite ? MemCmd::WriteReq : MemCmd::ReadReq);
     // Temporarily lock and migrate to the event queue of the

diff --git a/src/cpu/minor/fetch1.cc b/src/cpu/minor/fetch1.cc
index 84aaf02f580f21269f3083d5ad98fec237fd9b19..d19d7b042657f52212990c2338ae909446efce48 100644 (file)
--- a/src/cpu/minor/fetch1.cc
+++ b/src/cpu/minor/fetch1.cc
@@ -135,8 +135,7 @@ Fetch1::fetchLine()
         "%s addr: 0x%x pc: %s line_offset: %d request_size: %d\n",
         request_id, aligned_pc, pc, line_offset, request_size);
 
-    request->request.setThreadContext(cpu.threads[0]->getTC()->contextId(),
-                                      /* thread id */ 0);
+    request->request.setContext(cpu.threads[0]->getTC()->contextId());
     request->request.setVirt(0 /* asid */,
         aligned_pc, request_size, Request::INST_FETCH, cpu.instMasterId(),
         /* I've no idea why we need the PC, but give it */

diff --git a/src/cpu/minor/lsq.cc b/src/cpu/minor/lsq.cc
index e0c5796c89c6c2485f24c9005dda61aed89ce2f6..b5c0bc97415231865c9f67faaadf3faa05a856ab 100644 (file)
--- a/src/cpu/minor/lsq.cc
+++ b/src/cpu/minor/lsq.cc
@@ -422,7 +422,7 @@ LSQ::SplitDataRequest::makeFragmentRequests()
 
         Request *fragment = new Request();
 
-        fragment->setThreadContext(request.contextId(), /* thread id */ 0);
+        fragment->setContext(request.contextId());
         fragment->setVirt(0 /* asid */,
             fragment_addr, fragment_size, request.getFlags(),
             request.masterId(),
@@ -1070,7 +1070,8 @@ LSQ::tryToSend(LSQRequestPtr request)
 
         if (request->request.isMmappedIpr()) {
             ThreadContext *thread =
-                cpu.getContext(request->request.threadId());
+                cpu.getContext(cpu.contextToThread(
+                                request->request.contextId()));
 
             if (request->isLoad) {
                 DPRINTF(MinorMem, "IPR read inst: %s\n", *(request->inst));
@@ -1502,7 +1503,7 @@ LSQ::pushRequest(MinorDynInstPtr inst, bool isLoad, uint8_t *data,
         inst->traceData->setMem(addr, size, flags);
 
     int cid = cpu.threads[inst->id.threadId]->getTC()->contextId();
-    request->request.setThreadContext(cid, /* thread id */ 0);
+    request->request.setContext(cid);
     request->request.setVirt(0 /* asid */,
         addr, size, flags, cpu.dataMasterId(),
         /* I've no idea why we need the PC, but give it */

diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 4b1479bcbc3d6f03d29635e797f8f677f3b3b498..3b29d87d43238cae8b377f3aad9ab060b29068ec 100644 (file)
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -378,7 +378,7 @@ template<class Impl>
 void
 DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt)
 {
-    ThreadID tid = pkt->req->threadId();
+    ThreadID tid = cpu->contextToThread(pkt->req->contextId());
 
     DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n", tid);
     assert(!cpu->switchedOut());
@@ -622,7 +622,7 @@ DefaultFetch<Impl>::fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc)
     RequestPtr mem_req =
         new Request(tid, fetchBufferBlockPC, fetchBufferSize,
                     Request::INST_FETCH, cpu->instMasterId(), pc,
-                    cpu->thread[tid]->contextId(), tid);
+                    cpu->thread[tid]->contextId());
 
     mem_req->taskId(cpu->taskId());
 
@@ -640,7 +640,7 @@ template <class Impl>
 void
 DefaultFetch<Impl>::finishTranslation(const Fault &fault, RequestPtr mem_req)
 {
-    ThreadID tid = mem_req->threadId();
+    ThreadID tid = cpu->contextToThread(mem_req->contextId());
     Addr fetchBufferBlockPC = mem_req->getVaddr();
 
     assert(!cpu->switchedOut());

diff --git a/src/cpu/o3/lsq.hh b/src/cpu/o3/lsq.hh
index dcd676221d52e795beba7f45bd653d3f2aaf1c30..6bc9b3d73f3596d8ca3ffa233e88918aed1e981a 100644 (file)
--- a/src/cpu/o3/lsq.hh
+++ b/src/cpu/o3/lsq.hh
@@ -334,7 +334,7 @@ Fault
 LSQ<Impl>::read(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh,
                 int load_idx)
 {
-    ThreadID tid = req->threadId();
+    ThreadID tid = cpu->contextToThread(req->contextId());
 
     return thread[tid].read(req, sreqLow, sreqHigh, load_idx);
 }
@@ -344,7 +344,7 @@ Fault
 LSQ<Impl>::write(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh,
                  uint8_t *data, int store_idx)
 {
-    ThreadID tid = req->threadId();
+    ThreadID tid = cpu->contextToThread(req->contextId());
 
     return thread[tid].write(req, sreqLow, sreqHigh, data, store_idx);
 }

diff --git a/src/cpu/o3/lsq_impl.hh b/src/cpu/o3/lsq_impl.hh
index 06467243dcebcb0b681dc4fbca06aff72d9d847f..9080907fe84fc1c20cb6dda843c9dad50a610765 100644 (file)
--- a/src/cpu/o3/lsq_impl.hh
+++ b/src/cpu/o3/lsq_impl.hh
@@ -347,7 +347,8 @@ LSQ<Impl>::recvTimingResp(PacketPtr pkt)
         DPRINTF(LSQ, "Got error packet back for address: %#X\n",
                 pkt->getAddr());
 
-    thread[pkt->req->threadId()].completeDataAccess(pkt);
+    thread[cpu->contextToThread(pkt->req->contextId())]
+        .completeDataAccess(pkt);
 
     if (pkt->isInvalidate()) {
         // This response also contains an invalidate; e.g. this can be the case

diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index f3e14d40199044bebc3e2917d3182d0e8ba98afc..3996b33cab6a30ad5d4481a1849d2846757b84f2 100644 (file)
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -87,9 +87,9 @@ AtomicSimpleCPU::init()
     BaseSimpleCPU::init();
 
     int cid = threadContexts[0]->contextId();
-    ifetch_req.setThreadContext(cid, 0);
-    data_read_req.setThreadContext(cid, 0);
-    data_write_req.setThreadContext(cid, 0);
+    ifetch_req.setContext(cid);
+    data_read_req.setContext(cid);
+    data_write_req.setContext(cid);
 }
 
 AtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p)
@@ -554,9 +554,9 @@ AtomicSimpleCPU::tick()
     if (numThreads > 1) {
         ContextID cid = threadContexts[curThread]->contextId();
 
-        ifetch_req.setThreadContext(cid, curThread);
-        data_read_req.setThreadContext(cid, curThread);
-        data_write_req.setThreadContext(cid, curThread);
+        ifetch_req.setContext(cid);
+        data_read_req.setContext(cid);
+        data_write_req.setContext(cid);
     }
 
     SimpleExecContext& t_info = *threadInfo[curThread];

diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 43f4eb9f4590d5e74720d4c499f15e32800447e9..6b63d894f0cca1df3f193738cba73a0f7de7bbc9 100644 (file)
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -419,7 +419,6 @@ TimingSimpleCPU::initiateMemRead(Addr addr, unsigned size, unsigned flags)
 
     Fault fault;
     const int asid = 0;
-    const ThreadID tid = curThread;
     const Addr pc = thread->instAddr();
     unsigned block_size = cacheLineSize();
     BaseTLB::Mode mode = BaseTLB::Read;
@@ -427,9 +426,8 @@ TimingSimpleCPU::initiateMemRead(Addr addr, unsigned size, unsigned flags)
     if (traceData)
         traceData->setMem(addr, size, flags);
 
-    RequestPtr req  = new Request(asid, addr, size,
-                                  flags, dataMasterId(), pc,
-                                  thread->contextId(), tid);
+    RequestPtr req = new Request(asid, addr, size, flags, dataMasterId(), pc,
+                                 thread->contextId());
 
     req->taskId(taskId());
 
@@ -494,7 +492,6 @@ TimingSimpleCPU::writeMem(uint8_t *data, unsigned size,
 
     uint8_t *newData = new uint8_t[size];
     const int asid = 0;
-    const ThreadID tid = curThread;
     const Addr pc = thread->instAddr();
     unsigned block_size = cacheLineSize();
     BaseTLB::Mode mode = BaseTLB::Write;
@@ -510,9 +507,8 @@ TimingSimpleCPU::writeMem(uint8_t *data, unsigned size,
     if (traceData)
         traceData->setMem(addr, size, flags);
 
-    RequestPtr req = new Request(asid, addr, size,
-                                 flags, dataMasterId(), pc,
-                                 thread->contextId(), tid);
+    RequestPtr req = new Request(asid, addr, size, flags, dataMasterId(), pc,
+                                 thread->contextId());
 
     req->taskId(taskId());
 
@@ -614,7 +610,7 @@ TimingSimpleCPU::fetch()
         _status = BaseSimpleCPU::Running;
         Request *ifetch_req = new Request();
         ifetch_req->taskId(taskId());
-        ifetch_req->setThreadContext(thread->contextId(), curThread);
+        ifetch_req->setContext(thread->contextId());
         setupFetchRequest(ifetch_req);
         DPRINTF(SimpleCPU, "Translating address %#x\n", ifetch_req->getVaddr());
         thread->itb->translateTiming(ifetch_req, thread->getTC(),

diff --git a/src/cpu/testers/memtest/memtest.cc b/src/cpu/testers/memtest/memtest.cc
index b0dde6d27ada7f624e2474acb8efc2610b0008fa..3e0d67c3223871219b41fede9c441ef96709a110 100644 (file)
--- a/src/cpu/testers/memtest/memtest.cc
+++ b/src/cpu/testers/memtest/memtest.cc
@@ -243,7 +243,7 @@ MemTest::tick()
     bool do_functional = (random_mt.random(0, 100) < percentFunctional) &&
         !uncacheable;
     Request *req = new Request(paddr, 1, flags, masterId);
-    req->setThreadContext(id, 0);
+    req->setContext(id);
 
     outstandingAddrs.insert(paddr);
 

diff --git a/src/cpu/testers/networktest/networktest.cc b/src/cpu/testers/networktest/networktest.cc
index 79a563f284c2caa31890117090aab24ca05b145d..6ad26077cffb78fc031a465ada3dcc5b0edbce81 100644 (file)
--- a/src/cpu/testers/networktest/networktest.cc
+++ b/src/cpu/testers/networktest/networktest.cc
@@ -243,7 +243,7 @@ NetworkTest::generatePkt()
         // generate packet for virtual network 1
         requestType = MemCmd::ReadReq;
         flags.set(Request::INST_FETCH);
-        req = new Request(0, 0x0, access_size, flags, masterId, 0x0, 0, 0);
+        req = new Request(0, 0x0, access_size, flags, masterId, 0x0, 0);
         req->setPaddr(paddr);
     } else {  // if (randomReqType == 2)
         // generate packet for virtual network 2
@@ -251,7 +251,7 @@ NetworkTest::generatePkt()
         req = new Request(paddr, access_size, flags, masterId);
     }
 
-    req->setThreadContext(id,0);
+    req->setContext(id);
 
     //No need to do functional simulation
     //We just do timing simulation of the network

diff --git a/src/cpu/testers/rubytest/Check.cc b/src/cpu/testers/rubytest/Check.cc
index c8e7816c34ac26db9b5d88e9f505badf850df207..c869bd72826b3d69a842b40a2266d2ccb391d5c9 100644 (file)
--- a/src/cpu/testers/rubytest/Check.cc
+++ b/src/cpu/testers/rubytest/Check.cc
@@ -107,7 +107,7 @@ Check::initiatePrefetch()
     // Prefetches are assumed to be 0 sized
     Request *req = new Request(m_address, 0, flags,
             m_tester_ptr->masterId(), curTick(), m_pc);
-    req->setThreadContext(index, 0);
+    req->setContext(index);
 
     PacketPtr pkt = new Packet(req, cmd);
     // despite the oddity of the 0 size (questionable if this should
@@ -180,7 +180,7 @@ Check::initiateAction()
     Request *req = new Request(writeAddr, 1, flags, m_tester_ptr->masterId(),
                                curTick(), m_pc);
 
-    req->setThreadContext(index, 0);
+    req->setContext(index);
     Packet::Command cmd;
 
     // 1 out of 8 chance, issue an atomic rather than a write
@@ -245,7 +245,7 @@ Check::initiateCheck()
     Request *req = new Request(m_address, CHECK_SIZE, flags,
                                m_tester_ptr->masterId(), curTick(), m_pc);
 
-    req->setThreadContext(index, 0);
+    req->setContext(index);
     PacketPtr pkt = new Packet(req, MemCmd::ReadReq);
     uint8_t *dataArray = new uint8_t[CHECK_SIZE];
     pkt->dataDynamic(dataArray);

diff --git a/src/cpu/trace/trace_cpu.cc b/src/cpu/trace/trace_cpu.cc
index d6aa9aaebc89548cf35706bf7a1c1e89c2b7439e..e81a7981878ec3ec12acc017de2e9db4be480ccf 100644 (file)
--- a/src/cpu/trace/trace_cpu.cc
+++ b/src/cpu/trace/trace_cpu.cc
@@ -627,7 +627,7 @@ TraceCPU::ElasticDataGen::executeMemReq(GraphNode* node_ptr)
     // Create a request and the packet containing request
     Request* req = new Request(node_ptr->physAddr, node_ptr->size,
                                node_ptr->flags, masterID, node_ptr->seqNum,
-                               ContextID(0), ThreadID(0));
+                               ContextID(0));
     req->setPC(node_ptr->pc);
     // If virtual address is valid, set the asid and virtual address fields
     // of the request.
@@ -1123,7 +1123,7 @@ TraceCPU::FixedRetryGen::send(Addr addr, unsigned size, const MemCmd& cmd,
     req->setPC(pc);
 
     // If this is not done it triggers assert in L1 cache for invalid contextId
-    req->setThreadContext(ContextID(0), ThreadID(0));
+    req->setContext(ContextID(0));
 
     // Embed it in a packet
     PacketPtr pkt = new Packet(req, cmd);

diff --git a/src/gpu-compute/compute_unit.cc b/src/gpu-compute/compute_unit.cc
index 1387f9b5683b35c34894174da172ec1ebb888551..49029f815f4ac490db1e97f4fc8102fd56efbac2 100644 (file)
--- a/src/gpu-compute/compute_unit.cc
+++ b/src/gpu-compute/compute_unit.cc
@@ -982,7 +982,7 @@ ComputeUnit::injectGlobalMemFence(GPUDynInstPtr gpuDynInst, bool kernelLaunch,
                                   Request* req)
 {
     if (!req) {
-        req = new Request(0, 0, 0, 0, masterId(), 0, gpuDynInst->wfDynId, -1);
+        req = new Request(0, 0, 0, 0, masterId(), 0, gpuDynInst->wfDynId);
     }
     req->setPaddr(0);
     if (kernelLaunch) {

diff --git a/src/gpu-compute/dispatcher.cc b/src/gpu-compute/dispatcher.cc
index 55e4be72a18d2cb1199d29afb0eb1484237bacd8..95c0c56a20eb878a66b31c9d2bd5c9224d37f067 100644 (file)
--- a/src/gpu-compute/dispatcher.cc
+++ b/src/gpu-compute/dispatcher.cc
@@ -222,7 +222,7 @@ GpuDispatcher::write(PacketPtr pkt)
         ndr->addrToNotify = (volatile bool*)curTask.addrToNotify;
         ndr->numDispLeft = (volatile uint32_t*)curTask.numDispLeft;
         ndr->dispatchId = nextId;
-        ndr->curTid = pkt->req->threadId();
+        ndr->curCid = pkt->req->contextId();
         DPRINTF(GPUDisp, "launching kernel %d\n",nextId);
         execIds.push(nextId);
         ++nextId;
@@ -272,7 +272,7 @@ GpuDispatcher::exec()
 
         while (ndRangeMap[execId].wg_disp_rem) {
             //update the thread context
-            shader->updateThreadContext(ndRangeMap[execId].curTid);
+            shader->updateContext(ndRangeMap[execId].curCid);
 
             // attempt to dispatch_workgroup
             if (!shader->dispatch_workgroups(&ndRangeMap[execId])) {

diff --git a/src/gpu-compute/ndrange.hh b/src/gpu-compute/ndrange.hh
index d1ad35d4b11fe27d45853350e7b1e6c6ba0b1c8f..db6dc455f9309a91df04ec9106aa8d472e9da88f 100644 (file)
--- a/src/gpu-compute/ndrange.hh
+++ b/src/gpu-compute/ndrange.hh
@@ -64,7 +64,7 @@ struct NDRange
     volatile bool *addrToNotify;
     volatile uint32_t *numDispLeft;
     int dispatchId;
-    int curTid; // Current thread id
+    int curCid; // Current context id
 };
 
 #endif // __NDRANGE_HH__

diff --git a/src/gpu-compute/shader.cc b/src/gpu-compute/shader.cc
index 31aa1e4cff4954d71d9169fa7fa0c7e3d73d8150..d02f95d2953e73acbad4d722091489ae4567c346 100644 (file)
--- a/src/gpu-compute/shader.cc
+++ b/src/gpu-compute/shader.cc
@@ -116,10 +116,10 @@ Shader::~Shader()
 }
 
 void
-Shader::updateThreadContext(int tid) {
-    // thread context of the thread which dispatched work
+Shader::updateContext(int cid) {
+    // context of the thread which dispatched work
     assert(cpuPointer);
-    gpuTc = cpuPointer->getContext(tid);
+    gpuTc = cpuPointer->getContext(cid);
     assert(gpuTc);
 }
 

diff --git a/src/gpu-compute/shader.hh b/src/gpu-compute/shader.hh
index 91ea8aae02cbd0f17784789a464c95f144397f61..c1f741d6a3da51152f770f6cdf58078fb3df3e95 100644 (file)
--- a/src/gpu-compute/shader.hh
+++ b/src/gpu-compute/shader.hh
@@ -205,7 +205,7 @@ class Shader : public SimObject
     bool dispatch_workgroups(NDRange *ndr);
     Addr mmap(int length);
     void functionalTLBAccess(PacketPtr pkt, int cu_id, BaseTLB::Mode mode);
-    void updateThreadContext(int tid);
+    void updateContext(int cid);
     void hostWakeUp(BaseCPU *cpu);
 };
 

diff --git a/src/mem/cache/prefetch/queued.cc b/src/mem/cache/prefetch/queued.cc
index 03ca3188fb8b19c5a59e445ac6ee330dfc0ec4d2..4bc75acd631ced66b211fc9a198b7ddd19dd97de 100644 (file)
--- a/src/mem/cache/prefetch/queued.cc
+++ b/src/mem/cache/prefetch/queued.cc
@@ -122,8 +122,7 @@ QueuedPrefetcher::notify(const PacketPtr &pkt)
             pf_pkt->allocate();
 
             if (pkt->req->hasContextId()) {
-                pf_req->setThreadContext(pkt->req->contextId(),
-                                         pkt->req->threadId());
+                pf_req->setContext(pkt->req->contextId());
             }
 
             if (tagPrefetch && pkt->req->hasPC()) {

diff --git a/src/mem/request.hh b/src/mem/request.hh
index 0d2750a16f4bf48a58f996b1b071d202afd85ebb..d9f58d21d71257e25d481defbade9aa3706bb458 100644 (file)
--- a/src/mem/request.hh
+++ b/src/mem/request.hh
@@ -257,14 +257,13 @@ class Request
         VALID_PC             = 0x00000010,
         /** Whether or not the context ID is valid. */
         VALID_CONTEXT_ID     = 0x00000020,
-        VALID_THREAD_ID      = 0x00000040,
         /** Whether or not the sc result is valid. */
         VALID_EXTRA_DATA     = 0x00000080,
         /**
          * These flags are *not* cleared when a Request object is reused
          * (assigned a new address).
          */
-        STICKY_PRIVATE_FLAGS = VALID_CONTEXT_ID | VALID_THREAD_ID
+        STICKY_PRIVATE_FLAGS = VALID_CONTEXT_ID
     };
 
   private:
@@ -339,10 +338,8 @@ class Request
      * store conditional or the compare value for a CAS. */
     uint64_t _extraData;
 
-    /** The context ID (for statistics, typically). */
+    /** The context ID (for statistics, locks, and wakeups). */
     ContextID _contextId;
-    /** The thread ID (id within this CPU) */
-    ThreadID _threadId;
 
     /** program counter of initiating access; for tracing/debugging */
     Addr _pc;
@@ -363,21 +360,21 @@ class Request
     Request()
         : _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
           _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
-          _extraData(0), _contextId(0), _threadId(0), _pc(0),
+          _extraData(0), _contextId(0), _pc(0),
           _reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0),
           accessDelta(0), depth(0)
     {}
 
     Request(Addr paddr, unsigned size, Flags flags, MasterID mid,
-            InstSeqNum seq_num, ContextID cid, ThreadID tid)
+            InstSeqNum seq_num, ContextID cid)
         : _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
           _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
-          _extraData(0), _contextId(0), _threadId(0), _pc(0),
+          _extraData(0), _contextId(0), _pc(0),
           _reqInstSeqNum(seq_num), atomicOpFunctor(nullptr), translateDelta(0),
           accessDelta(0), depth(0)
     {
         setPhys(paddr, size, flags, mid, curTick());
-        setThreadContext(cid, tid);
+        setContext(cid);
         privateFlags.set(VALID_INST_SEQ_NUM);
     }
 
@@ -389,7 +386,7 @@ class Request
     Request(Addr paddr, unsigned size, Flags flags, MasterID mid)
         : _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
           _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
-          _extraData(0), _contextId(0), _threadId(0), _pc(0),
+          _extraData(0), _contextId(0), _pc(0),
           _reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0),
           accessDelta(0), depth(0)
     {
@@ -399,7 +396,7 @@ class Request
     Request(Addr paddr, unsigned size, Flags flags, MasterID mid, Tick time)
         : _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
           _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
-          _extraData(0), _contextId(0), _threadId(0), _pc(0),
+          _extraData(0), _contextId(0), _pc(0),
           _reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0),
           accessDelta(0), depth(0)
     {
@@ -410,7 +407,7 @@ class Request
             Addr pc)
         : _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
           _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
-          _extraData(0), _contextId(0), _threadId(0), _pc(pc),
+          _extraData(0), _contextId(0), _pc(pc),
           _reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0),
           accessDelta(0), depth(0)
     {
@@ -419,23 +416,23 @@ class Request
     }
 
     Request(int asid, Addr vaddr, unsigned size, Flags flags, MasterID mid,
-            Addr pc, ContextID cid, ThreadID tid)
+            Addr pc, ContextID cid)
         : _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
           _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
-          _extraData(0), _contextId(0), _threadId(0), _pc(0),
+          _extraData(0), _contextId(0), _pc(0),
           _reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0),
           accessDelta(0), depth(0)
     {
         setVirt(asid, vaddr, size, flags, mid, pc);
-        setThreadContext(cid, tid);
+        setContext(cid);
     }
 
-    Request(int asid, Addr vaddr, int size, Flags flags, MasterID mid, Addr pc,
-            int cid, ThreadID tid, AtomicOpFunctor *atomic_op)
+    Request(int asid, Addr vaddr, unsigned size, Flags flags, MasterID mid,
+            Addr pc, ContextID cid, AtomicOpFunctor *atomic_op)
         : atomicOpFunctor(atomic_op)
     {
         setVirt(asid, vaddr, size, flags, mid, pc);
-        setThreadContext(cid, tid);
+        setContext(cid);
     }
 
     ~Request()
@@ -446,14 +443,13 @@ class Request
     }
 
     /**
-     * Set up CPU and thread numbers.
+     * Set up Context numbers.
      */
     void
-    setThreadContext(ContextID context_id, ThreadID tid)
+    setContext(ContextID context_id)
     {
         _contextId = context_id;
-        _threadId = tid;
-        privateFlags.set(VALID_CONTEXT_ID|VALID_THREAD_ID);
+        privateFlags.set(VALID_CONTEXT_ID);
     }
 
     /**
@@ -701,14 +697,6 @@ class Request
         return _contextId;
     }
 
-    /** Accessor function for thread ID. */
-    ThreadID
-    threadId() const
-    {
-        assert(privateFlags.isSet(VALID_THREAD_ID));
-        return _threadId;
-    }
-
     void
     setPC(Addr pc)
     {