Fix clock input

In Micron's DDR3 model code, the clock is delayed and recreated as diff_ck from
ck and ck_n. The clock is reconstituted by updating diff_ck on every positive edge
of ck and ck_n. Having ck_n set as 0 would mean diff_ck being equal to a constant 1.

diff --git a/gram/simulation/simsoctb.v b/gram/simulation/simsoctb.v
index f855a8b1f2d64fe4c927960987feb0302379e887..4c1cabf35a5d4d568373584fe713cbd239b2e8a8 100644 (file)
--- a/gram/simulation/simsoctb.v
+++ b/gram/simulation/simsoctb.v
@@ -51,7 +51,7 @@ module simsoctb;
   ddr3 ram_chip (
     .rst_n(1'b1),
     .ck(dram_ck),
-    .ck_n(1'b0),
+    .ck_n(~dram_ck),
     .cke(dram_cke),
     .cs_n(1'b0),
     .ras_n(dram_ras_n),