2004-06-26 Alexandre Oliva <aoliva@redhat.com>
+ 2000-08-07 Graham Stott <grahams@cygnus.co.uk>
+ * am33-2.igen (fmadd, fmsub, fmnadd, fmnsub): Correct typo.
+ 2000-05-29 Alexandre Oliva <aoliva@cygnus.com>
+ * interp.c (fpu_disabled_exception, fpu_unimp_exception,
+ fpu_check_signal_exception): Take additional state arguments.
+ Print exception type and call program_interrupt. Adjust callers.
+ (fpu_rsqrt, fpu_cmp, fpu_add, fpu_sub, fpu_mul, fpu_div,
+ fpu_fmadd, fpu_fmsub, fpu_fnmadd, fpu_fnmsub): Take additional
+ arguments.
+ * mn10300_sim.h (fpu_disabled_exception, fpu_unimp_exception,
+ fpu_check_signal_exception): Adjust prototypes.
+ (fpu_rsqrt, fpu_cmp, fpu_add, fpu_sub, fpu_mul, fpu_div,
+ fpu_fmadd, fpu_fmsub, fpu_fnmadd, fpu_fnmsub): Likewise.
+ * am33-2.igen: Adjust calls.
+ 2000-05-19 Alexandre Oliva <aoliva@cygnus.com>
+ * op_utils.c (cmp2fcc): Moved...
+ * interp.c: ... here.
+ 2000-05-18 Alexandre Oliva <aoliva@cygnus.com>
+ * am33-2.igen: Use `unsigned32', `signed32', `unsigned64' or
+ `signed64' where type width is relevant.
+ 2000-05-15 Alexandre Oliva <aoliva@cygnus.com>
+ * mn10300_sim.h: Include sim-fpu.h.
+ (FD2FPU, FPU2FD): Enclose the FD argument in parentheses.
+ (fpu_check_signal_exception): Declare.
+ (struct fp_prec_t, fp_single_prec, fp_double_prec): Likewise.
+ (FP_SINGLE, FP_DOUBLE): Shorthands for fp_*_prec.
+ (fpu_rsqrt, fpu_cmp, fpu_add, fpu_sub, fpu_mul, fpu_div,
+ fpu_fmadd, fpu_fmsub, fpu_fnmadd, fpu_fnmsub): Declare.
+ * interp.c (fpu_disabled_exception): Document.
+ (fpu_unimp_exception): Likewise.
+ (fpu_check_signal_exception): Define.
+ (reg2val_32, round_32, val2reg_32, fp_single_prec): Likewise.
+ (reg2val_64, round_64, val2reg_64, fp_double_prec): Likewise.
+ (REG2VAL, ROUND, VAL2REG): Define shorthands.
+ (fpu_status_ok): Define.
+ (fpu_rsqrt, fpu_cmp, fpu_add, fpu_sub, fpu_mul, fpu_div,
+ fpu_fmadd, fpu_fmsub, fpu_fnmadd, fpu_fnmsub): Define.
+ * am33-2.igen (frsqrt, fcmp, fadd, fsub, fmul, fdiv,
+ fmadd, fmsub, fnmadd, fnmsub): Use new functions.
+ 2000-04-27 Alexandre Oliva <aoliva@cygnus.com>
+ * interp.c (sim_create_inferior): Set PSW bit to enable FP insns
+ if architecture is AM33/2.0.
+ * am33.igen: Include am33-2.igen.
+ 2000-04-23 Alexandre Oliva <aoliva@cygnus.com>
+ * mn10300.igen (movm, call, ret, retf): Check for am33_2 too.
+ * am33.igen (movm): Likewise.
+ 2000-04-19 Alexandre Oliva <aoliva@cygnus.com>
+ * am33.igen: Added `*am33_2' to some instructions that were
+ missing it.
+ 2000-04-07 Alexandre Oliva <aoliva@cygnus.com>
+ * am33-2.igen: New file. All insns implemented, but FP flags are
+ only set for fcmp, exceptional conditions are not handled yet.
+ * Makefile.in (IGEN_INSN): Added am33-2.igen.
+ (tmp-igen): Added -M am33_2.
+ * mn10300.igen, am33.igen: Added `*am33_2' to all insns.
+ * gencode.c: Support FMT_D3.
+ * mn10300_sim.h (dword): New type.
+ (struct _state): Added fpregs.
+ (REG_FPCR, FPCR): New define. All assorted bitmaps.
+ (XS2FS, AS2FS, Xf2FD): New macros.
+ (FS2FPU, FD2FPU, FPU2FS, FPU2FD): Likewise.
+ (load_dword, store_dword): New functions or macros.
+ (u642dw, dw2u64): New functions.
+ (fpu_disabled_exception, fpu_unimp_exception): Declared.
+ * interp.c (fpu_disabled_exception): Defined; no actual
+ implementation.
+ (fpu_unimp_exception): Likewise.
+ * op_utils.c (cmp2fcc): New function.
+
* interp.c, mn10300_sim.h, op_utils.c: Convert function prototypes
and definitions to ISO C.
cd ../igen && $(MAKE)
IGEN_TRACE= # -G omit-line-numbers # -G trace-rule-selection -G trace-rule-rejection -G trace-entries
-IGEN_INSN=$(srcdir)/mn10300.igen $(srcdir)/am33.igen
+IGEN_INSN=$(srcdir)/mn10300.igen $(srcdir)/am33.igen $(srcdir)/am33-2.igen
IGEN_DC=$(srcdir)/mn10300.dc
tmp-igen: $(IGEN_INSN) $(IGEN_DC) ../igen/igen
cd ../igen && $(MAKE)
$(IGEN_TRACE) \
-G gen-direct-access \
-M mn10300,am33 -G gen-multi-sim=am33 \
+ -M am33_2 \
-I $(srcdir) \
-i $(IGEN_INSN) \
-o $(IGEN_DC) \
--- /dev/null
+// data cache pre-fetch:
+
+// 1111 1001 1010 0110 Rm.. 0000; dcpf (Rm)
+8.0xf9+8.0xa6+4.RN2,4.0000:D1a:::dcpf
+"dcpf"
+*am33_2
+{
+ int srcreg;
+
+ PC = cia;
+
+ srcreg = translate_rreg (SD_, RN2);
+ load_word (State.regs[srcreg]);
+}
+
+// 1111 1001 1010 0111 0000 0000; dcpf (sp)
+8.0xf9+8.0xa7+8.0x00:D1b:::dcpf
+"dcpf"
+*am33_2
+{
+ PC = cia;
+
+ load_word (SP);
+}
+
+// 1111 1011 1010 0110 Ri.. Rm.. 0000 0000; dcpf (Ri,Rm)
+8.0xfb+8.0xa6+4.RN2,4.RN0+8.0x00:D2a:::dcpf
+"dcpf"
+*am33_2
+{
+ int srci, srcm;
+
+ PC = cia;
+
+ srci = translate_rreg (SD_, RN2);
+ srcm = translate_rreg (SD_, RN0);
+
+ load_word (State.regs[srci] + State.regs[srcm]);
+}
+
+// 1111 1011 1010 0111 Rm.. 0000 IMM8; dcpf (d8,Rm)
+8.0xfb+8.0xa7+4.RN2,4.0000+8.IMM8:D2b:::dcpf
+"dcpf"
+*am33_2
+{
+ int srcreg;
+
+ PC = cia;
+
+ srcreg = translate_rreg (SD_, RN2);
+
+ load_word (State.regs[srcreg] + EXTEND8 (IMM8));
+}
+
+// 1111 1101 1010 0111 Rm.. 0000 IMM24; dcpf (d24,Rm)
+8.0xfd+8.0xa7+4.RN2,4.0000+8.IMM24A+8.IMM24B+8.IMM24C:D4a:::dcpf
+"dcpf"
+*am33_2
+{
+ int srcreg;
+
+ PC = cia;
+
+ srcreg = translate_rreg (SD_, RN2);
+
+ load_word (State.regs[srcreg] + EXTEND24 (FETCH24 (IMM24A,
+ IMM24B, IMM24C)));
+}
+
+// 1111 1110 0100 0110 Rm.. 0000 IMM32; dcpf (d32,Rm)
+8.0xfe+8.0x46+4.RN2,4.0000+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5a:::dcpf
+"dcpf"
+*am33_2
+{
+ int srcreg;
+
+ PC = cia;
+
+ srcreg = translate_rreg (SD_, RN2);
+
+ load_word (State.regs[srcreg]
+ + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
+}
+
+// bit operations with imm8,(abs16) addressing mode:
+
+// 1111 1110 1000 0010 ABS16 IMM8; btst imm8,(abs16)
+8.0xfe+8.0x82+8.IMM16A+8.IMM16B+8.IMM8:D3:::btst
+"btst"
+*am33_2
+{
+ PC = cia;
+ genericBtst (IMM8, FETCH16 (IMM16A, IMM16B));
+}
+
+// 1111 1110 1000 0000 ABS16 IMM8; bset imm8,(abs16)
+8.0xfe+8.0x80+8.IMM16A+8.IMM16B+8.IMM8:D3:::bset
+"bset"
+*am33_2
+{
+ unsigned32 temp;
+ int z;
+
+ PC = cia;
+ temp = load_byte (FETCH16 (IMM16A, IMM16B));
+ z = (temp & IMM8) == 0;
+ temp |= IMM8;
+ store_byte (FETCH16 (IMM16A, IMM16B), temp);
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= (z ? PSW_Z : 0);
+}
+
+// 1111 1110 1000 0001 ABS16 IMM8; bclr imm8,(abs16)
+8.0xfe+8.0x81+8.IMM16A+8.IMM16B+8.IMM8:D3:::bclr
+"bclr"
+*am33_2
+{
+ unsigned32 temp;
+ int z;
+
+ PC = cia;
+ temp = load_byte (FETCH16 (IMM16A, IMM16B));
+ z = (temp & IMM8) == 0;
+ temp = temp & ~(IMM8);
+ store_byte (FETCH16 (IMM16A, IMM16B), temp);
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= (z ? PSW_Z : 0);
+}
+
+// single precision fmov:
+
+// 1111 1001 0010 000X Rm.. Sn..; fmov (Rm),FSn
+8.0xf9+4.2,3.0,1.X+4.Rm,4.Sn:D1a:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ XS2FS (X,Sn) = load_word (State.regs[reg]);
+ }
+}
+
+// 1111 1001 0010 001X Rm.. Sn..; fmov (Rm+),FSn
+8.0xf9+4.2,3.1,1.X+4.Rm,4.Sn:D1b:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ XS2FS (X,Sn) = load_word (State.regs[reg]);
+ State.regs[reg] += 4;
+ }
+}
+
+// 1111 1001 0010 010X ---- Sn..; fmov (SP),FSn
+8.0xf9+4.2,3.2,1.X+4.0,4.Sn:D1c:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = REG_SP;
+ XS2FS (X,Sn) = load_word (State.regs[reg]);
+ }
+}
+
+// 1111 1001 0010 011X Rm.. Sn..; fmov Rm,FSn
+8.0xf9+4.2,3.3,1.X+4.Rm,4.Sn:D1d:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ XS2FS (X,Sn) = State.regs[reg];
+ }
+}
+
+// 1111 1001 0011 00Y0 Sm.. Rn..; fmov FSm,(Rn)
+8.0xf9+4.3,2.0,1.Y,1.0+4.Sm,4.Rn:D1e:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ store_word (State.regs[reg], XS2FS (Y,Sm));
+ }
+}
+
+// 1111 1001 0011 00Y1 Sm.. Rn..; fmov FSm,(Rn+)
+8.0xf9+4.3,2.0,1.Y,1.1+4.Sm,4.Rn:D1f:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ store_word (State.regs[reg], XS2FS (Y,Sm));
+ State.regs[reg] += 4;
+ }
+}
+
+// 1111 1001 0011 01Y0 Sm.. ----; fmov FSm,(SP)
+8.0xf9+4.3,2.1,1.Y,1.0+4.Sm,4.0:D1g:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = REG_SP;
+ store_word (State.regs[reg], XS2FS (Y,Sm));
+ }
+}
+
+// 1111 1001 0011 01Y1 Sm.. Rn..; fmov FSm,Rn
+8.0xf9+4.3,2.1,1.Y,1.1+4.Sm,4.Rn:D1h:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ State.regs[reg] = XS2FS (Y,Sm);
+ }
+}
+
+// 1111 1001 0100 00YX Sm.. Sn..; fmov FSm,FSn
+8.0xf9+4.4,2.0,1.Y,1.X+4.Sm,4.Sn:D1i:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ XS2FS (X,Sn) = XS2FS (Y,Sm);
+}
+
+// 1111 1011 0010 000X Rm.. Sn.. d8; fmov (d8,Rm),FSn
+8.0xfb+4.2,3.0,1.X+4.Rm,4.Sn+8.IMM8:D2a:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ XS2FS (X, Sn) = load_word (State.regs[reg] + EXTEND8 (IMM8));
+ }
+}
+
+// 1111 1011 0010 001X Rm.. Sn.. d8; fmov (Rm+,imm8),FSn
+8.0xfb+4.2,3.1,1.X+4.Rm,4.Sn+8.IMM8:D2b:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ XS2FS (X, Sn) = load_word (State.regs[reg] + EXTEND8 (IMM8));
+ State.regs[reg] += 4;
+ }
+}
+
+// 1111 1011 0010 010X ---- Sn.. d8; fmov (d8,SP),FSn
+8.0xfb+4.2,3.2,1.X+4.0,4.Sn+8.IMM8:D2c:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = REG_SP;
+ XS2FS (X, Sn) = load_word (State.regs[reg] + IMM8);
+ }
+}
+
+// 1111 1011 0010 0111 Ri.. Rm.. Sn.. --Z-; fmov (Ri,Rm),FSn
+8.0xfb+8.0x27+4.Ri,4.Rm+4.Sn,2.0,1.Z,1.0:D2d:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int ri = translate_rreg (SD_, Ri);
+ int rm = translate_rreg (SD_, Rm);
+ XS2FS (Z, Sn) = load_word (State.regs[ri] + State.regs[rm]);
+ }
+}
+
+// 1111 1011 0011 00Y0 Sm.. Rn.. d8; fmov FSm,(d8,Rn)
+8.0xfb+4.3,2.0,1.Y,1.0+4.Sm,4.Rn+8.IMM8:D2e:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ store_word (State.regs[reg] + EXTEND8 (IMM8), XS2FS (Y, Sm));
+ }
+}
+
+// 1111 1011 0011 00Y1 Sm.. Rn.. d8; fmov FSm,(Rn+,d8)
+8.0xfb+4.3,2.0,1.Y,1.1+4.Sm,4.Rn+8.IMM8:D2f:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ store_word (State.regs[reg] + EXTEND8 (IMM8), XS2FS (Y, Sm));
+ State.regs[reg] += 4;
+ }
+}
+
+// 1111 1011 0011 01Y0 Sm.. ---- d8; fmov FSm,(d8,SP)
+8.0xfb+4.3,2.1,1.Y,1.0+4.Sm,4.0+8.IMM8:D2g:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = REG_SP;
+ store_word (State.regs[reg] + IMM8, XS2FS (Y, Sm));
+ }
+}
+
+// 1111 1011 0011 0111 Ri.. Rm.. Sm.. --Z-; fmov FSm,(Ri,Rm)
+8.0xfb+8.0x37+4.Ri,4.Rm+4.Sm,2.0,1.Z,1.0:D2h:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int ri = translate_rreg (SD_, Ri);
+ int rm = translate_rreg (SD_, Rm);
+ store_word (State.regs[ri] + State.regs[rm], XS2FS (Z, Sm));
+ }
+}
+
+// 1111 1101 0010 000X Rm.. Sn.. d24; fmov (d24,Rm),FSn
+8.0xfd+4.2,3.0,1.X+4.Rm,4.Sn+8.IMM24A+8.IMM24B+8.IMM24C:D4a:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ XS2FS (X, Sn) = load_word (State.regs[reg]
+ + EXTEND24 (FETCH24 (IMM24A,
+ IMM24B, IMM24C)));
+ }
+}
+
+// 1111 1101 0010 001X Rm.. Sn.. d24; fmov (Rm+,imm24),FSn
+8.0xfd+4.2,3.1,1.X+4.Rm,4.Sn+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ XS2FS (X, Sn) = load_word (State.regs[reg]
+ + EXTEND24 (FETCH24 (IMM24A,
+ IMM24B, IMM24C)));
+ State.regs[reg] += 4;
+ }
+}
+
+// 1111 1101 0010 010X ---- Sn.. d24; fmov (d24,SP),FSn
+8.0xfd+4.2,3.2,1.X+4.0,4.Sn+8.IMM24A+8.IMM24B+8.IMM24C:D4c:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = REG_SP;
+ XS2FS (X, Sn) = load_word (State.regs[reg] + FETCH24 (IMM24A,
+ IMM24B, IMM24C));
+ }
+}
+
+// 1111 1101 0011 00Y0 Sm.. Rn.. d24; fmov FSm,(d24,Rn)
+8.0xfd+4.3,2.0,1.Y,1.0+4.Sm,4.Rn+8.IMM24A+8.IMM24B+8.IMM24C:D4e:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ store_word (State.regs[reg]
+ + EXTEND24 (FETCH24 (IMM24A,
+ IMM24B, IMM24C)), XS2FS (Y, Sm));
+ }
+}
+
+// 1111 1101 0011 00Y1 Sm.. Rn.. d24; fmov FSm,(Rn+,d24)
+8.0xfd+4.3,2.0,1.Y,1.1+4.Sm,4.Rn+8.IMM24A+8.IMM24B+8.IMM24C:D4f:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ store_word (State.regs[reg]
+ + EXTEND24 (FETCH24 (IMM24A,
+ IMM24B, IMM24C)), XS2FS (Y, Sm));
+ State.regs[reg] += 4;
+ }
+}
+
+// 1111 1101 0011 01Y0 Sm.. ---- d24; fmov FSm,(d24,SP)
+8.0xfd+4.3,2.1,1.Y,1.0+4.Sm,4.0+8.IMM24A+8.IMM24B+8.IMM24C:D4g:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = REG_SP;
+ store_word (State.regs[reg]
+ + FETCH24 (IMM24A,
+ IMM24B, IMM24C), XS2FS (Y, Sm));
+ }
+}
+
+// 1111 1110 0010 000X Rm.. Sn.. d32; fmov (d32,Rm),FSn
+8.0xfe+4.2,3.0,1.X+4.Rm,4.Sn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5a:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ XS2FS (X, Sn) = load_word (State.regs[reg]
+ + EXTEND32 (FETCH32 (IMM32A, IMM32B,
+ IMM32C, IMM32D)));
+ }
+}
+
+// 1111 1110 0010 001X Rm.. Sn.. d32; fmov (Rm+,imm32),FSn
+8.0xfe+4.2,3.1,1.X+4.Rm,4.Sn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ XS2FS (X, Sn) = load_word (State.regs[reg]
+ + EXTEND32 (FETCH32 (IMM32A, IMM32B,
+ IMM32C, IMM32D)));
+ State.regs[reg] += 4;
+ }
+}
+
+// 1111 1110 0010 010X ---- Sn.. d32; fmov (d32,SP),FSn
+8.0xfe+4.2,3.2,1.X+4.0,4.Sn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = REG_SP;
+ XS2FS (X, Sn) = load_word (State.regs[reg]
+ + FETCH32 (IMM32A, IMM32B,
+ IMM32C, IMM32D));
+ }
+}
+
+// 1111 1110 0010 011X ---- Sn.. d32; fmov imm32,FSn
+8.0xfe+4.2,3.3,1.X+4.0,4.Sn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ XS2FS (X, Sn) = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+}
+
+// 1111 1110 0011 00Y0 Sm.. Rn.. d32; fmov FSm,(d32,Rn)
+8.0xfe+4.3,2.0,1.Y,1.0+4.Sm,4.Rn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ store_word (State.regs[reg]
+ + EXTEND32 (FETCH32 (IMM32A, IMM32B,
+ IMM32C, IMM32D)), XS2FS (Y, Sm));
+ }
+}
+
+// 1111 1110 0011 00Y1 Sm.. Rn.. d32; fmov FSm,(Rn+,d32)
+8.0xfe+4.3,2.0,1.Y,1.1+4.Sm,4.Rn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ store_word (State.regs[reg]
+ + EXTEND32 (FETCH32 (IMM32A, IMM32B,
+ IMM32C, IMM32D)), XS2FS (Y, Sm));
+ State.regs[reg] += 4;
+ }
+}
+
+// 1111 1110 0011 01Y0 Sm.. ---- d32; fmov FSm,(d32,SP)
+8.0xfe+4.3,2.1,1.Y,1.0+4.Sm,4.0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5g:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = REG_SP;
+ store_word (State.regs[reg]
+ + FETCH32 (IMM32A, IMM32B,
+ IMM32C, IMM32D), XS2FS (Y, Sm));
+ }
+}
+
+// double precision fmov:
+
+// 1111 1001 1010 000X Rm.. fn.-; fmov (Rm),FDn
+8.0xf9+4.0xa,3.0,1.X+4.Rm,3.fn,1.0:D1j:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ Xf2FD (X,fn) = load_dword (State.regs[reg]);
+ }
+}
+
+// 1111 1001 1010 001X Rm.. fn.-; fmov (Rm+),FDn
+8.0xf9+4.0xa,3.1,1.X+4.Rm,3.fn,1.0:D1k:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ Xf2FD (X,fn) = load_dword (State.regs[reg]);
+ State.regs[reg] += 8;
+ }
+}
+
+// 1111 1001 1010 010X ---- fn.-; fmov (SP),FDn
+8.0xf9+4.0xa,3.2,1.X+4.0,3.fn,1.0:D1l:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = REG_SP;
+ Xf2FD (X,fn) = load_dword (State.regs[reg]);
+ }
+}
+
+// 1111 1001 1011 00Y0 fm.- Rn..; fmov FDm,(Rn)
+8.0xf9+4.0xb,2.0,1.Y,1.0+3.fm,1.0,4.Rn:D1m:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ store_dword (State.regs[reg], Xf2FD (Y,fm));
+ }
+}
+
+// 1111 1001 1011 00Y1 fm.- Rn..; fmov FDm,(Rn+)
+8.0xf9+4.0xb,2.0,1.Y,1.1+3.fm,1.0,4.Rn:D1n:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ store_dword (State.regs[reg], Xf2FD (Y,fm));
+ State.regs[reg] += 8;
+ }
+}
+
+// 1111 1001 1011 01Y0 fm.- ----; fmov FDm,(SP)
+8.0xf9+4.0xb,2.1,1.Y,1.0+3.fm,1.0,4.0:D1o:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = REG_SP;
+ store_dword (State.regs[reg], Xf2FD (Y,fm));
+ }
+}
+
+// 1111 1001 1100 00YX fm.- fn.-; fmov FDm,FDn
+8.0xf9+4.0xc,2.0,1.Y,1.X+3.fm,1.0,3.fn,1.0:D1p:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1011 0100 0111 Ri.. Rm.. fn.- --Z-; fmov (Ri,Rm),FDn
+8.0xfb+8.0x47+4.Ri,4.Rm+3.fn,1.0,2.0,1.Z,1.0:D2i:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int ri = translate_rreg (SD_, Ri);
+ int rm = translate_rreg (SD_, Rm);
+ Xf2FD (Z,fn) = load_dword (State.regs[ri] + State.regs[rm]);
+ }
+}
+
+// 1111 1011 0101 0111 Ri.. Rn.. fm.- --Z-; fmov FDm,(Ri,Rn)
+8.0xfb+8.0x57+4.Ri,4.Rn+3.fm,1.0,2.0,1.Z,1.0:D2j:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int ri = translate_rreg (SD_, Ri);
+ int rn = translate_rreg (SD_, Rn);
+ store_dword (State.regs[ri] + State.regs[rn], Xf2FD (Z,fm));
+ }
+}
+
+// 1111 1011 1010 000X Rm.. fn.- d8; fmov (d8,Rm),FDn
+8.0xfb+4.0xa,3.0,1.X+4.Rm,4.fn+8.IMM8:D2k:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ Xf2FD (X, fn) = load_dword (State.regs[reg] + EXTEND8 (IMM8));
+ }
+}
+
+// 1111 1011 1010 001X Rm.. fn.- d8; fmov (Rm+,imm8),FDn
+8.0xfb+4.0xa,3.1,1.X+4.Rm,4.fn+8.IMM8:D2l:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ Xf2FD (X, fn) = load_dword (State.regs[reg] + EXTEND8 (IMM8));
+ State.regs[reg] += 8;
+ }
+}
+
+// 1111 1011 1010 010X ---- fn.- d8; fmov (d8,SP),FDn
+8.0xfb+4.0xa,3.2,1.X+4.0,4.fn+8.IMM8:D2m:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = REG_SP;
+ Xf2FD (X, fn) = load_dword (State.regs[reg] + IMM8);
+ }
+}
+
+// 1111 1011 1011 00Y0 fm.- Rn.. d8; fmov FDm,(d8,Rn)
+8.0xfb+4.0xb,2.0,1.Y,1.0+4.fm,4.Rn+8.IMM8:D2n:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ store_dword (State.regs[reg] + EXTEND8 (IMM8), Xf2FD (Y, fm));
+ }
+}
+
+// 1111 1011 1011 00Y1 fm.- Rn.. d8; fmov FDm,(Rn+,d8)
+8.0xfb+4.0xb,2.0,1.Y,1.1+4.fm,4.Rn+8.IMM8:D2o:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ store_dword (State.regs[reg] + EXTEND8 (IMM8), Xf2FD (Y, fm));
+ State.regs[reg] += 8;
+ }
+}
+
+// 1111 1011 1011 01Y0 fm.- ---- d8; fmov FDm,(d8,SP)
+8.0xfb+4.0xb,2.1,1.Y,1.0+4.fm,4.0+8.IMM8:D2p:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = REG_SP;
+ store_dword (State.regs[reg] + IMM8, Xf2FD (Y, fm));
+ }
+}
+
+// 1111 1101 1010 000X Rm.. fn.- d24; fmov (d24,Rm),FDn
+8.0xfd+4.0xa,3.0,1.X+4.Rm,4.fn+8.IMM24A+8.IMM24B+8.IMM24C:D4k:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ Xf2FD (X, fn) = load_dword (State.regs[reg]
+ + EXTEND24 (FETCH24 (IMM24A,
+ IMM24B, IMM24C)));
+ }
+}
+
+// 1111 1101 1010 001X Rm.. fn.- d24; fmov (Rm+,imm24),FDn
+8.0xfd+4.0xa,3.1,1.X+4.Rm,4.fn+8.IMM24A+8.IMM24B+8.IMM24C:D4l:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ Xf2FD (X, fn) = load_dword (State.regs[reg]
+ + EXTEND24 (FETCH24 (IMM24A,
+ IMM24B, IMM24C)));
+ State.regs[reg] += 8;
+ }
+}
+
+// 1111 1101 1010 010X ---- fn.- d24; fmov (d24,SP),FDn
+8.0xfd+4.0xa,3.2,1.X+4.0,4.fn+8.IMM24A+8.IMM24B+8.IMM24C:D4m:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = REG_SP;
+ Xf2FD (X, fn) = load_dword (State.regs[reg]
+ + FETCH24 (IMM24A,
+ IMM24B, IMM24C));
+ }
+}
+
+// 1111 1101 1011 00Y0 fm.- Rn.. d24; fmov FDm,(d24,Rn)
+8.0xfd+4.0xb,2.0,1.Y,1.0+4.fm,4.Rn+8.IMM24A+8.IMM24B+8.IMM24C:D4n:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ store_dword (State.regs[reg]
+ + EXTEND24 (FETCH24 (IMM24A,
+ IMM24B, IMM24C)), Xf2FD (Y, fm));
+ }
+}
+
+// 1111 1101 1011 00Y1 fm.- Rn.. d24; fmov FDm,(Rn+,d24)
+8.0xfd+4.0xb,2.0,1.Y,1.1+4.fm,4.Rn+8.IMM24A+8.IMM24B+8.IMM24C:D4o:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ store_dword (State.regs[reg]
+ + EXTEND24 (FETCH24 (IMM24A,
+ IMM24B, IMM24C)), Xf2FD (Y, fm));
+ State.regs[reg] += 8;
+ }
+}
+
+// 1111 1101 1011 01Y0 fm.- ---- d24; fmov FDm,(d24,SP)
+8.0xfd+4.0xb,2.1,1.Y,1.0+4.fm,4.0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = REG_SP;
+ store_dword (State.regs[reg] + FETCH24 (IMM24A,
+ IMM24B, IMM24C), Xf2FD (Y, fm));
+ }
+}
+
+// 1111 1110 1010 000X Rm.. fn.- d32; fmov (d32,Rm),FDn
+8.0xfe+4.0xa,3.0,1.X+4.Rm,4.fn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5k:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ Xf2FD (X, fn) = load_dword (State.regs[reg]
+ + EXTEND32 (FETCH32 (IMM32A, IMM32B,
+ IMM32C, IMM32D)));
+ }
+}
+
+// 1111 1110 1010 001X Rm.. fn.- d32; fmov (Rm+,imm32),FDn
+8.0xfe+4.0xa,3.1,1.X+4.Rm,4.fn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5l:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ Xf2FD (X, fn) = load_dword (State.regs[reg]
+ + EXTEND32 (FETCH32 (IMM32A, IMM32B,
+ IMM32C, IMM32D)));
+ State.regs[reg] += 8;
+ }
+}
+
+// 1111 1110 1010 010X ---- fn.- d32; fmov (d32,SP),FDn
+8.0xfe+4.0xa,3.2,1.X+4.0,4.fn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5m:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = REG_SP;
+ Xf2FD (X, fn) = load_dword (State.regs[reg]
+ + FETCH32 (IMM32A, IMM32B,
+ IMM32C, IMM32D));
+ }
+}
+
+// 1111 1110 1011 00Y0 fm.- Rn.. d32; fmov FDm,(d32,Rn)
+8.0xfe+4.0xb,2.0,1.Y,1.0+4.fm,4.Rn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5n:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ store_dword (State.regs[reg]
+ + EXTEND32 (FETCH32 (IMM32A, IMM32B,
+ IMM32C, IMM32D)), Xf2FD (Y, fm));
+ }
+}
+
+// 1111 1110 1011 00Y1 fm.- Rn.. d32; fmov FDm,(Rn+,d32)
+8.0xfe+4.0xb,2.0,1.Y,1.1+4.fm,4.Rn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5o:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ store_dword (State.regs[reg]
+ + EXTEND32 (FETCH32 (IMM32A, IMM32B,
+ IMM32C, IMM32D)), Xf2FD (Y, fm));
+ State.regs[reg] += 8;
+ }
+}
+
+// 1111 1110 1011 01Y0 fm.- ---- d32; fmov FDm,(d32,SP)
+8.0xfe+4.0xb,2.1,1.Y,1.0+4.fm,4.0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5p:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = REG_SP;
+ store_dword (State.regs[reg]
+ + FETCH32 (IMM32A, IMM32B,
+ IMM32C, IMM32D), Xf2FD (Y, fm));
+ }
+}
+
+// FPCR fmov:
+
+// 1111 1001 1011 0101 Rm.. ----; fmov Rm,FPCR
+8.0xf9+8.0xb5+4.Rm,4.0:D1q:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ unsigned32 val = State.regs[reg];
+ FPCR = (val & (EC_MASK | EE_MASK | FCC_MASK))
+ | ((FPCR & ~val) & EF_MASK);
+ }
+}
+
+// 1111 1001 1011 0111 ---- Rn..; fmov FPCR,Rn
+8.0xf9+8.0xb7+4.0,4.Rn:D1r:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ State.regs[reg] = FPCR & FPCR_MASK;
+ }
+}
+
+// 1111 1101 1011 0101 imm32; fmov imm32,FPCR
+8.0xfd+8.0xb5+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ unsigned32 val = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+ FPCR = (val & (EC_MASK | EE_MASK | FCC_MASK))
+ | ((FPCR & ~val) & EF_MASK);
+ }
+}
+
+// fabs:
+
+// 1111 1001 0100 010X ---- Sn..; fabs FSn
+8.0xf9+4.4,3.2,1.X+4.0,4.Sn:D1a:::fabs
+"fabs"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ sim_fpu in, out;
+
+ FS2FPU (XS2FS (X,Sn), in);
+ sim_fpu_abs (&out, &in);
+ FPU2FS (out, XS2FS (X,Sn));
+ }
+}
+
+// 1111 1001 1100 010X ---- Sn..; fabs FDn
+8.0xf9+4.0xc,3.2,1.X+4.0,3.fn,1.0:D1b:::fabs
+"fabs"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1011 0100 0100 Sm.. ---- Sn.. X-Z-; fabs FSm,FSn
+8.0xfb+8.0x44+4.Sm,4.0+4.Sn,1.X,1.0,1.Z,1.0:D2a:::fabs
+"fabs"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ sim_fpu in, out;
+
+ FS2FPU (XS2FS (X,Sm), in);
+ sim_fpu_abs (&out, &in);
+ FPU2FS (out, XS2FS (Z,Sn));
+ }
+}
+
+// 1111 1011 1100 0100 fm.- ---- fn.- X-Z-; fabs FDm,FDn
+8.0xfb+8.0xc4+3.fm,1.0,4.0+3.fn,1.0,1.X,1.0,1.Z,1.0:D2b:::fabs
+"fabs"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1001 0100 011X ---- Sn..; fneg FSn
+8.0xf9+4.4,3.3,1.X+4.0,4.Sn:D1a:::fneg
+"fneg"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ sim_fpu in, out;
+
+ FS2FPU (XS2FS (X,Sn), in);
+ sim_fpu_neg (&out, &in);
+ FPU2FS (out, XS2FS (X,Sn));
+ }
+}
+
+// 1111 1001 1100 011X ---- Sn..; fneg FDn
+8.0xf9+4.0xc,3.3,1.X+4.0,3.fn,1.0:D1b:::fneg
+"fneg"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1011 0100 0110 Sm.. ---- Sn.. X-Z-; fneg FSm,FSn
+8.0xfb+8.0x46+4.Sm,4.0+4.Sn,1.X,1.0,1.Z,1.0:D2a:::fneg
+"fneg"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ sim_fpu in, out;
+
+ FS2FPU (XS2FS (X,Sm), in);
+ sim_fpu_neg (&out, &in);
+ FPU2FS (out, XS2FS (Z,Sn));
+ }
+}
+
+// 1111 1011 1100 0110 fm.- ---- fn.- X-Z-; fneg FDm,FDn
+8.0xfb+8.0xc6+3.fm,1.0,4.0+3.fn,1.0,1.X,1.0,1.Z,1.0:D2b:::fneg
+"fneg"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1001 0101 000X ---- Sn..; frsqrt FSn
+8.0xf9+4.5,3.0,1.X+4.0,4.Sn:D1a:::frsqrt
+"frsqrt"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_rsqrt (SD, CPU, cia, &XS2FS (X,Sn), &XS2FS (X,Sn), FP_SINGLE);
+}
+
+// 1111 1001 1101 000X ---- fn.-; frsqrt FDn
+8.0xf9+4.0xd,3.0,1.X+4.0,3.fn,1.0:D1b:::frsqrt
+"frsqrt"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1011 0101 0000 Sm.. ---- Sn.. X-Z-; frsqrt FSm,FSn
+8.0xfb+8.0x50+4.Sm,4.0+4.Sn,1.X,1.0,1.Z,1.0:D2a:::frsqrt
+"frsqrt"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_rsqrt (SD, CPU, cia, &XS2FS (X,Sm), &XS2FS (Z,Sn), FP_SINGLE);
+}
+
+// 1111 1011 1101 0000 fm.- ---- fn.- X-Z-; frsqrt FDm,FDn
+8.0xfb+8.0xd0+3.fm,1.0,4.0+3.fn,1.0,1.X,1.0,1.Z,1.0:D2b:::frsqrt
+"frsqrt"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1001 0101 001X ---- Sn..; fsqrt FSn
+8.0xf9+4.5,3.1,1.X+4.0,4.Sn:D1a:::fsqrt
+"fsqrt"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1001 1101 001X ---- fn.-; fsqrt FDn
+8.0xf9+4.0xd,3.1,1.X+4.0,3.fn,1.0:D1b:::fsqrt
+"fsqrt"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1011 0101 0100 Sm.. ---- Sn.. X-Z-; fsqrt FSm,FSn
+8.0xfb+8.0x54+4.Sm,4.0+4.Sn,1.X,1.0,1.Z,1.0:D2a:::fsqrt
+"fsqrt"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1011 1101 0100 fm.- ---- fn.- X-Z-; fsqrt FDm,FDn
+8.0xfb+8.0xd4+3.fm,1.0,4.0+3.fn,1.0,1.X,1.0,1.Z,1.0:D2b:::fsqrt
+"fsqrt"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1001 0101 01YX Sm.. Sn..; fcmp FSm, FSn
+8.0xf9+4.5,2.1,1.Y,1.X+4.Sm,4.Sn:D1a:::fcmp
+"fcmp"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_cmp (SD, CPU, cia, &XS2FS (X,Sn), &XS2FS (Y,Sm), FP_SINGLE);
+}
+
+// 1111 1001 1101 01YX fm.- fn.-; fcmp FDm, FDn
+8.0xf9+4.0xd,2.1,1.Y,1.X+3.fm,1.0,3.fn,1.0:D1b:::fcmp
+"fcmp"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1110 0011 01Y1 Sm.. ---- IMM32; fcmp imm32, FSm
+8.0xfe+4.3,2.1,1.Y,1.1+4.Sm,4.0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::fcmp
+"fcmp"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ uint32 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+ fpu_cmp (SD, CPU, cia, &XS2FS (Y,Sm), &imm, FP_SINGLE);
+ }
+}
+
+// 1111 1001 0110 00YX Sm.. Sn..; fadd FSm, FSn
+8.0xf9+4.6,2.0,1.Y,1.X+4.Sm,4.Sn:D1a:::fadd
+"fadd"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_add (SD, CPU, cia,
+ &XS2FS (Y,Sm), &XS2FS (X,Sn), &XS2FS (X,Sn), FP_SINGLE);
+}
+
+// 1111 1001 1110 00YX fm.- fn.-; fadd FDm, FDn
+8.0xf9+4.0xe,2.0,1.Y,1.X+3.fm,1.0,3.fn,1.0:D1b:::fadd
+"fadd"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1011 0110 0000 Sm1. Sm2. Sn.. XYZ-; fadd FSm1, FSm2, FSn
+8.0xfb+8.0x60+4.Sm1,4.Sm2+4.Sn,1.X,1.Y,1.Z,1.0:D2a:::fadd
+"fadd"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_add (SD, CPU, cia,
+ &XS2FS (X,Sm1), &XS2FS (Y,Sm2), &XS2FS (Z,Sn), FP_SINGLE);
+}
+
+// 1111 1011 1110 0000 fm1- fm2- fn.- XYZ-; fadd FDm1, FDm2, FDn
+8.0xfb+8.0xe0+3.fm1,1.0,3.fm2,1.0+3.fn,1.0,1.X,1.Y,1.Z,1.0:D2b:::fadd
+"fadd"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+
+// 1111 1110 0110 00YX Sm.. Sn.. IMM32; fadd imm32, FSm, FSn
+8.0xfe+4.6,2.0,1.Y,1.X+4.Sm,4.Sn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::fadd
+"fadd"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ uint32 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+ fpu_add (SD, CPU, cia,
+ &XS2FS (Y,Sm), &imm, &XS2FS (X,Sn), FP_SINGLE);
+ }
+}
+
+// 1111 1001 0110 01YX Sm.. Sn..; fsub FSm, FSn
+8.0xf9+4.6,2.1,1.Y,1.X+4.Sm,4.Sn:D1a:::fsub
+"fsub"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_sub (SD, CPU, cia,
+ &XS2FS (X,Sn), &XS2FS (Y,Sm), &XS2FS (X,Sn), FP_SINGLE);
+}
+
+// 1111 1001 1110 01YX fm.- fn.-; fsub FDm, FDn
+8.0xf9+4.0xe,2.1,1.Y,1.X+3.fm,1.0,3.fn,1.0:D1b:::fsub
+"fsub"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1011 0110 0100 Sm1. Sm2. Sn.. XYZ-; fsub FSm1, FSm2, FSn
+8.0xfb+8.0x64+4.Sm1,4.Sm2+4.Sn,1.X,1.Y,1.Z,1.0:D2a:::fsub
+"fsub"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_sub (SD, CPU, cia,
+ &XS2FS (Y,Sm2), &XS2FS (X,Sm1), &XS2FS (Z,Sn), FP_SINGLE);
+}
+
+// 1111 1011 1110 0100 fm1- fm2- fn.- XYZ-; fsub FDm1, FDm2, FDn
+8.0xfb+8.0xe4+3.fm1,1.0,3.fm2,1.0+3.fn,1.0,1.X,1.Y,1.Z,1.0:D2b:::fsub
+"fsub"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+
+// 1111 1110 0110 01YX Sm.. Sn.. IMM32; fsub imm32, FSm, FSn
+8.0xfe+4.6,2.1,1.Y,1.X+4.Sm,4.Sn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::fsub
+"fsub"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ uint32 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+ fpu_sub (SD, CPU, cia,
+ &XS2FS (Y,Sm), &imm, &XS2FS (X,Sn), FP_SINGLE);
+ }
+}
+
+// 1111 1001 0111 00YX Sm.. Sn..; fmul FSm, FSn
+8.0xf9+4.7,2.0,1.Y,1.X+4.Sm,4.Sn:D1a:::fmul
+"fmul"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_mul (SD, CPU, cia,
+ &XS2FS (Y,Sm), &XS2FS (X,Sn), &XS2FS (X,Sn), FP_SINGLE);
+}
+
+// 1111 1001 1111 00YX fm.- fn.-; fmul FDm, FDn
+8.0xf9+4.0xf,2.0,1.Y,1.X+3.fm,1.0,3.fn,1.0:D1b:::fmul
+"fmul"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1011 0111 0000 Sm1. Sm2. Sn.. XYZ-; fmul FSm1, FSm2, FSn
+8.0xfb+8.0x70+4.Sm1,4.Sm2+4.Sn,1.X,1.Y,1.Z,1.0:D2a:::fmul
+"fmul"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_mul (SD, CPU, cia,
+ &XS2FS (X,Sm1), &XS2FS (Y,Sm2), &XS2FS (Z,Sn), FP_SINGLE);
+}
+
+// 1111 1011 1111 0000 fm1- fm2- fn.- XYZ-; fmul FDm1, FDm2, FDn
+8.0xfb+8.0xf0+3.fm1,1.0,3.fm2,1.0+3.fn,1.0,1.X,1.Y,1.Z,1.0:D2b:::fmul
+"fmul"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+
+// 1111 1110 0111 00YX Sm.. Sn.. IMM32; fmul imm32, FSm, FSn
+8.0xfe+4.7,2.0,1.Y,1.X+4.Sm,4.Sn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::fmul
+"fmul"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ uint32 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+ fpu_mul (SD, CPU, cia,
+ &imm, &XS2FS (Y,Sm), &XS2FS (X,Sn), FP_SINGLE);
+ }
+}
+
+// 1111 1001 0111 01YX Sm.. Sn..; fdiv FSm, FSn
+8.0xf9+4.7,2.1,1.Y,1.X+4.Sm,4.Sn:D1a:::fdiv
+"fdiv"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_div (SD, CPU, cia,
+ &XS2FS (X,Sn), &XS2FS (Y,Sm), &XS2FS (X,Sn), FP_SINGLE);
+}
+
+// 1111 1001 1111 01YX fm.- fn.-; fdiv FDm, FDn
+8.0xf9+4.0xf,2.1,1.Y,1.X+3.fm,1.0,3.fn,1.0:D1b:::fdiv
+"fdiv"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1011 0111 0100 Sm1. Sm2. Sn.. XYZ-; fdiv FSm1, FSm2, FSn
+8.0xfb+8.0x74+4.Sm1,4.Sm2+4.Sn,1.X,1.Y,1.Z,1.0:D2a:::fdiv
+"fdiv"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_div (SD, CPU, cia,
+ &XS2FS (Y,Sm2), &XS2FS (X,Sm1), &XS2FS (Z,Sn), FP_SINGLE);
+}
+
+// 1111 1011 1111 0100 fm1- fm2- fn.- XYZ-; fdiv FDm1, FDm2, FDn
+8.0xfb+8.0xf4+3.fm1,1.0,3.fm2,1.0+3.fn,1.0,1.X,1.Y,1.Z,1.0:D2b:::fdiv
+"fdiv"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+
+// 1111 1110 0111 01YX Sm.. Sn.. IMM32; fdiv imm32, FSm, FSn
+8.0xfe+4.7,2.1,1.Y,1.X+4.Sm,4.Sn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::fdiv
+"fdiv"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ uint32 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+ fpu_div (SD, CPU, cia,
+ &XS2FS (Y,Sm), &imm, &XS2FS (X,Sn), FP_SINGLE);
+ }
+}
+
+// 1111 1011 1000 00Sn Sm1. Sm2. Sm3. XYZA; fmadd FSm1, FSm2, FSm3, FSn
+8.0xfb+4.8,2.0,2.Sn+4.Sm1,4.Sm2+4.Sm3,1.X,1.Y,1.Z,1.A:D2:::fmadd
+"fmadd"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_fmadd (SD, CPU, cia,
+ &XS2FS (X,Sm1), &XS2FS (Y,Sm2), &XS2FS (Z,Sm3),
+ &AS2FS (A,Sn), FP_SINGLE);
+}
+
+// 1111 1011 1000 01Sn Sm1. Sm2. Sm3. XYZA; fmsub FSm1, FSm2, FSm3, FSn
+8.0xfb+4.8,2.1,2.Sn+4.Sm1,4.Sm2+4.Sm3,1.X,1.Y,1.Z,1.A:D2:::fmsub
+"fmsub"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_fmsub (SD, CPU, cia,
+ &XS2FS (X,Sm1), &XS2FS (Y,Sm2), &XS2FS (Z,Sm3),
+ &AS2FS (A,Sn), FP_SINGLE);
+}
+
+// 1111 1011 1001 00Sn Sm1. Sm2. Sm3. XYZA; fnmadd FSm1, FSm2, FSm3, FSn
+8.0xfb+4.9,2.0,2.Sn+4.Sm1,4.Sm2+4.Sm3,1.X,1.Y,1.Z,1.A:D2:::fnmadd
+"fnmadd"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_fnmadd (SD, CPU, cia,
+ &XS2FS (X,Sm1), &XS2FS (Y,Sm2), &XS2FS (Z,Sm3),
+ &AS2FS (A,Sn), FP_SINGLE);
+}
+
+// 1111 1011 1001 01Sn Sm1. Sm2. Sm3. XYZA; fnmsub FSm1, FSm2, FSm3, FSn
+8.0xfb+4.9,2.1,2.Sn+4.Sm1,4.Sm2+4.Sm3,1.X,1.Y,1.Z,1.A:D2:::fnmsub
+"fnmsub"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_fnmsub (SD, CPU, cia,
+ &XS2FS (X,Sm1), &XS2FS (Y,Sm2), &XS2FS (Z,Sm3),
+ &AS2FS (A,Sn), FP_SINGLE);
+}
+
+// conversion:
+
+// 1111 1011 0100 0000 Sm.. ---- Sn.. X-Z-; ftoi FSm,FSn
+8.0xfb+8.0x40+4.Sm,4.0+4.Sn,1.X,1.0,1.Z,1.0:D2:::ftoi
+"ftoi"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1011 0100 0010 Sm.. ---- Sn.. X-Z-; itof FSm,FSn
+8.0xfb+8.0x42+4.Sm,4.0+4.Sn,1.X,1.0,1.Z,1.0:D2:::itof
+"itof"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1011 0101 0010 Sm.. ---- fn.- X-Z-; ftod FSm,FDn
+8.0xfb+8.0x52+4.Sm,4.0+3.fn,1.0,1.X,1.0,1.Z,1.0:D2:::ftod
+"ftod"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1011 0101 0110 fm.- ---- Sn.. X-Z-; dtof FDm,FSn
+8.0xfb+8.0x56+3.fm,1.0,4.0+4.Sn,1.X,1.0,1.Z,1.0:D2:::dtof
+"dtof"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// branching:
+
+// 1111 1000 1101 0000 d8; fbeq (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xd0+8.D8:D1:::fbeq
+"fbeq"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & FCC_E))
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+
+// 1111 1000 1101 0001 d8; fbne (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xd1+8.D8:D1:::fbne
+"fbne"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_U | FCC_L | FCC_G)))
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+
+// 1111 1000 1101 0010 d8; fbgt (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xd2+8.D8:D1:::fbgt
+"fbgt"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & FCC_G))
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+
+// 1111 1000 1101 0011 d8; fbge (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xd3+8.D8:D1:::fbge
+"fbge"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_G | FCC_E)))
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+
+// 1111 1000 1101 0100 d8; fblt (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xd4+8.D8:D1:::fblt
+"fblt"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & FCC_L))
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+
+// 1111 1000 1101 0101 d8; fble (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xd5+8.D8:D1:::fble
+"fble"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_L | FCC_E)))
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+
+// 1111 1000 1101 0110 d8; fbuo (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xd6+8.D8:D1:::fbuo
+"fbuo"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & FCC_U))
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+
+// 1111 1000 1101 0111 d8; fblg (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xd7+8.D8:D1:::fblg
+"fblg"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_L | FCC_G)))
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+// 1111 1000 1101 1000 d8; fbleg (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xd8+8.D8:D1:::fbleg
+"fbleg"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_L | FCC_E | FCC_G)))
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+
+// 1111 1000 1101 1001 d8; fbug (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xd9+8.D8:D1:::fbug
+"fbug"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_U | FCC_G)))
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+
+// 1111 1000 1101 1010 d8; fbuge (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xda+8.D8:D1:::fbuge
+"fbuge"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_U | FCC_G | FCC_E)))
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+
+// 1111 1000 1101 1011 d8; fbul (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xdb+8.D8:D1:::fbul
+"fbul"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_U | FCC_L)))
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+
+// 1111 1000 1101 1100 d8; fbule (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xdc+8.D8:D1:::fbule
+"fbule"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_U | FCC_L | FCC_E)))
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+
+// 1111 1000 1101 1101 d8; fbue (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xdd+8.D8:D1:::fbue
+"fbue"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_U | FCC_E)))
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+
+// 1111 0000 1101 0000; fleq
+8.0xf0+8.0xd0:D0:::fleq
+"fleq"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & FCC_E))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+// 1111 0000 1101 0001; flne
+8.0xf0+8.0xd1:D0:::flne
+"flne"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_U | FCC_L | FCC_G)))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+// 1111 0000 1101 0010; flgt
+8.0xf0+8.0xd2:D0:::flgt
+"flgt"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & FCC_G))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+// 1111 0000 1101 0011; flge
+8.0xf0+8.0xd3:D0:::flge
+"flge"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_G | FCC_E)))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+// 1111 0000 1101 0100; fllt
+8.0xf0+8.0xd4:D0:::fllt
+"fllt"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & FCC_L))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+// 1111 0000 1101 0101; flle
+8.0xf0+8.0xd5:D0:::flle
+"flle"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_L | FCC_E)))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+// 1111 0000 1101 0110; fluo
+8.0xf0+8.0xd6:D0:::fluo
+"fluo"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & FCC_U))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+// 1111 0000 1101 0111; fllg
+8.0xf0+8.0xd7:D0:::fllg
+"fllg"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_L | FCC_G)))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+// 1111 0000 1101 1000; flleg
+8.0xf0+8.0xd8:D0:::flleg
+"flleg"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_L | FCC_E | FCC_G)))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+// 1111 0000 1101 1001; flug
+8.0xf0+8.0xd9:D0:::flug
+"flug"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_U | FCC_G)))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+// 1111 0000 1101 1010; fluge
+8.0xf0+8.0xda:D0:::fluge
+"fluge"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_U | FCC_G | FCC_E)))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+// 1111 0000 1101 1011; flul
+8.0xf0+8.0xdb:D0:::flul
+"flul"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_U | FCC_L)))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+// 1111 0000 1101 1100; flule
+8.0xf0+8.0xdc:D0:::flule
+"flule"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_U | FCC_L | FCC_E)))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+// 1111 0000 1101 1101; flue
+8.0xf0+8.0xdd:D0:::flue
+"flue"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_U | FCC_E)))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
8.0xf0+4.0x2,00,2.AN0:D0m:::mov
"mov"
*am33
+*am33_2
{
PC = cia;
State.regs[REG_A0 + AN0] = State.regs[REG_USP];
8.0xf0+4.0x2,01,2.AN0:D0n:::mov
"mov"
*am33
+*am33_2
{
PC = cia;
State.regs[REG_A0 + AN0] = State.regs[REG_SSP];
8.0xf0+4.0x2,10,2.AN0:D0o:::mov
"mov"
*am33
+*am33_2
{
PC = cia;
State.regs[REG_A0 + AN0] = State.regs[REG_MSP];
8.0xf0+4.0x2,11,2.AN0:D0p:::mov
"mov"
*am33
+*am33_2
{
PC = cia;
State.regs[REG_A0 + AN0] = PC;
8.0xf0+4.0x3,2.AM1,00:D0q:::mov
"mov"
*am33
+*am33_2
{
PC = cia;
State.regs[REG_USP] = State.regs[REG_A0 + AM1];
8.0xf0+4.0x3,2.AM1,01:D0r:::mov
"mov"
*am33
+*am33_2
{
PC = cia;
State.regs[REG_SSP] = State.regs[REG_A0 + AM1];
8.0xf0+4.0x3,2.AM1,10:D0s:::mov
"mov"
*am33
+*am33_2
{
PC = cia;
State.regs[REG_MSP] = State.regs[REG_A0 + AM1];
8.0xf0+4.0xe,IMM4:D0t:::syscall
"syscall"
*am33
+*am33_2
{
unsigned32 sp, next_pc;
8.0xf2+4.0xe,11,2.DN0:D0u:::mov
"mov"
*am33
+*am33_2
{
PC = cia;
State.regs[REG_D0 + DN0] = PSW;
8.0xf2+4.0xf,2.DM1,01:D0v:::mov
"mov"
*am33
+*am33_2
{
PC = cia;
PSW = State.regs[REG_D0 + DM1];
8.0xf5+00,2.AM1,4.RN0:D0w:::mov
"mov"
*am33
+*am33_2
{
int destreg = translate_rreg (SD_, RN0);
8.0xf5+01,2.DM1,4.RN0:D0x:::mov
"mov"
*am33
+*am33_2
{
int destreg = translate_rreg (SD_, RN0);
8.0xf5+10,4.RM1,2.AN0:D0y:::mov
"mov"
*am33
+*am33_2
{
int destreg = translate_rreg (SD_, RM1);
8.0xf5+11,4.RM1,2.DN0:D0z:::mov
"mov"
*am33
+*am33_2
{
int destreg = translate_rreg (SD_, RM1);
8.0xf8+8.0xce+8.REGS:D1a:::movm
"movm"
*am33
+*am33_2
{
unsigned32 usp = State.regs[REG_USP];
unsigned32 mask;
}
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
+ || STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2
)
{
if (mask & 0x1)
8.0xf8+8.0xcf+8.REGS:D1b:::movm
"movm"
*am33
+*am33_2
{
unsigned32 usp = State.regs[REG_USP];
unsigned32 mask;
mask = REGS;
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
+ || STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2
)
{
if (mask & 0x4)
8.0xfc+8.0xfc+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:4a:::and
"and"
*am33
+*am33_2
{
PC = cia;
PSW &= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
8.0xfc+8.0xfd+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::or
"or"
*am33
+*am33_2
{
PC = cia;
PSW |= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
8.0xf9+8.0x08+4.RM2,4.RN0!RM2:D1g:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xf9+8.0x18+4.RN0,4.RN2=RN0:D1:::ext
"mov"
*am33
+*am33_2
{
int srcreg;
8.0xf9+8.0x28+4.RM2,4.RN0!RM2:D1:::extb
"extb"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xf9+8.0x38+4.RM2,4.RN0!RM2:D1:::extbu
"extbu"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xf9+8.0x48+4.RM2,4.RN0!RM2:D1:::exth
"exth"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xf9+8.0x58+4.RM2,4.RN0!RM2:D1:::exthu
"exthu"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xf9+8.0x68+4.RM2,4.RN0=RM2:D1:::clr
"clr"
*am33
+*am33_2
{
int dstreg;
8.0xf9+8.0x78+4.RM2,4.RN0:D1b:::add
"add"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xf9+8.0x88+4.RM2,4.RN0:D1b:::addc
"addc"
*am33
+*am33_2
{
int srcreg, dstreg;
int z, c, n, v;
8.0xf9+8.0x98+4.RM2,4.RN0:D1b:::sub
"sub"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xf9+8.0xa8+4.RM2,4.RN0:D1b:::subc
"subc"
*am33
+*am33_2
{
int srcreg, dstreg;
int z, c, n, v;
8.0xf9+8.0xb8+4.RN0,4.RN2=RN0:D1:::inc
"inc"
*am33
+*am33_2
{
int dstreg;
8.0xf9+8.0xc8+4.RN0,4.RN2=RN0:D1:::inc4
"inc4"
*am33
+*am33_2
{
int dstreg;
8.0xf9+8.0xd8+4.RM2,4.RN0:D1:::cmp
"cmp"
*am33
+*am33_2
{
int srcreg1, srcreg2;
8.0xf9+8.0xe8+4.XRM2,4.RN0:D1l:::mov
"mov"
*am33
+*am33_2
{
int dstreg, srcreg;
8.0xf9+8.0xf8+4.RM2,4.XRN0:D1m:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xf9+8.0x09+4.RM2,4.RN0:D1a:::and
"and"
*am33
+*am33_2
{
int srcreg, dstreg;
int z, n;
8.0xf9+8.0x19+4.RM2,4.RN0:D1a:::or
"or"
*am33
+*am33_2
{
int srcreg, dstreg;
int z, n;
8.0xf9+8.0x29+4.RM2,4.RN0:D1a:::xor
"xor"
*am33
+*am33_2
{
int srcreg, dstreg;
int z, n;
8.0xf9+8.0x39+4.RM2,4.RN0=RM2:D1:::not
"not"
*am33
+*am33_2
{
int dstreg;
int z, n;
8.0xf9+8.0x49+4.RM2,4.RN0:D1a:::asr
"asr"
*am33
+*am33_2
{
int srcreg, dstreg;
signed32 temp;
8.0xf9+8.0x59+4.RM2,4.RN0:D1a:::lsr
"lsr"
*am33
+*am33_2
{
int srcreg, dstreg;
int z, n, c;
8.0xf9+8.0x69+4.RM2,4.RN0:D1a:::asl
"asl"
*am33
+*am33_2
{
int srcreg, dstreg;
int z, n;
8.0xf9+8.0x79+4.RM2,4.RN0=RM2:D1:::asl2
"asl2"
*am33
+*am33_2
{
int dstreg;
int n, z;
8.0xf9+8.0x89+4.RM2,4.RN0=RM2:D1:::ror
"ror"
*am33
+*am33_2
{
int dstreg;
int c, n, z;
8.0xf9+8.0x99+4.RM2,4.RN0=RM2:D1:::rol
"rol"
*am33
+*am33_2
{
int dstreg;
int c, n, z;
8.0xf9+8.0xa9+4.RM2,4.RN0:D1b:::mul
"mul"
*am33
+*am33_2
{
int srcreg, dstreg;
unsigned64 temp;
8.0xf9+8.0xb9+4.RM2,4.RN0:D1b:::mulu
"mulu"
*am33
+*am33_2
{
int srcreg, dstreg;
unsigned64 temp;
8.0xf9+8.0xc9+4.RM2,4.RN0:D1b:::div
"div"
*am33
+*am33_2
{
int srcreg, dstreg;
signed64 temp;
8.0xf9+8.0xd9+4.RM2,4.RN0:D1b:::divu
"divu"
*am33
+*am33_2
{
int srcreg, dstreg;
unsigned64 temp;
8.0xf9+8.0x0a+4.RN2,4.RM0:D1h:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xf9+8.0x1a+4.RM2,4.RN0:D1i:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xf9+8.0x2a+4.RN2,4.RM0:D1g:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xf9+8.0x3a+4.RM2,4.RN0:D1i:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xf9+8.0x4a+4.RN2,4.RM0:D1g:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xf9+8.0x5a+4.RM2,4.RN0:D1i:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xf9+8.0x6a+4.RN2,4.RM0!RN2:D1y:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xf9+8.0x7a+4.RM2,4.RN0:D1z:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xf9+8.0x8a+4.RN2,4.0000:D1j:::mov
"mov"
*am33
+*am33_2
{
int dstreg;
8.0xf9+8.0x9a+4.RM2,4.0000:D1k:::mov
"mov"
*am33
+*am33_2
{
int srcreg;
8.0xf9+8.0xaa+4.RN2,4.0000:D1j:::movbu
"movbu"
*am33
+*am33_2
{
int dstreg;
8.0xf9+8.0xba+4.RM2,4.0000:D1k:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg;
8.0xf9+8.0xca+4.RN2,4.0000:D1j:::movhu
"movhu"
*am33
+*am33_2
{
int dstreg;
8.0xf9+8.0xda+4.RM2,4.0000:D1k:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg;
8.0xf9+8.0xea+4.RN2,4.RM0!RN2:D1y:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xf9+8.0xfa+4.RM2,4.RN0:D1z:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xf9+8.0x0b+4.RM2,4.RN0:D1:::mac
"mac"
*am33
+*am33_2
{
int srcreg1, srcreg2;
signed64 temp, sum;
8.0xf9+8.0x1b+4.RM2,4.RN0:D1:::macu
"macu"
*am33
+*am33_2
{
int srcreg1, srcreg2;
unsigned64 temp, sum;
8.0xf9+8.0x2b+4.RM2,4.RN0:D1:::macb
"macb"
*am33
+*am33_2
{
int srcreg1, srcreg2;
signed32 temp, sum;
8.0xf9+8.0x3b+4.RM2,4.RN0:D1:::macbu
"macbu"
*am33
+*am33_2
{
int srcreg1, srcreg2;
signed64 temp, sum;
8.0xf9+8.0x4b+4.RM2,4.RN0:D1:::mach
"mach"
*am33
+*am33_2
{
int srcreg1, srcreg2;
signed64 temp, sum;
8.0xf9+8.0x5b+4.RM2,4.RN0:D1:::machu
"machu"
*am33
+*am33_2
{
int srcreg1, srcreg2;
signed64 temp, sum;
8.0xf9+8.0x6b+4.RM2,4.RN0:D1:::dmach
"dmach"
*am33
+*am33_2
{
int srcreg1, srcreg2;
signed32 temp, temp2, sum;
8.0xf9+8.0x7b+4.RM2,4.RN0:D1:::dmachu
"dmachu"
*am33
+*am33_2
{
int srcreg1, srcreg2;
unsigned32 temp, temp2, sum;
8.0xf9+8.0x8b+4.RM2,4.RN0:D1:::dmulh
"dmulh"
*am33
+*am33_2
{
int srcreg, dstreg;
signed32 temp;
8.0xf9+8.0x9b+4.RM2,4.RN0:D1:::dumachu
"dmachu"
*am33
+*am33_2
{
int srcreg, dstreg;
unsigned32 temp;
8.0xf9+8.0xab+4.RM2,4.RN0:D1:::sat16
"sat16"
*am33
+*am33_2
{
int srcreg, dstreg;
int value, z, n;
8.0xf9+8.0xbb+4.RM2,4.RN0:D1:::mcste
"mcste"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xf9+8.0xcb+4.RM2,4.RN0:D1:::swap
"swap"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xf9+8.0xdb+4.RM2,4.RN0:D1:::swaph
"swaph"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xf9+8.0xeb+4.RM2,4.RN0:D1:::swhw
"swhw"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xf9+8.0xfb+4.RM2,4.RN0:D1:::bsch
"bsch"
*am33
+*am33_2
{
int temp, c, i;
int srcreg, dstreg;
8.0xfb+8.0x08+4.RM2,4.RN0=RM2+8.IMM8:D2j:::mov
"mov"
*am33
+*am33_2
{
int dstreg;
8.0xfb+8.0x18+4.RM2,4.RN0=RM2+8.IMM8:D2:::movu
"movu"
*am33
+*am33_2
{
int dstreg;
8.0xfb+8.0x78+4.RM2,4.RN0=RM2+8.IMM8:D2d:::add
"add"
*am33
+*am33_2
{
int dstreg;
8.0xfb+8.0x88+4.RM2,4.RN0=RM2+8.IMM8:D2d:::addc
"addc"
*am33
+*am33_2
{
int dstreg, imm;
int z, c, n, v;
8.0xfb+8.0x98+4.RM2,4.RN0=RM2+8.IMM8:D2d:::sub
"sub"
*am33
+*am33_2
{
int dstreg;
8.0xfb+8.0xa8+4.RM2,4.RN0=RM2+8.IMM8:D2d:::subc
"subc"
*am33
+*am33_2
{
int imm, dstreg;
int z, c, n, v;
8.0xfb+8.0xd8+4.RM2,4.RN0=RM2+8.IMM8:D2b:::cmp
"cmp"
*am33
+*am33_2
{
int srcreg;
8.0xfb+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM8:D2k:::mov
"mov"
*am33
+*am33_2
{
int dstreg;
8.0xfb+8.0x09+4.RM2,4.RN0=RM2+8.IMM8:D2d:::and
"and"
*am33
+*am33_2
{
int dstreg;
int z, n;
8.0xfb+8.0x19+4.RM2,4.RN0=RM2+8.IMM8:D2d:::or
"or"
*am33
+*am33_2
{
int dstreg;
int z, n;
8.0xfb+8.0x29+4.RM2,4.RN0=RM2+8.IMM8:D2d:::xor
"xor"
*am33
+*am33_2
{
int dstreg;
int z, n;
8.0xfb+8.0x49+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asr
"asr"
*am33
+*am33_2
{
int dstreg;
signed32 temp;
8.0xfb+8.0x59+4.RM2,4.RN0=RM2+8.IMM8:D2a:::lsr
"lsr"
*am33
+*am33_2
{
int dstreg;
int z, n, c;
8.0xfb+8.0x69+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asl
"asl"
*am33
+*am33_2
{
int dstreg;
int z, n;
8.0xfb+8.0xa9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mul
"mul"
*am33
+*am33_2
{
int dstreg;
unsigned64 temp;
8.0xfb+8.0xb9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mulu
"mulu"
*am33
+*am33_2
{
int dstreg;
unsigned64 temp;
8.0xfb+8.0xe9+4.RN2,4.RM0=RN2+8.IMM8:D2l:::btst
"btst"
*am33
+*am33_2
{
int srcreg;
8.0xfb+8.0x0a+4.RN2,4.RM0+8.IMM8:D2l:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xfb+8.0x1a+4.RM2,4.RN0+8.IMM8:D2m:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xfb+8.0x2a+4.RN2,4.RM0+8.IMM8:D2l:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xfb+8.0x3a+4.RM2,4.RN0+8.IMM8:D2m:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xfb+8.0x4a+4.RN2,4.RM0+8.IMM8:D2l:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xfb+8.0x5a+4.RM2,4.RN0+8.IMM8:D2m:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xfb+8.0x6a+4.RN2,4.RM0!RN2+8.IMM8:D2y:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xfb+8.0x7a+4.RM2,4.RN0+8.IMM8:D2z:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xfb+8.0x8a+4.RN2,4.0x0+8.IMM8:D2n:::mov
"mov"
*am33
+*am33_2
{
int dstreg;
8.0xfb+8.0x9a+4.RM2,4.0x0+8.IMM8:D2o:::mov
"mov"
*am33
+*am33_2
{
int srcreg;
8.0xfb+8.0xaa+4.RN2,4.0x0+8.IMM8:D2n:::movbu
"movbu"
*am33
+*am33_2
{
int dstreg;
8.0xfb+8.0xba+4.RM2,4.0x0+8.IMM8:D2o:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg;
8.0xfb+8.0xca+4.RN2,4.0x0+8.IMM8:D2n:::movhu
"movhu"
*am33
+*am33_2
{
int dstreg;
8.0xfb+8.0xda+4.RM2,4.0x0+8.IMM8:D2o:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg;
8.0xfb+8.0xea+4.RN2,4.RM0!RN2+8.IMM8:D2y:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xfb+8.0xfa+4.RM2,4.RN0+8.IMM8:D2z:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xfb+8.0x0b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mac
"mac"
*am33
+*am33_2
{
int srcreg;
signed64 temp, sum;
8.0xfb+8.0x1b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macu
"macu"
*am33
+*am33_2
{
int srcreg;
signed64 temp, sum;
8.0xfb+8.0x2b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macb
"macb"
*am33
+*am33_2
{
int srcreg;
signed64 temp, sum;
8.0xfb+8.0x3b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macbu
"macbu"
*am33
+*am33_2
{
int srcreg;
signed64 temp, sum;
8.0xfb+8.0x4b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mach
"mach"
*am33
+*am33_2
{
int srcreg;
signed64 temp, sum;
8.0xfb+8.0x5b+4.RN2,4.RN0=RN2+8.IMM8:D2:::machu
"machu"
*am33
+*am33_2
{
int srcreg;
signed64 temp, sum;
8.0xfb+8.0xbb+4.RN2,4.RN0=RN2+8.IMM8:D2:::mcste
"mcste"
*am33
+*am33_2
{
int dstreg;
8.0xfb+8.0x7c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::add
"add"
*am33
+*am33_2
{
int z, c, n, v;
unsigned32 sum, source1, source2;
8.0xfb+8.0x8c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::addc
"addc"
*am33
+*am33_2
{
int z, c, n, v;
unsigned32 sum, source1, source2;
8.0xfb+8.0x9c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::sub
"sub"
*am33
+*am33_2
{
int z, c, n, v;
unsigned32 difference, source1, source2;
8.0xfb+8.0xac+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::subc
"subc"
*am33
+*am33_2
{
int z, c, n, v;
unsigned32 difference, source1, source2;
8.0xfb+8.0x0d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::and
"and"
*am33
+*am33_2
{
int z, n;
int srcreg1, srcreg2, dstreg;
8.0xfb+8.0x1d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::or
"or"
*am33
+*am33_2
{
int z, n;
int srcreg1, srcreg2, dstreg;
8.0xfb+8.0x2d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::xor
"xor"
*am33
+*am33_2
{
int z, n;
int srcreg1, srcreg2, dstreg;
8.0xfb+8.0x4d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asr
"asr"
*am33
+*am33_2
{
int z, c, n;
signed32 temp;
8.0xfb+8.0x5d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::lsr
"lsr"
*am33
+*am33_2
{
int z, c, n;
int srcreg1, srcreg2, dstreg;
8.0xfb+8.0x6d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asl
"asl"
*am33
+*am33_2
{
int z, n;
int srcreg1, srcreg2, dstreg;
8.0xfb+8.0xad+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mul
"mul"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed64 temp;
8.0xfb+8.0xbd+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mulu
"mulu"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed64 temp;
8.0xfb+8.0x0e+4.RN2,4.0x0+8.IMM8:D2p:::mov
"mov"
*am33
+*am33_2
{
int dstreg;
8.0xfb+8.0x1e+4.RM2,4.0x0+8.IMM8:D2q:::mov
"mov"
*am33
+*am33_2
{
int srcreg;
8.0xfb+8.0x2e+4.RN2,4.0x0+8.IMM8:D2p:::movbu
"movbu"
*am33
+*am33_2
{
int dstreg;
8.0xfb+8.0x3e+4.RM2,4.0x0+8.IMM8:D2q:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg;
8.0xfb+8.0x4e+4.RN2,4.0x0+8.IMM8:D2p:::movhu
"movhu"
*am33
+*am33_2
{
int dstreg;
8.0xfb+8.0x5e+4.RM2,4.0x0+8.IMM8:D2q:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg;
8.0xfb+8.0x8e+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::mov
"mov"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg;
8.0xfb+8.0x9e+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg1, dstreg2;
8.0xfb+8.0xae+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg;
8.0xfb+8.0xbe+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg, dstreg1, dstreg2;
8.0xfb+8.0xce+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg;
8.0xfb+8.0xde+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg1, dstreg2;
8.0xfb+8.0x0f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mac
"mac"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed64 temp;
8.0xfb+8.0x1f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::macu
"macu"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed64 temp;
8.0xfb+8.0x2f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::macb
"macb"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg;
signed32 temp, sum;
8.0xfb+8.0x3f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::macbu
"macbu"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg;
signed32 temp, sum;
8.0xfb+8.0x4f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mach
"mach"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed64 temp, sum;
8.0xfb+8.0x5f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::machu
"machu"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed64 temp, sum;
8.0xfb+8.0x6f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::dmach
"dmach"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg;
signed32 temp, temp2, sum;
8.0xfb+8.0x7f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::dmachu
"dmachu"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg;
signed32 temp, temp2, sum;
8.0xfb+8.0x8f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::dmulh
"dmulh"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed64 temp;
8.0xfb+8.0x9f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::dmulhu
"dmulhu"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed64 temp;
8.0xfb+8.0xaf+4.RM2,4.RN0+8.0x0:D2:::sat24
"sat24"
*am33
+*am33_2
{
int srcreg, dstreg;
int value, n, z;
8.0xfb+8.0xff+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::bsch
"bsch"
*am33
+*am33_2
{
int temp, c, i;
int srcreg1, srcreg2, dstreg;
8.0xfd+8.0x08+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::mov
"mov"
*am33
+*am33_2
{
int dstreg;
8.0xfd+8.0x18+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4k:::movu
"movu"
*am33
+*am33_2
{
int dstreg;
8.0xfd+8.0x78+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4c:::add
"add"
*am33
+*am33_2
{
int dstreg;
8.0xfd+8.0x88+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::addc
"addc"
*am33
+*am33_2
{
int dstreg, z, n, c, v;
unsigned32 sum, imm, reg2;
8.0xfd+8.0x98+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::sub
"sub"
*am33
+*am33_2
{
int dstreg;
8.0xfd+8.0xa8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::subc
"subc"
*am33
+*am33_2
{
int dstreg, z, n, c, v;
unsigned32 difference, imm, reg2;
8.0xfd+8.0xd8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::cmp
"cmp"
*am33
+*am33_2
{
int srcreg;
8.0xfd+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM24A+8.IMM24B+8.IMM24C:D4o:::mov
"mov"
*am33
+*am33_2
{
int dstreg;
8.0xfd+8.0x09+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::and
"and"
*am33
+*am33_2
{
int dstreg;
int z,n;
8.0xfd+8.0x19+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::or
"or"
*am33
+*am33_2
{
int dstreg;
int z,n;
8.0xfd+8.0x29+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::xor
"xor"
*am33
+*am33_2
{
int dstreg;
int z,n;
8.0xfd+8.0x49+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asr
"asr"
*am33
+*am33_2
{
int dstreg;
signed32 temp;
8.0xfd+8.0x59+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::lsr
"lsr"
*am33
+*am33_2
{
int dstreg;
int z, n, c;
8.0xfd+8.0x69+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asl
"asl"
*am33
+*am33_2
{
int dstreg;
int z, n;
8.0xfd+8.0xa9+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::mul
"mul"
*am33
+*am33_2
{
int dstreg;
unsigned64 temp;
8.0xfd+8.0xb9+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::mulu
"mulu"
*am33
+*am33_2
{
int dstreg;
unsigned64 temp;
8.0xfd+8.0xe9+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::btst
"btst"
*am33
+*am33_2
{
int srcreg;
8.0xfd+8.0x0a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xfd+8.0x1a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xfd+8.0x2a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xfd+8.0x3a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xfd+8.0x4a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xfd+8.0x5a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xfd+8.0x6a+4.RN2,4.RM0!RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xfd+8.0x7a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xfd+8.0x8a+4.RN2,4.0x0+IMM24A+8.IMM24B+8.IMM24C:D4r:::mov
"mov"
*am33
+*am33_2
{
int dstreg;
8.0xfd+8.0x9a+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::mov
"mov"
*am33
+*am33_2
{
int srcreg;
8.0xfd+8.0xaa+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movbu
"movbu"
*am33
+*am33_2
{
int dstreg;
8.0xfd+8.0xba+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg;
8.0xfd+8.0xca+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movhu
"movhu"
*am33
+*am33_2
{
int dstreg;
8.0xfd+8.0xda+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg;
8.0xfd+8.0xea+4.RN2,4.RM0!RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xfd+8.0xfa+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xfd+8.0x0b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mac
"mac"
*am33
+*am33_2
{
int srcreg;
signed64 temp, sum;
8.0xfd+8.0x1b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macu
"macu"
*am33
+*am33_2
{
int srcreg;
signed64 temp, sum;
8.0xfd+8.0x2b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macb
"macb"
*am33
+*am33_2
{
int srcreg;
signed64 temp, sum;
8.0xfd+8.0x3b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macbu
"macbu"
*am33
+*am33_2
{
int srcreg;
signed64 temp, sum;
8.0xfd+8.0x4b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mach
"mach"
*am33
+*am33_2
{
int srcreg;
signed64 temp, sum;
8.0xfd+8.0x5b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::machu
"machu"
*am33
+*am33_2
{
int srcreg;
signed64 temp, sum;
8.0xfd+8.0x0e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::mov
"mov"
*am33
+*am33_2
{
int dstreg;
8.0xfd+8.0x1e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4v:::mov
"mov"
*am33
+*am33_2
{
int srcreg;
8.0xfd+8.0x2e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movbu
"movbu"
*am33
+*am33_2
{
int dstreg;
8.0xfd+8.0x3e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg;
8.0xfd+8.0x4e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movhu
"movhu"
*am33
+*am33_2
{
int dstreg;
8.0xfd+8.0x5e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg;
8.0xfe+8.0x08+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mov
"mov"
*am33
+*am33_2
{
int dstreg;
8.0xfe+8.0x18+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movu
"movu"
*am33
+*am33_2
{
int dstreg;
8.0xfe+8.0x78+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::add
"add"
*am33
+*am33_2
{
int dstreg;
8.0xfe+8.0x88+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::addc
"addc"
*am33
+*am33_2
{
int dstreg;
unsigned32 imm, reg2, sum;
8.0xfe+8.0x98+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::sub
"sub"
*am33
+*am33_2
{
int dstreg;
8.0xfe+8.0xa8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::subc
"subc"
*am33
+*am33_2
{
int dstreg;
unsigned32 imm, reg2, difference;
8.0xfe+8.0xd8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::cmp
"cmp"
*am33
+*am33_2
{
int srcreg;
8.0xfe+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::mov
"mov"
*am33
+*am33_2
{
int dstreg;
8.0xfe+8.0x09+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::and
"and"
*am33
+*am33_2
{
int dstreg;
int z,n;
8.0xfe+8.0x19+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::or
"or"
*am33
+*am33_2
{
int dstreg;
int z,n;
8.0xfe+8.0x29+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::xor
"xor"
*am33
+*am33_2
{
int dstreg;
int z,n;
8.0xfe+8.0x49+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asr
"asr"
*am33
+*am33_2
{
int dstreg;
signed32 temp;
8.0xfe+8.0x59+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::lsr
"lsr"
*am33
+*am33_2
{
int dstreg;
int z, n, c;
8.0xfe+8.0x69+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asl
"asl"
*am33
+*am33_2
{
int dstreg;
int z, n;
8.0xfe+8.0xa9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mul
"mul"
*am33
+*am33_2
{
int dstreg;
unsigned64 temp;
8.0xfe+8.0xb9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mulu
"mulu"
*am33
+*am33_2
{
int dstreg;
unsigned64 temp;
8.0xfe+8.0xe9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5a:::btst
"btst"
*am33
+*am33_2
{
int srcreg;
8.0xfe+8.0x0a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xfe+8.0x1a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5g:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xfe+8.0x2a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xfe+8.0x3a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xfe+8.0x4a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xfe+8.0x5a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xfe+8.0x6a+4.RN2,4.RM0!RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xfe+8.0x7a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5z:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xfe+8.0x8a+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::mov
"mov"
*am33
+*am33_2
{
int dstreg;
8.0xfe+8.0x9a+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::mov
"mov"
*am33
+*am33_2
{
int srcreg;
8.0xfe+8.0xaa+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movbu
"movbu"
*am33
+*am33_2
{
int dstreg;
8.0xfe+8.0xba+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg;
8.0xfe+8.0xca+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movhu
"movhu"
*am33
+*am33_2
{
int dstreg;
8.0xfe+8.0xda+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg;
8.0xfe+8.0xea+4.RN2,4.RM0!RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xfe+8.0xfa+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xfe+8.0x0b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mac
"mac"
*am33
+*am33_2
{
int srcreg, imm;
signed64 temp, sum;
8.0xfe+8.0x1b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macu
"macu"
*am33
+*am33_2
{
int srcreg, imm;
signed64 temp, sum;
8.0xfe+8.0x2b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macb
"macb"
*am33
+*am33_2
{
int srcreg, imm;
signed32 temp, sum;
8.0xfe+8.0x3b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macbu
"macbu"
*am33
+*am33_2
{
int srcreg, imm;
signed32 temp, sum;
8.0xfe+8.0x4b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mach
"mach"
*am33
+*am33_2
{
int srcreg, imm;
signed32 temp, sum;
8.0xfe+8.0x5b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::machu
"machu"
*am33
+*am33_2
{
int srcreg, imm;
signed32 temp, sum;
8.0xfe+8.0x6b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmach
"dmach"
*am33
+*am33_2
{
int srcreg, imm;
signed32 temp, temp2, sum;
8.0xfe+8.0x7b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmachu
"dmachu"
*am33
+*am33_2
{
int srcreg, imm;
signed32 temp, temp2, sum;
8.0xfe+8.0x8b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmulh
"dmulh"
*am33
+*am33_2
{
int imm, dstreg;
signed32 temp;
8.0xfe+8.0x9b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmulhu
"dmulhu"
*am33
+*am33_2
{
int imm, dstreg;
signed32 temp;
8.0xfe+8.0x0e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5h:::mov
"mov"
*am33
+*am33_2
{
int dstreg;
8.0xfe+8.0x1e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::mov
"mov"
*am33
+*am33_2
{
int srcreg;
8.0xfe+8.0x2e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5i:::movbu
"movbu"
*am33
+*am33_2
{
int dstreg;
8.0xfe+8.0x3e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg;
8.0xfe+8.0x4e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5j:::movhu
"movhu"
*am33
+*am33_2
{
int dstreg;
8.0xfe+8.0x5e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg;
8.0xf7+8.0x00+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_add
"add_add"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x10+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_add
"add_add"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x20+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_sub
"add_sub"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x30+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_sub
"add_sub"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x40+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_cmp
"add_cmp"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
8.0xf7+8.0x50+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_cmp
"add_cmp"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
8.0xf7+8.0x60+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_mov
"add_mov"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x70+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_mov
"add_mov"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x80+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_asr
"add_asr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x90+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_asr
"add_asr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0xa0+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_lsr
"add_lsr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0xb0+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_lsr
"add_lsr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0xc0+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_asl
"add_asl"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0xd0+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_asl
"add_asl"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x01+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_add
"cmp_add"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
8.0xf7+8.0x11+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_add
"cmp_add"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
8.0xf7+8.0x21+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_sub
"cmp_sub"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
8.0xf7+8.0x31+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_sub
"cmp_sub"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
8.0xf7+8.0x61+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_mov
"cmp_mov"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
8.0xf7+8.0x71+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_mov
"cmp_mov"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
8.0xf7+8.0x81+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_asr
"cmp_asr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed int temp;
8.0xf7+8.0x91+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_asr
"cmp_asr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
signed int temp;
8.0xf7+8.0xa1+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_lsr
"cmp_lsr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
8.0xf7+8.0xb1+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_lsr
"cmp_lsr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
8.0xf7+8.0xc1+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_asl
"cmp_asl"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
8.0xf7+8.0xd1+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_asl
"cmp_asl"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
8.0xf7+8.0x02+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_add
"sub_add"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x12+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_add
"sub_add"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x22+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_sub
"sub_sub"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x32+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_sub
"sub_sub"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x42+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_cmp
"sub_cmp"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
8.0xf7+8.0x52+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_cmp
"sub_cmp"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
8.0xf7+8.0x62+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_mov
"sub_mov"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x72+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_mov
"sub_mov"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x82+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_asr
"sub_asr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x92+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_asr
"sub_asr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0xa2+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_lsr
"sub_lsr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0xb2+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_lsr
"sub_lsr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0xc2+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_asl
"sub_asl"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0xd2+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_asl
"sub_asl"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x03+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_add
"mov_add"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x13+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_add
"mov_add"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x23+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_sub
"mov_sub"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x33+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_sub
"mov_sub"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x43+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_cmp
"mov_cmp"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
8.0xf7+8.0x53+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_cmp
"mov_cmp"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
8.0xf7+8.0x63+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_mov
"mov_mov"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x73+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_mov
"mov_mov"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x83+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_asr
"mov_asr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x93+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_asr
"mov_asr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0xa3+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_lsr
"mov_lsr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0xb3+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_lsr
"mov_lsr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0xc3+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_asl
"mov_asl"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0xd3+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_asl
"mov_asl"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x04+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_add
"add_add"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x14+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_add
"add_add"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
8.0xf7+8.0x24+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_sub
"add_sub"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x34+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_sub
"add_sub"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
8.0xf7+8.0x44+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_cmp
"add_cmp"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
8.0xf7+8.0x54+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_cmp
"add_cmp"
*am33
+*am33_2
{
int dstreg1, dstreg2;
8.0xf7+8.0x64+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_mov
"add_mov"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x74+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_mov
"add_mov"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
8.0xf7+8.0x84+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_asr
"add_asr"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x94+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_asr
"add_asr"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
8.0xf7+8.0xa4+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_lsr
"add_lsr"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0xb4+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_lsr
"add_lsr"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
8.0xf7+8.0xc4+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_asl
"add_asl"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0xd4+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_asl
"add_asl"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
8.0xf7+8.0x05+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_add
"cmp_add"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
8.0xf7+8.0x15+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_add
"cmp_add"
*am33
+*am33_2
{
int dstreg1, dstreg2;
8.0xf7+8.0x25+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_sub
"cmp_sub"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
8.0xf7+8.0x35+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_sub
"cmp_sub"
*am33
+*am33_2
{
int dstreg1, dstreg2;
8.0xf7+8.0x65+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_mov
"cmp_mov"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
8.0xf7+8.0x75+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_mov
"cmp_mov"
*am33
+*am33_2
{
int dstreg1, dstreg2;
8.0xf7+8.0x85+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_asr
"cmp_asr"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
signed int temp;
8.0xf7+8.0x95+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_asr
"cmp_asr"
*am33
+*am33_2
{
int dstreg1, dstreg2;
signed int temp;
8.0xf7+8.0xa5+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_lsr
"cmp_lsr"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
8.0xf7+8.0xb5+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_lsr
"cmp_lsr"
*am33
+*am33_2
{
int dstreg1, dstreg2;
8.0xf7+8.0xc5+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_asl
"cmp_asl"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
8.0xf7+8.0xd5+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_asl
"cmp_asl"
*am33
+*am33_2
{
int dstreg1, dstreg2;
8.0xf7+8.0x06+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_add
"sub_add"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x16+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_add
"sub_add"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
8.0xf7+8.0x26+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_sub
"sub_sub"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x36+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_sub
"sub_sub"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
8.0xf7+8.0x46+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_cmp
"sub_cmp"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
8.0xf7+8.0x56+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_cmp
"sub_cmp"
*am33
+*am33_2
{
int dstreg1, dstreg2;
8.0xf7+8.0x66+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_mov
"sub_mov"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x76+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_mov
"sub_mov"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
8.0xf7+8.0x86+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_asr
"sub_asr"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x96+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_asr
"sub_asr"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
8.0xf7+8.0xa6+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_lsr
"sub_lsr"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0xb6+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_lsr
"sub_lsr"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
8.0xf7+8.0xc6+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_asl
"sub_asl"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0xd6+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_asl
"sub_asl"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
8.0xf7+8.0x07+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_add
"mov_add"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x17+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_add
"mov_add"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
8.0xf7+8.0x27+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_sub
"mov_sub"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x37+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_sub
"mov_sub"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
8.0xf7+8.0x47+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_cmp
"mov_cmp"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
8.0xf7+8.0x57+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_cmp
"mov_cmp"
*am33
+*am33_2
{
int dstreg1, dstreg2;
8.0xf7+8.0x67+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_mov
"mov_mov"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x77+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_mov
"mov_mov"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
8.0xf7+8.0x87+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_asr
"mov_asr"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x97+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_asr
"mov_asr"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
8.0xf7+8.0xa7+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_lsr
"mov_lsr"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0xb7+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_lsr
"mov_lsr"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
8.0xf7+8.0xc7+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_asl
"mov_asl"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0xd7+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_asl
"mov_asl"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
8.0xf7+8.0x08+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_add
"and_add"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x18+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_add
"and_add"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x28+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_sub
"and_sub"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x38+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_sub
"and_sub"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x48+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_cmp
"and_cmp"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
8.0xf7+8.0x58+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_cmp
"and_cmp"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
8.0xf7+8.0x68+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_mov
"and_mov"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x78+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_mov
"and_mov"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x88+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_asr
"and_asr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x98+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_asr
"and_asr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0xa8+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_lsr
"and_lsr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0xb8+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_lsr
"and_lsr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0xc8+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_asl
"and_asl"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0xd8+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_asl
"and_asl"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x09+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_add
"dmach_add"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed32 temp, temp2, sum;
8.0xf7+8.0x19+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_add
"dmach_add"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
signed32 temp, temp2, sum;
8.0xf7+8.0x29+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_sub
"dmach_sub"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed32 temp, temp2, sum;
8.0xf7+8.0x39+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_sub
"dmach_sub"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
signed32 temp, temp2, sum;
8.0xf7+8.0x49+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_cmp
"dmach_cmp"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed32 temp, temp2, sum;
8.0xf7+8.0x59+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_cmp
"dmach_cmp"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
signed32 temp, temp2, sum;
8.0xf7+8.0x69+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_mov
"dmach_mov"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed32 temp, temp2, sum;
8.0xf7+8.0x79+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_mov
"dmach_mov"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
signed32 temp, temp2, sum;
8.0xf7+8.0x89+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_asr
"dmach_asr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed32 temp, temp2, sum;
8.0xf7+8.0x99+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_asr
"dmach_asr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
signed32 temp, temp2, sum;
8.0xf7+8.0xa9+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_lsr
"dmach_lsr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed32 temp, temp2, sum;
8.0xf7+8.0xb9+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_lsr
"dmach_lsr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
signed32 temp, temp2, sum;
8.0xf7+8.0xc9+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_asl
"dmach_asl"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed32 temp, temp2, sum;
8.0xf7+8.0xd9+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_asl
"dmach_asl"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
signed32 temp, temp2, sum;
8.0xf7+8.0x0a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_add
"xor_add"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x1a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_add
"xor_add"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x2a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_sub
"xor_sub"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x3a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_sub
"xor_sub"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x4a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_cmp
"xor_cmp"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
8.0xf7+8.0x5a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_cmp
"xor_cmp"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
8.0xf7+8.0x6a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_mov
"xor_mov"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x7a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_mov
"xor_mov"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x8a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_asr
"xor_asr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x9a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_asr
"xor_asr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0xaa+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_lsr
"xor_lsr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0xba+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_lsr
"xor_lsr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0xca+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_asl
"xor_asl"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0xda+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_asl
"xor_asl"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x0b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_add
"swhw_add"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x1b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_add
"swhw_add"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x2b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_sub
"swhw_sub"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x3b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_sub
"swhw_sub"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x4b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_cmp
"swhw_cmp"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
8.0xf7+8.0x5b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_cmp
"swhw_cmp"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
8.0xf7+8.0x6b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_mov
"swhw_mov"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x7b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_mov
"swhw_mov"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x8b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_asr
"swhw_asr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x9b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_asr
"swhw_asr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0xab+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_lsr
"swhw_lsr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0xbb+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_lsr
"swhw_lsr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0xcb+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_asl
"swhw_asl"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0xdb+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_asl
"swhw_asl"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x0c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_add
"or_add"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x1c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_add
"or_add"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x2c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_sub
"or_sub"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x3c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_sub
"or_sub"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x4c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_cmp
"or_cmp"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
8.0xf7+8.0x5c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_cmp
"or_cmp"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
8.0xf7+8.0x6c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_mov
"or_mov"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x7c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_mov
"or_mov"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x8c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_asr
"or_asr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x9c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_asr
"or_asr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0xac+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_lsr
"or_lsr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0xbc+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_lsr
"or_lsr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0xcc+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_asl
"or_asl"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0xdc+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_asl
"or_asl"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x0d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_add
"sat16_add"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x1d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_add
"sat16_add"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x2d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_sub
"sat16_sub"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x3d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_sub
"sat16_sub"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x4d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_cmp
"sat16_cmp"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
8.0xf7+8.0x5d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_cmp
"sat16_cmp"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
8.0xf7+8.0x6d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_mov
"sat16_mov"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x7d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_mov
"sat16_mov"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x8d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_asr
"sat16_asr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x9d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_asr
"sat16_asr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0xad+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_lsr
"sat16_lsr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0xbd+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_lsr
"sat16_lsr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0xcd+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_asl
"sat16_asl"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0xdd+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_asl
"sat16_asl"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x0:D2:::mov_llt
"mov_llt"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x1:D2:::mov_lgt
"mov_lgt"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x2:D2:::mov_lge
"mov_lge"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x3:D2:::mov_lle
"mov_lle"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x4:D2:::mov_lcs
"mov_lcs"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x5:D2:::mov_lhi
"mov_lhi"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x6:D2:::mov_lcc
"mov_lcc"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x7:D2:::mov_lls
"mov_lls"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x8:D2:::mov_leq
"mov_leq"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x9:D2:::mov_lne
"mov_lne"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0xa:D2:::mov_lra
"mov_lra"
*am33
+*am33_2
{
int srcreg, dstreg;
nia = PC;
}
+:include::am33_2:am33-2.igen
}
CIA_SET (STATE_CPU (sd, 0), (unsigned64) PC);
+ if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2)
+ PSW |= PSW_FE;
+
return SIM_RC_OK;
}
}
State.exc_suspended = 0;
}
+
+/* This is called when an FP instruction is issued when the FP unit is
+ disabled, i.e., the FE bit of PSW is zero. It raises interrupt
+ code 0x1c0. */
+void
+fpu_disabled_exception (SIM_DESC sd, sim_cpu *cpu, sim_cia cia)
+{
+ sim_io_eprintf(sd, "FPU disabled exception\n");
+ program_interrupt (sd, cpu, cia, SIM_SIGFPE);
+}
+
+/* This is called when the FP unit is enabled but one of the
+ unimplemented insns is issued. It raises interrupt code 0x1c8. */
+void
+fpu_unimp_exception (SIM_DESC sd, sim_cpu *cpu, sim_cia cia)
+{
+ sim_io_eprintf(sd, "Unimplemented FPU instruction exception\n");
+ program_interrupt (sd, cpu, cia, SIM_SIGFPE);
+}
+
+/* This is called at the end of any FP insns that may have triggered
+ FP exceptions. If no exception is enabled, it returns immediately.
+ Otherwise, it raises an exception code 0x1d0. */
+void
+fpu_check_signal_exception (SIM_DESC sd, sim_cpu *cpu, sim_cia cia)
+{
+ if ((FPCR & EC_MASK) == 0)
+ return;
+
+ sim_io_eprintf(sd, "FPU %s%s%s%s%s exception\n",
+ (FPCR & EC_V) ? "V" : "",
+ (FPCR & EC_Z) ? "Z" : "",
+ (FPCR & EC_O) ? "O" : "",
+ (FPCR & EC_U) ? "U" : "",
+ (FPCR & EC_I) ? "I" : "");
+ program_interrupt (sd, cpu, cia, SIM_SIGFPE);
+}
+
+/* Convert a 32-bit single-precision FP value in the target platform
+ format to a sim_fpu value. */
+static void
+reg2val_32 (const void *reg, sim_fpu *val)
+{
+ FS2FPU (*(reg_t *)reg, *val);
+}
+
+/* Round the given sim_fpu value to single precision, following the
+ target platform rounding and denormalization conventions. On
+ AM33/2.0, round_near is the only rounding mode. */
+static int
+round_32 (sim_fpu *val)
+{
+ return sim_fpu_round_32 (val, sim_fpu_round_near, sim_fpu_denorm_zero);
+}
+
+/* Convert a sim_fpu value to the 32-bit single-precision target
+ representation. */
+static void
+val2reg_32 (const sim_fpu *val, void *reg)
+{
+ FPU2FS (*val, *(reg_t *)reg);
+}
+
+/* Define the 32-bit single-precision conversion and rounding uniform
+ interface. */
+const struct fp_prec_t
+fp_single_prec = {
+ reg2val_32, round_32, val2reg_32
+};
+
+/* Convert a 64-bit double-precision FP value in the target platform
+ format to a sim_fpu value. */
+static void
+reg2val_64 (const void *reg, sim_fpu *val)
+{
+ FD2FPU (*(dword *)reg, *val);
+}
+
+/* Round the given sim_fpu value to double precision, following the
+ target platform rounding and denormalization conventions. On
+ AM33/2.0, round_near is the only rounding mode. */
+int
+round_64 (sim_fpu *val)
+{
+ return sim_fpu_round_64 (val, sim_fpu_round_near, sim_fpu_denorm_zero);
+}
+
+/* Convert a sim_fpu value to the 64-bit double-precision target
+ representation. */
+static void
+val2reg_64 (const sim_fpu *val, void *reg)
+{
+ FPU2FD (*val, *(dword *)reg);
+}
+
+/* Define the 64-bit single-precision conversion and rounding uniform
+ interface. */
+const struct fp_prec_t
+fp_double_prec = {
+ reg2val_64, round_64, val2reg_64
+};
+
+/* Define shortcuts to the uniform interface operations. */
+#define REG2VAL(reg,val) (*ops->reg2val) (reg,val)
+#define ROUND(val) (*ops->round) (val)
+#define VAL2REG(val,reg) (*ops->val2reg) (val,reg)
+
+/* Check whether overflow, underflow or inexact exceptions should be
+ raised. */
+int
+fpu_status_ok (sim_fpu_status stat)
+{
+ if ((stat & sim_fpu_status_overflow)
+ && (FPCR & EE_O))
+ FPCR |= EC_O;
+ else if ((stat & (sim_fpu_status_underflow | sim_fpu_status_denorm))
+ && (FPCR & EE_U))
+ FPCR |= EC_U;
+ else if ((stat & (sim_fpu_status_inexact | sim_fpu_status_rounded))
+ && (FPCR & EE_I))
+ FPCR |= EC_I;
+ else if (stat & ~ (sim_fpu_status_overflow
+ | sim_fpu_status_underflow
+ | sim_fpu_status_denorm
+ | sim_fpu_status_inexact
+ | sim_fpu_status_rounded))
+ abort ();
+ else
+ return 1;
+ return 0;
+}
+
+/* Implement a 32/64 bit reciprocal square root, signaling FP
+ exceptions when appropriate. */
+void
+fpu_rsqrt (SIM_DESC sd, sim_cpu *cpu, sim_cia cia,
+ const void *reg_in, void *reg_out, const struct fp_prec_t *ops)
+{
+ sim_fpu in, med, out;
+
+ REG2VAL (reg_in, &in);
+ ROUND (&in);
+ FPCR &= ~ EC_MASK;
+ switch (sim_fpu_is (&in))
+ {
+ case SIM_FPU_IS_SNAN:
+ case SIM_FPU_IS_NNUMBER:
+ case SIM_FPU_IS_NINF:
+ if (FPCR & EE_V)
+ FPCR |= EC_V;
+ else
+ VAL2REG (&sim_fpu_qnan, reg_out);
+ break;
+
+ case SIM_FPU_IS_QNAN:
+ VAL2REG (&sim_fpu_qnan, reg_out);
+ break;
+
+ case SIM_FPU_IS_PINF:
+ VAL2REG (&sim_fpu_zero, reg_out);
+ break;
+
+ case SIM_FPU_IS_PNUMBER:
+ {
+ /* Since we don't have a function to compute rsqrt directly,
+ use sqrt and inv. */
+ sim_fpu_status stat = 0;
+ stat |= sim_fpu_sqrt (&med, &in);
+ stat |= sim_fpu_inv (&out, &med);
+ stat |= ROUND (&out);
+ if (fpu_status_ok (stat))
+ VAL2REG (&out, reg_out);
+ }
+ break;
+
+ case SIM_FPU_IS_NZERO:
+ case SIM_FPU_IS_PZERO:
+ if (FPCR & EE_Z)
+ FPCR |= EC_Z;
+ else
+ {
+ /* Generate an INF with the same sign. */
+ sim_fpu_inv (&out, &in);
+ VAL2REG (&out, reg_out);
+ }
+ break;
+
+ default:
+ abort ();
+ }
+
+ fpu_check_signal_exception (sd, cpu, cia);
+}
+
+static inline reg_t
+cmp2fcc (int res)
+{
+ switch (res)
+ {
+ case SIM_FPU_IS_SNAN:
+ case SIM_FPU_IS_QNAN:
+ return FCC_U;
+
+ case SIM_FPU_IS_NINF:
+ case SIM_FPU_IS_NNUMBER:
+ case SIM_FPU_IS_NDENORM:
+ return FCC_L;
+
+ case SIM_FPU_IS_PINF:
+ case SIM_FPU_IS_PNUMBER:
+ case SIM_FPU_IS_PDENORM:
+ return FCC_G;
+
+ case SIM_FPU_IS_NZERO:
+ case SIM_FPU_IS_PZERO:
+ return FCC_E;
+
+ default:
+ abort ();
+ }
+}
+
+/* Implement a 32/64 bit FP compare, setting the FPCR status and/or
+ exception bits as specified. */
+void
+fpu_cmp (SIM_DESC sd, sim_cpu *cpu, sim_cia cia,
+ const void *reg_in1, const void *reg_in2,
+ const struct fp_prec_t *ops)
+{
+ sim_fpu m, n;
+
+ REG2VAL (reg_in1, &m);
+ REG2VAL (reg_in2, &n);
+ FPCR &= ~ EC_MASK;
+ FPCR &= ~ FCC_MASK;
+ ROUND (&m);
+ ROUND (&n);
+ if (sim_fpu_is_snan (&m) || sim_fpu_is_snan (&n))
+ {
+ if (FPCR & EE_V)
+ FPCR |= EC_V;
+ else
+ FPCR |= FCC_U;
+ }
+ else
+ FPCR |= cmp2fcc (sim_fpu_cmp (&m, &n));
+
+ fpu_check_signal_exception (sd, cpu, cia);
+}
+
+/* Implement a 32/64 bit FP add, setting FP exception bits when
+ appropriate. */
+void
+fpu_add (SIM_DESC sd, sim_cpu *cpu, sim_cia cia,
+ const void *reg_in1, const void *reg_in2,
+ void *reg_out, const struct fp_prec_t *ops)
+{
+ sim_fpu m, n, r;
+
+ REG2VAL (reg_in1, &m);
+ REG2VAL (reg_in2, &n);
+ ROUND (&m);
+ ROUND (&n);
+ FPCR &= ~ EC_MASK;
+ if (sim_fpu_is_snan (&m) || sim_fpu_is_snan (&n)
+ || (sim_fpu_is (&m) == SIM_FPU_IS_PINF
+ && sim_fpu_is (&n) == SIM_FPU_IS_NINF)
+ || (sim_fpu_is (&m) == SIM_FPU_IS_NINF
+ && sim_fpu_is (&n) == SIM_FPU_IS_PINF))
+ {
+ if (FPCR & EE_V)
+ FPCR |= EC_V;
+ else
+ VAL2REG (&sim_fpu_qnan, reg_out);
+ }
+ else
+ {
+ sim_fpu_status stat = sim_fpu_add (&r, &m, &n);
+ stat |= ROUND (&r);
+ if (fpu_status_ok (stat))
+ VAL2REG (&r, reg_out);
+ }
+
+ fpu_check_signal_exception (sd, cpu, cia);
+}
+
+/* Implement a 32/64 bit FP sub, setting FP exception bits when
+ appropriate. */
+void
+fpu_sub (SIM_DESC sd, sim_cpu *cpu, sim_cia cia,
+ const void *reg_in1, const void *reg_in2,
+ void *reg_out, const struct fp_prec_t *ops)
+{
+ sim_fpu m, n, r;
+
+ REG2VAL (reg_in1, &m);
+ REG2VAL (reg_in2, &n);
+ ROUND (&m);
+ ROUND (&n);
+ FPCR &= ~ EC_MASK;
+ if (sim_fpu_is_snan (&m) || sim_fpu_is_snan (&n)
+ || (sim_fpu_is (&m) == SIM_FPU_IS_PINF
+ && sim_fpu_is (&n) == SIM_FPU_IS_PINF)
+ || (sim_fpu_is (&m) == SIM_FPU_IS_NINF
+ && sim_fpu_is (&n) == SIM_FPU_IS_NINF))
+ {
+ if (FPCR & EE_V)
+ FPCR |= EC_V;
+ else
+ VAL2REG (&sim_fpu_qnan, reg_out);
+ }
+ else
+ {
+ sim_fpu_status stat = sim_fpu_sub (&r, &m, &n);
+ stat |= ROUND (&r);
+ if (fpu_status_ok (stat))
+ VAL2REG (&r, reg_out);
+ }
+
+ fpu_check_signal_exception (sd, cpu, cia);
+}
+
+/* Implement a 32/64 bit FP mul, setting FP exception bits when
+ appropriate. */
+void
+fpu_mul (SIM_DESC sd, sim_cpu *cpu, sim_cia cia,
+ const void *reg_in1, const void *reg_in2,
+ void *reg_out, const struct fp_prec_t *ops)
+{
+ sim_fpu m, n, r;
+
+ REG2VAL (reg_in1, &m);
+ REG2VAL (reg_in2, &n);
+ ROUND (&m);
+ ROUND (&n);
+ FPCR &= ~ EC_MASK;
+ if (sim_fpu_is_snan (&m) || sim_fpu_is_snan (&n)
+ || (sim_fpu_is_infinity (&m) && sim_fpu_is_zero (&n))
+ || (sim_fpu_is_zero (&m) && sim_fpu_is_infinity (&n)))
+ {
+ if (FPCR & EE_V)
+ FPCR |= EC_V;
+ else
+ VAL2REG (&sim_fpu_qnan, reg_out);
+ }
+ else
+ {
+ sim_fpu_status stat = sim_fpu_mul (&r, &m, &n);
+ stat |= ROUND (&r);
+ if (fpu_status_ok (stat))
+ VAL2REG (&r, reg_out);
+ }
+
+ fpu_check_signal_exception (sd, cpu, cia);
+}
+
+/* Implement a 32/64 bit FP div, setting FP exception bits when
+ appropriate. */
+void
+fpu_div (SIM_DESC sd, sim_cpu *cpu, sim_cia cia,
+ const void *reg_in1, const void *reg_in2,
+ void *reg_out, const struct fp_prec_t *ops)
+{
+ sim_fpu m, n, r;
+
+ REG2VAL (reg_in1, &m);
+ REG2VAL (reg_in2, &n);
+ ROUND (&m);
+ ROUND (&n);
+ FPCR &= ~ EC_MASK;
+ if (sim_fpu_is_snan (&m) || sim_fpu_is_snan (&n)
+ || (sim_fpu_is_infinity (&m) && sim_fpu_is_infinity (&n))
+ || (sim_fpu_is_zero (&m) && sim_fpu_is_zero (&n)))
+ {
+ if (FPCR & EE_V)
+ FPCR |= EC_V;
+ else
+ VAL2REG (&sim_fpu_qnan, reg_out);
+ }
+ else if (sim_fpu_is_number (&m) && sim_fpu_is_zero (&n)
+ && (FPCR & EE_Z))
+ FPCR |= EC_Z;
+ else
+ {
+ sim_fpu_status stat = sim_fpu_div (&r, &m, &n);
+ stat |= ROUND (&r);
+ if (fpu_status_ok (stat))
+ VAL2REG (&r, reg_out);
+ }
+
+ fpu_check_signal_exception (sd, cpu, cia);
+}
+
+/* Implement a 32/64 bit FP madd, setting FP exception bits when
+ appropriate. */
+void
+fpu_fmadd (SIM_DESC sd, sim_cpu *cpu, sim_cia cia,
+ const void *reg_in1, const void *reg_in2, const void *reg_in3,
+ void *reg_out, const struct fp_prec_t *ops)
+{
+ sim_fpu m1, m2, m, n, r;
+
+ REG2VAL (reg_in1, &m1);
+ REG2VAL (reg_in2, &m2);
+ REG2VAL (reg_in3, &n);
+ ROUND (&m1);
+ ROUND (&m2);
+ ROUND (&n);
+ FPCR &= ~ EC_MASK;
+ if (sim_fpu_is_snan (&m1) || sim_fpu_is_snan (&m2) || sim_fpu_is_snan (&n)
+ || (sim_fpu_is_infinity (&m1) && sim_fpu_is_zero (&m2))
+ || (sim_fpu_is_zero (&m1) && sim_fpu_is_infinity (&m2)))
+ {
+ invalid_operands:
+ if (FPCR & EE_V)
+ FPCR |= EC_V;
+ else
+ VAL2REG (&sim_fpu_qnan, reg_out);
+ }
+ else
+ {
+ sim_fpu_status stat = sim_fpu_mul (&m, &m1, &m2);
+
+ if (sim_fpu_is_infinity (&m) && sim_fpu_is_infinity (&n)
+ && sim_fpu_sign (&m) != sim_fpu_sign (&n))
+ goto invalid_operands;
+
+ stat |= sim_fpu_add (&r, &m, &n);
+ stat |= ROUND (&r);
+ if (fpu_status_ok (stat))
+ VAL2REG (&r, reg_out);
+ }
+
+ fpu_check_signal_exception (sd, cpu, cia);
+}
+
+/* Implement a 32/64 bit FP msub, setting FP exception bits when
+ appropriate. */
+void
+fpu_fmsub (SIM_DESC sd, sim_cpu *cpu, sim_cia cia,
+ const void *reg_in1, const void *reg_in2, const void *reg_in3,
+ void *reg_out, const struct fp_prec_t *ops)
+{
+ sim_fpu m1, m2, m, n, r;
+
+ REG2VAL (reg_in1, &m1);
+ REG2VAL (reg_in2, &m2);
+ REG2VAL (reg_in3, &n);
+ ROUND (&m1);
+ ROUND (&m2);
+ ROUND (&n);
+ FPCR &= ~ EC_MASK;
+ if (sim_fpu_is_snan (&m1) || sim_fpu_is_snan (&m2) || sim_fpu_is_snan (&n)
+ || (sim_fpu_is_infinity (&m1) && sim_fpu_is_zero (&m2))
+ || (sim_fpu_is_zero (&m1) && sim_fpu_is_infinity (&m2)))
+ {
+ invalid_operands:
+ if (FPCR & EE_V)
+ FPCR |= EC_V;
+ else
+ VAL2REG (&sim_fpu_qnan, reg_out);
+ }
+ else
+ {
+ sim_fpu_status stat = sim_fpu_mul (&m, &m1, &m2);
+
+ if (sim_fpu_is_infinity (&m) && sim_fpu_is_infinity (&n)
+ && sim_fpu_sign (&m) == sim_fpu_sign (&n))
+ goto invalid_operands;
+
+ stat |= sim_fpu_sub (&r, &m, &n);
+ stat |= ROUND (&r);
+ if (fpu_status_ok (stat))
+ VAL2REG (&r, reg_out);
+ }
+
+ fpu_check_signal_exception (sd, cpu, cia);
+}
+
+/* Implement a 32/64 bit FP nmadd, setting FP exception bits when
+ appropriate. */
+void
+fpu_fnmadd (SIM_DESC sd, sim_cpu *cpu, sim_cia cia,
+ const void *reg_in1, const void *reg_in2, const void *reg_in3,
+ void *reg_out, const struct fp_prec_t *ops)
+{
+ sim_fpu m1, m2, m, mm, n, r;
+
+ REG2VAL (reg_in1, &m1);
+ REG2VAL (reg_in2, &m2);
+ REG2VAL (reg_in3, &n);
+ ROUND (&m1);
+ ROUND (&m2);
+ ROUND (&n);
+ FPCR &= ~ EC_MASK;
+ if (sim_fpu_is_snan (&m1) || sim_fpu_is_snan (&m2) || sim_fpu_is_snan (&n)
+ || (sim_fpu_is_infinity (&m1) && sim_fpu_is_zero (&m2))
+ || (sim_fpu_is_zero (&m1) && sim_fpu_is_infinity (&m2)))
+ {
+ invalid_operands:
+ if (FPCR & EE_V)
+ FPCR |= EC_V;
+ else
+ VAL2REG (&sim_fpu_qnan, reg_out);
+ }
+ else
+ {
+ sim_fpu_status stat = sim_fpu_mul (&m, &m1, &m2);
+
+ if (sim_fpu_is_infinity (&m) && sim_fpu_is_infinity (&n)
+ && sim_fpu_sign (&m) == sim_fpu_sign (&n))
+ goto invalid_operands;
+
+ stat |= sim_fpu_neg (&mm, &m);
+ stat |= sim_fpu_add (&r, &mm, &n);
+ stat |= ROUND (&r);
+ if (fpu_status_ok (stat))
+ VAL2REG (&r, reg_out);
+ }
+
+ fpu_check_signal_exception (sd, cpu, cia);
+}
+
+/* Implement a 32/64 bit FP nmsub, setting FP exception bits when
+ appropriate. */
+void
+fpu_fnmsub (SIM_DESC sd, sim_cpu *cpu, sim_cia cia,
+ const void *reg_in1, const void *reg_in2, const void *reg_in3,
+ void *reg_out, const struct fp_prec_t *ops)
+{
+ sim_fpu m1, m2, m, mm, n, r;
+
+ REG2VAL (reg_in1, &m1);
+ REG2VAL (reg_in2, &m2);
+ REG2VAL (reg_in3, &n);
+ ROUND (&m1);
+ ROUND (&m2);
+ ROUND (&n);
+ FPCR &= ~ EC_MASK;
+ if (sim_fpu_is_snan (&m1) || sim_fpu_is_snan (&m2) || sim_fpu_is_snan (&n)
+ || (sim_fpu_is_infinity (&m1) && sim_fpu_is_zero (&m2))
+ || (sim_fpu_is_zero (&m1) && sim_fpu_is_infinity (&m2)))
+ {
+ invalid_operands:
+ if (FPCR & EE_V)
+ FPCR |= EC_V;
+ else
+ VAL2REG (&sim_fpu_qnan, reg_out);
+ }
+ else
+ {
+ sim_fpu_status stat = sim_fpu_mul (&m, &m1, &m2);
+
+ if (sim_fpu_is_infinity (&m) && sim_fpu_is_infinity (&n)
+ && sim_fpu_sign (&m) != sim_fpu_sign (&n))
+ goto invalid_operands;
+
+ stat |= sim_fpu_neg (&mm, &m);
+ stat |= sim_fpu_sub (&r, &mm, &n);
+ stat |= ROUND (&r);
+ if (fpu_status_ok (stat))
+ VAL2REG (&r, reg_out);
+ }
+
+ fpu_check_signal_exception (sd, cpu, cia);
+}
:option:::hi-bit-nr:7
:model:::mn10300:mn10300:
:model:::am33:am33:
+:model:::am33_2:am33_2:
// What do we do with an illegal instruction?
:internal::::illegal:
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_8000 (); */
signed32 immed = EXTEND8 (IMM8);
"mov"
*mn10300
*am33
+*am33_2
{
PC = cia;
/* OP_80 (); */
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_F1E0 (); */
PC = cia;
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_F1D0 (); */
PC = cia;
"mov"
*mn10300
*am33
+*am33_2
{
PC = cia;
/* OP_9000 (); */
"mov"
*mn10300
*am33
+*am33_2
{
PC = cia;
/* OP_90 (); */
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_3C (); */
PC = cia;
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_F2F0 (); */
PC = cia;
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_F2E4 (); */
PC = cia;
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_F2F3 (); */
PC = cia;
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_F2E0 (); */
PC = cia;
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_F2F2 (); */
PC = cia;
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_70 (); */
PC = cia;
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_F80000 (); */
PC = cia;
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_FA000000 (); */
PC = cia;
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_FC000000 (); */
PC = cia;
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_5800 (); */
PC = cia;
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_FAB40000 (); */
PC = cia;
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_FCB40000 (); */
PC = cia;
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_F300 (); */
PC = cia;
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_300000 (); */
PC = cia;
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_FCA40000 (); */
PC = cia;
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_F000 (); */
PC = cia;
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_F82000 (); */
PC = cia;
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_FA200000 (); */
PC = cia;
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_FC200000 (); */
PC = cia;
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_5C00 (); */
PC = cia;
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_FAB00000 (); */
PC = cia;
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_FCB00000 (); */
PC = cia;
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_F380 (); */
PC = cia;
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_FAA00000 (); */
PC = cia;
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_FCA00000 (); */
PC = cia;
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_F8F000 (); */
PC = cia;
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_60 (); */
PC = cia;
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_F81000 (); */
PC = cia;
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_FA100000 (); */
PC = cia;
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_FC100000 (); */
PC = cia;
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_4200 (); */
PC = cia;
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_FA910000 (); */
PC = cia;
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_FC910000 (); */
PC = cia;
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_F340 (); */
PC = cia;
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_10000 (); */
PC = cia;
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_FC810000 (); */
PC = cia;
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_F010 (); */
PC = cia;
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_F83000 (); */
PC = cia;
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_FA300000 (); */
PC = cia;
"mov"
*mn10300
*am33
+*am33_2
{
/* OP_FC300000 (); */
PC = cia;
*mn10300
*am33
+*am33_2
{
/* OP_4300 (); */
*mn10300
*am33
+*am33_2
{
/* OP_FA900000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_FC900000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_F3C0 (); */
*mn10300
*am33
+*am33_2
{
/* OP_FA800000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_FC800000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_F8F400 (); */
*mn10300
*am33
+*am33_2
{
/* OP_2C0000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_FCCC0000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_240000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_FCDC0000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_F040 (); */
*mn10300
*am33
+*am33_2
{
/* OP_F84000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_FA400000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_FC400000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_F8B800 (); */
*mn10300
*am33
+*am33_2
{
/* OP_FAB80000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_FCB80000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_F400 (); */
*mn10300
*am33
+*am33_2
{
/* OP_340000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_FCA80000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_F050 (); */
*mn10300
*am33
+*am33_2
{
/* OP_F85000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_FA500000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_FC500000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_F89200 (); */
*mn10300
*am33
+*am33_2
{
/* OP_FA920000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_FC920000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_F440 (); */
*mn10300
*am33
+*am33_2
{
/* OP_20000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_FC820000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_F060 (); */
*mn10300
*am33
+*am33_2
{
/* OP_F86000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_FA600000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_FC600000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_F8BC00 (); */
*mn10300
*am33
+*am33_2
{
/* OP_FABC0000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_FCBC0000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_F480 (); */
*mn10300
*am33
+*am33_2
{
/* OP_380000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_FCAC0000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_F070 (); */
*mn10300
*am33
+*am33_2
{
/* OP_F87000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_FA700000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_FC700000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_F89300 (); */
*mn10300
*am33
+*am33_2
{
/* OP_FA930000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_FC930000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_F4C0 (); */
*mn10300
*am33
+*am33_2
{
/* OP_30000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_FC830000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_F2D0 (); */
*mn10300
*am33
+*am33_2
{
/* OP_10 (); */
*mn10300
*am33
+*am33_2
{
/* OP_14 (); */
*mn10300
*am33
+*am33_2
{
/* OP_18 (); */
*mn10300
*am33
+*am33_2
{
/* OP_1C (); */
*mn10300
*am33
+*am33_2
{
/* OP_0 (); */
*mn10300
*am33
+*am33_2
{
/* OP_E0 (); */
*mn10300
*am33
+*am33_2
{
/* OP_F160 (); */
*mn10300
*am33
+*am33_2
{
/* OP_F150 (); */
*mn10300
*am33
+*am33_2
{
/* OP_F170 (); */
*mn10300
*am33
+*am33_2
{
/* OP_2800 (); */
*mn10300
*am33
+*am33_2
{
/* OP_FAC00000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_FCC00000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_2000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_FAD00000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_FCD00000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_F8FE00 (); */
*mn10300
*am33
+*am33_2
{
/* OP_FAFE0000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_FCFE0000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_F140 (); */
*mn10300
*am33
+*am33_2
{
/* OP_F100 (); */
*mn10300
*am33
+*am33_2
{
/* OP_F120 (); */
*mn10300
*am33
+*am33_2
{
/* OP_F110 (); */
*mn10300
*am33
+*am33_2
{
/* OP_F130 (); */
*mn10300
*am33
+*am33_2
{
/* OP_FCC40000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_FCD40000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_F180 (); */
*mn10300
*am33
+*am33_2
{
/* OP_F240 (); */
*mn10300
*am33
+*am33_2
{
/* OP_F250 (); */
*mn10300
*am33
+*am33_2
{
/* OP_F260 (); */
*mn10300
*am33
+*am33_2
{
/* OP_F270 (); */
*mn10300
*am33
+*am33_2
{
/* OP_40 (); */
*mn10300
*am33
+*am33_2
{
/* OP_41 (); */
*mn10300
*am33
+*am33_2
{
/* OP_50 (); */
*mn10300
*am33
+*am33_2
{
PC = cia;
*mn10300
*am33
+*am33_2
{
PC = cia;
*mn10300
*am33
+*am33_2
{
/* OP_F1A0 (); */
*mn10300
*am33
+*am33_2
{
/* OP_F190 (); */
*mn10300
*am33
+*am33_2
{
PC = cia;
*mn10300
*am33
+*am33_2
{
PC = cia;
*mn10300
*am33
+*am33_2
{
/* OP_FAC80000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_FCC80000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_FAD80000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_FCD80000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_F200 (); */
*mn10300
*am33
+*am33_2
{
/* OP_F8E000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_FAE00000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_FCE00000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_FAFC0000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_F210 (); */
*mn10300
*am33
+*am33_2
{
/* OP_F8E400 (); */
*mn10300
*am33
+*am33_2
{
/* OP_FAE40000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_FCE40000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_FAFD0000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_F220 (); */
*mn10300
*am33
+*am33_2
{
/* OP_FAE80000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_FCE80000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_F230 (); */
*mn10300
*am33
+*am33_2
{
/* OP_F8EC00 (); */
*mn10300
*am33
+*am33_2
{
/* OP_FAEC0000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_FCEC0000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_FE020000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_FAF80000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_F080 (); */
*mn10300
*am33
+*am33_2
{
/* OP_FE000000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_FAF00000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_F090 (); */
*mn10300
*am33
+*am33_2
{
/* OP_FE010000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_FAF40000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_F2B0 (); */
*mn10300
*am33
+*am33_2
{
/* OP_F8C800 (); */
*mn10300
*am33
+*am33_2
{
/* OP_F2A0 (); */
*mn10300
*am33
+*am33_2
{
/* OP_F8C400 (); */
*mn10300
*am33
+*am33_2
{
/* OP_F290 (); */
*mn10300
*am33
+*am33_2
{
/* OP_F8C000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_54 (); */
*mn10300
*am33
+*am33_2
{
/* OP_F284 (); */
*mn10300
*am33
+*am33_2
{
/* OP_F280 (); */
*mn10300
*am33
+*am33_2
{
/* OP_C800 (); */
*mn10300
*am33
+*am33_2
{
/* OP_C900 (); */
*mn10300
*am33
+*am33_2
{
/* OP_C100 (); */
*mn10300
*am33
+*am33_2
{
/* OP_C200 (); */
*mn10300
*am33
+*am33_2
{
/* OP_C300 (); */
*mn10300
*am33
+*am33_2
{
/* OP_C000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_C500 (); */
*mn10300
*am33
+*am33_2
{
/* OP_C600 (); */
*mn10300
*am33
+*am33_2
{
/* OP_C700 (); */
*mn10300
*am33
+*am33_2
{
/* OP_C400 (); */
*mn10300
*am33
+*am33_2
{
/* OP_F8E800 (); */
*mn10300
*am33
+*am33_2
{
/* OP_F8E900 (); */
*mn10300
*am33
+*am33_2
{
/* OP_F8EA00 (); */
*mn10300
*am33
+*am33_2
{
/* OP_F8EB00 (); */
*mn10300
*am33
+*am33_2
{
/* OP_CA00 (); */
*mn10300
*am33
+*am33_2
{
/* OP_D8 (); */
*mn10300
*am33
+*am33_2
{
/* OP_D9 (); */
*mn10300
*am33
+*am33_2
{
/* OP_D1 (); */
*mn10300
*am33
+*am33_2
{
/* OP_D2 (); */
*mn10300
*am33
+*am33_2
{
/* OP_D3 (); */
*mn10300
*am33
+*am33_2
{
/* OP_D0 (); */
*mn10300
*am33
+*am33_2
{
/* OP_D5 (); */
*mn10300
*am33
+*am33_2
{
/* OP_D6 (); */
*mn10300
*am33
+*am33_2
{
/* OP_D7 (); */
*mn10300
*am33
+*am33_2
{
/* OP_D4 (); */
*mn10300
*am33
+*am33_2
{
/* OP_DA (); */
*mn10300
*am33
+*am33_2
{
/* OP_DB (); */
*mn10300
*am33
+*am33_2
{
/* OP_F0F4 (); */
*mn10300
*am33
+*am33_2
{
/* OP_CC0000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_DC000000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_F0F0 (); */
*mn10300
*am33
+*am33_2
{
/* OP_FAFF0000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_FCFF0000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_F0FC (); */
*mn10300
*am33
+*am33_2
{
/* OP_F0FD (); */
*mn10300
*am33
+*am33_2
{
/* OP_F0FE (); */
*mn10300
*am33
+*am33_2
{
/* OP_F0FF (); */
*mn10300
*am33
+*am33_2
{
/* OP_CB (); */
*mn10300
*am33
+*am33_2
{
/* OP_F6F0 (); */
*mn10300
*am33
+*am33_2
{
/* OP_F600 (); */
*mn10300
*am33
+*am33_2
{
/* OP_F90000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_FB000000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_FD000000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_F610 (); */
*mn10300
*am33
+*am33_2
{
/* OP_F91400 (); */
*mn10300
*am33
+*am33_2
{
/* OP_FB140000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_FD140000 (); */
*mn10300
*am33
+*am33_2
{
/* OP_F640 (); */
*mn10300
*am33
+*am33_2
{
/* OP_F650 (); */
*mn10300
*am33
+*am33_2
{
/* OP_F670 (); */
*mn10300
*am33
+*am33_2
{
/* OP_F0C0 (); */
*mn10300
*am33
+*am33_2
{
/* OP_FF (); */
*mn10300
*am33
+*am33_2
{
/* OP_CE00 (); */
}
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
+ || STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2
)
{
if (mask & 0x1)
*mn10300
*am33
+*am33_2
{
/* OP_CF00 (); */
mask = REGS;
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
+ || STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2
)
{
if (mask & 0x4)
*mn10300
*am33
+*am33_2
{
/* OP_CD000000 (); */
mask = REGS;
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
+ || STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2
)
{
if (mask & 0x4)
*mn10300
*am33
+*am33_2
{
/* OP_DD000000 (); */
mask = REGS;
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
+ || STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2
)
{
if (mask & 0x4)
*mn10300
*am33
+*am33_2
{
/* OP_DF0000 (); */
mask = REGS;
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
+ || STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2
)
{
*mn10300
*am33
+*am33_2
{
/* OP_DE0000 (); */
mask = REGS;
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
+ || STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2
)
{
#include <limits.h>
#include "gdb/remote-sim.h"
#include "bfd.h"
+#include "sim-fpu.h"
#ifndef INLINE
#ifdef __GNUC__
# endif
#endif
+typedef struct
+{
+ uint32 low, high;
+} dword;
typedef uint32 reg_t;
struct simops
reg_t regs[32]; /* registers, d0-d3, a0-a3, sp, pc, mdr, psw,
lir, lar, mdrq, plus some room for processor
specific regs. */
+ union
+ {
+ reg_t fs[32]; /* FS0-31 */
+ dword fd[16]; /* FD0,2,...,30 */
+ } fpregs;
uint8 *mem; /* main memory */
int exception;
int exited;
#define REG_MCRL 27
#define REG_MCVF 28
+#define REG_FPCR 29
+
+#define FPCR (State.regs[REG_FPCR])
+
+#define FCC_MASK LSMASK (21, 18)
+#define RM_MASK LSMASK (17, 16) /* Must always be zero. */
+#define EC_MASK LSMASK (14, 10)
+#define EE_MASK LSMASK ( 9, 5)
+#define EF_MASK LSMASK ( 4, 0)
+#define FPCR_MASK (FCC_MASK | EC_MASK | EE_MASK | EF_MASK)
+
+#define FCC_L LSBIT (21)
+#define FCC_G LSBIT (20)
+#define FCC_E LSBIT (19)
+#define FCC_U LSBIT (18)
+
+#define EC_V LSBIT (14)
+#define EC_Z LSBIT (13)
+#define EC_O LSBIT (12)
+#define EC_U LSBIT (11)
+#define EC_I LSBIT (10)
+
+#define EE_V LSBIT (9)
+#define EE_Z LSBIT (8)
+#define EE_O LSBIT (7)
+#define EE_U LSBIT (6)
+#define EE_I LSBIT (5)
+
+#define EF_V LSBIT (4)
+#define EF_Z LSBIT (3)
+#define EF_O LSBIT (2)
+#define EF_U LSBIT (1)
+#define EF_I LSBIT (0)
+
+#define PSW_FE LSBIT(20)
+#define FPU_DISABLED !(PSW & PSW_FE)
+
+#define XS2FS(X,S) State.fpregs.fs[((X<<4)|(S))]
+#define AS2FS(A,S) State.fpregs.fs[((A<<2)|(S))]
+#define Xf2FD(X,f) State.fpregs.fd[((X<<3)|(f))]
+
+#define FS2FPU(FS,F) sim_fpu_32to (&(F), (FS))
+#define FD2FPU(FD,F) sim_fpu_232to (&(F), ((FD).high), ((FD).low))
+#define FPU2FS(F,FS) sim_fpu_to32 (&(FS), &(F))
+#define FPU2FD(F,FD) sim_fpu_to232 (&((FD).high), &((FD).low), &(F))
+
#ifdef _WIN32
#define SIGTRAP 5
#define SIGQUIT 3
#define load_word(ADDR) \
sim_core_read_unaligned_4 (STATE_CPU (simulator, 0), PC, read_map, (ADDR))
+#define load_dword(ADDR) \
+u642dw (sim_core_read_unaligned_8 (STATE_CPU (simulator, 0), \
+ PC, read_map, (ADDR)))
+
+static INLINE dword
+u642dw (unsigned64 dw)
+{
+ dword r;
+
+ r.low = (unsigned32)dw;
+ r.high = (unsigned32)(dw >> 32);
+ return r;
+}
+
#define store_byte(ADDR, DATA) \
sim_core_write_unaligned_1 (STATE_CPU (simulator, 0), \
PC, write_map, (ADDR), (DATA))
#define store_word(ADDR, DATA) \
sim_core_write_unaligned_4 (STATE_CPU (simulator, 0), \
PC, write_map, (ADDR), (DATA))
+#define store_dword(ADDR, DATA) \
+sim_core_write_unaligned_8 (STATE_CPU (simulator, 0), \
+ PC, write_map, (ADDR), dw2u64 (DATA))
+
+static INLINE unsigned64
+dw2u64 (dword data)
+{
+ return data.low | (((unsigned64)data.high) << 32);
+}
/* Function declarations. */
void mn10300_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word pc);
void mn10300_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception);
void mn10300_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception);
+
+void fpu_disabled_exception (SIM_DESC, sim_cpu *, address_word);
+void fpu_unimp_exception (SIM_DESC, sim_cpu *, address_word);
+void fpu_check_signal_exception (SIM_DESC, sim_cpu *, address_word);
+
+extern const struct fp_prec_t
+{
+ void (* reg2val) (const void *, sim_fpu *);
+ int (* round) (sim_fpu *);
+ void (* val2reg) (const sim_fpu *, void *);
+} fp_single_prec, fp_double_prec;
+
+#define FP_SINGLE (&fp_single_prec)
+#define FP_DOUBLE (&fp_double_prec)
+
+void fpu_rsqrt (SIM_DESC, sim_cpu *, address_word, const void *, void *, const struct fp_prec_t *);
+void fpu_sqrt (SIM_DESC, sim_cpu *, address_word, const void *, void *, const struct fp_prec_t *);
+void fpu_cmp (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const struct fp_prec_t *);
+void fpu_add (SIM_DESC, sim_cpu *, address_word, const void *, const void *, void *, const struct fp_prec_t *);
+void fpu_sub (SIM_DESC, sim_cpu *, address_word, const void *, const void *, void *, const struct fp_prec_t *);
+void fpu_mul (SIM_DESC, sim_cpu *, address_word, const void *, const void *, void *, const struct fp_prec_t *);
+void fpu_div (SIM_DESC, sim_cpu *, address_word, const void *, const void *, void *, const struct fp_prec_t *);
+void fpu_fmadd (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const void *, void *, const struct fp_prec_t *);
+void fpu_fmsub (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const void *, void *, const struct fp_prec_t *);
+void fpu_fnmadd (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const void *, void *, const struct fp_prec_t *);
+void fpu_fnmsub (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const void *, void *, const struct fp_prec_t *);
projects / binutils-gdb.git / commitdiff