ac: add load_patch_vertices_in() to the abi
authorTimothy Arceri <tarceri@itsqueeze.com>
Wed, 10 Jan 2018 06:01:10 +0000 (17:01 +1100)
committerTimothy Arceri <tarceri@itsqueeze.com>
Thu, 11 Jan 2018 03:28:37 +0000 (14:28 +1100)
Fixes the follow test for radeonsi nir:

tests/spec/arb_tessellation_shader/execution/quads.shader_test

Also stops 8 other tests from crashing, they now just fail e.g.

tcs-output-array-float-index-rd-after-barrier.shader_test

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
src/amd/common/ac_nir_to_llvm.c
src/amd/common/ac_shader_abi.h
src/gallium/drivers/radeonsi/si_shader.c

index 8301b16057d501027dd72853c62924ece8b9fee1..7153c9708d418c723ffa3c5c352b6ffdcb4e2ed0 100644 (file)
@@ -4166,6 +4166,13 @@ load_tess_coord(struct ac_shader_abi *abi, LLVMTypeRef type,
        return LLVMBuildBitCast(ctx->builder, result, type, "");
 }
 
+static LLVMValueRef
+load_patch_vertices_in(struct ac_shader_abi *abi)
+{
+       struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
+       return LLVMConstInt(ctx->ac.i32, ctx->options->key.tcs.input_vertices, false);
+}
+
 static void visit_intrinsic(struct ac_nir_context *ctx,
                             nir_intrinsic_instr *instr)
 {
@@ -4366,7 +4373,7 @@ static void visit_intrinsic(struct ac_nir_context *ctx,
                result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_INNER);
                break;
        case nir_intrinsic_load_patch_vertices_in:
-               result = LLVMConstInt(ctx->ac.i32, ctx->nctx->options->key.tcs.input_vertices, false);
+               result = ctx->abi->load_patch_vertices_in(ctx->abi);
                break;
        default:
                fprintf(stderr, "Unknown intrinsic: ");
@@ -6698,11 +6705,13 @@ LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
                        ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
                        ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
                        ctx.abi.load_tess_inputs = load_tcs_input;
+                       ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
                        ctx.abi.store_tcs_outputs = store_tcs_output;
                } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
                        ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
                        ctx.abi.load_tess_inputs = load_tes_input;
                        ctx.abi.load_tess_coord = load_tess_coord;
+                       ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
                } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
                        if (shader_info->info.vs.needs_instance_id) {
                                if (ctx.ac.chip_class == GFX9 &&
index e3a47089a526506fcd5e6686cb7bad9f806c86f3..06e61207ec238a6281657ec69c71fd94e75d6ae5 100644 (file)
@@ -103,6 +103,8 @@ struct ac_shader_abi {
                                        LLVMTypeRef type,
                                        unsigned num_components);
 
+       LLVMValueRef (*load_patch_vertices_in)(struct ac_shader_abi *abi);
+
        LLVMValueRef (*load_tess_level)(struct ac_shader_abi *abi,
                                        unsigned varying_id);
 
index 86f3f7a8ba2208861b50cdc282e2034ef0fcb90e..dd635ae203593f6e5e1c9fbb5dd90eedca381b1d 100644 (file)
@@ -1955,6 +1955,17 @@ static LLVMValueRef si_load_tess_level(struct ac_shader_abi *abi,
 
 }
 
+static LLVMValueRef si_load_patch_vertices_in(struct ac_shader_abi *abi)
+{
+       struct si_shader_context *ctx = si_shader_context_from_abi(abi);
+       if (ctx->type == PIPE_SHADER_TESS_CTRL)
+               return unpack_param(ctx, ctx->param_tcs_out_lds_layout, 26, 6);
+       else if (ctx->type == PIPE_SHADER_TESS_EVAL)
+               return get_num_tcs_out_vertices(ctx);
+       else
+               assert(!"invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
+}
+
 void si_load_system_value(struct si_shader_context *ctx,
                          unsigned index,
                          const struct tgsi_full_declaration *decl)
@@ -2063,12 +2074,7 @@ void si_load_system_value(struct si_shader_context *ctx,
                break;
 
        case TGSI_SEMANTIC_VERTICESIN:
-               if (ctx->type == PIPE_SHADER_TESS_CTRL)
-                       value = unpack_param(ctx, ctx->param_tcs_out_lds_layout, 26, 6);
-               else if (ctx->type == PIPE_SHADER_TESS_EVAL)
-                       value = get_num_tcs_out_vertices(ctx);
-               else
-                       assert(!"invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
+               value = si_load_patch_vertices_in(&ctx->abi);
                break;
 
        case TGSI_SEMANTIC_TESSINNER:
@@ -5986,6 +5992,7 @@ static bool si_compile_tgsi_main(struct si_shader_context *ctx,
                bld_base->emit_store = store_output_tcs;
                ctx->abi.store_tcs_outputs = si_nir_store_output_tcs;
                ctx->abi.emit_outputs = si_llvm_emit_tcs_epilogue;
+               ctx->abi.load_patch_vertices_in = si_load_patch_vertices_in;
                bld_base->emit_epilogue = si_tgsi_emit_epilogue;
                break;
        case PIPE_SHADER_TESS_EVAL:
@@ -5993,6 +6000,7 @@ static bool si_compile_tgsi_main(struct si_shader_context *ctx,
                ctx->abi.load_tess_inputs = si_nir_load_input_tes;
                ctx->abi.load_tess_coord = si_load_tess_coord;
                ctx->abi.load_tess_level = si_load_tess_level;
+               ctx->abi.load_patch_vertices_in = si_load_patch_vertices_in;
                if (shader->key.as_es)
                        ctx->abi.emit_outputs = si_llvm_emit_es_epilogue;
                else