i965/fs: Properly report regs_written from SAMPLEINFO

The previous behavior would only allocate one register and then write
four thus potentially stomping three innocent bystanders.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index 725f5dac0c7bc62252aae1cc00791e3715737d2d..43d374534256abdae27e5ff8947e27a9352a8ffa 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
@@ -3205,12 +3205,18 @@ fs_visitor::nir_emit_texture(const fs_builder &bld, nir_tex_instr *instr)
    case nir_texop_txs: op = ir_txs; break;
    case nir_texop_texture_samples: {
       fs_reg dst = retype(get_nir_dest(instr->dest), BRW_REGISTER_TYPE_D);
-      fs_inst *inst = bld.emit(SHADER_OPCODE_SAMPLEINFO, dst,
+
+      fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_D, 4);
+      fs_inst *inst = bld.emit(SHADER_OPCODE_SAMPLEINFO, tmp,
                                bld.vgrf(BRW_REGISTER_TYPE_D, 1),
                                texture_reg, texture_reg);
       inst->mlen = 1;
       inst->header_size = 1;
       inst->base_mrf = -1;
+      inst->regs_written = 4 * (dispatch_width / 8);
+
+      /* Pick off the one component we care about */
+      bld.MOV(dst, tmp);
       return;
    }
    case nir_texop_samples_identical: op = ir_samples_identical; break;

diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp
index d9e654c4d4f3e9c070abb29f824d105a01f279ab..80fddfc1bd4163a16a8f0cd4a2e438627f4ebafe 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp
+++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
@@ -757,7 +757,8 @@ backend_instruction::is_tex() const
            opcode == SHADER_OPCODE_TXS ||
            opcode == SHADER_OPCODE_LOD ||
            opcode == SHADER_OPCODE_TG4 ||
-           opcode == SHADER_OPCODE_TG4_OFFSET);
+           opcode == SHADER_OPCODE_TG4_OFFSET ||
+           opcode == SHADER_OPCODE_SAMPLEINFO);
 }
 
 bool