Register outputs on execute2

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>

diff --git a/execute2.vhdl b/execute2.vhdl
index 851e58fae64015c61f7058fc38e85572ff54182a..c7cf61e0a631daf2eb8c3e9fa7a2506e228a7ba6 100644 (file)
--- a/execute2.vhdl
+++ b/execute2.vhdl
@@ -20,29 +20,38 @@ entity execute2 is
 end execute2;
 
 architecture behave of execute2 is
-       signal e: Execute1ToExecute2Type;
+       signal r, rin : Execute2ToWritebackType;
 begin
        execute2_0: process(clk)
        begin
-               if (rising_edge(clk)) then
-                       e <= e_in;
+               if rising_edge(clk) then
+                       r <= rin;
                end if;
        end process;
 
        execute2_1: process(all)
+               variable v : Execute2ToWritebackType;
        begin
-               e_out.valid <= e.valid;
-               e_out.write_enable <= e.write_enable;
-               e_out.write_reg <= e.write_reg;
-               e_out.write_data <= e.write_data;
-               e_out.write_cr_enable <= e.write_cr_enable;
-               e_out.write_cr_mask <= e.write_cr_mask;
-               e_out.write_cr_data <= e.write_cr_data;
-
-               if e.valid = '1' and e.rc = '1' then
-                       e_out.write_cr_enable <= '1';
-                       e_out.write_cr_mask <= num_to_fxm(0);
-                       e_out.write_cr_data <= ppc_cmpi('1', e.write_data, x"0000") & x"0000000";
+               v := rin;
+
+               v.valid := e_in.valid;
+               v.write_enable := e_in.write_enable;
+               v.write_reg := e_in.write_reg;
+               v.write_data := e_in.write_data;
+               v.write_cr_enable := e_in.write_cr_enable;
+               v.write_cr_mask := e_in.write_cr_mask;
+               v.write_cr_data := e_in.write_cr_data;
+
+               if e_in.valid = '1' and e_in.rc = '1' then
+                       v.write_cr_enable := '1';
+                       v.write_cr_mask := num_to_fxm(0);
+                       v.write_cr_data := ppc_cmpi('1', e_in.write_data, x"0000") & x"0000000";
                end if;
+
+               -- Update registers
+               rin <= v;
+
+               -- Update outputs
+               e_out <= v;
        end process;
 end;