Fixed bug in "read_verilog -ignore_redef"

diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index 551859ebfc09bf9798e60ea272975d30c3103883..ec9616be3482606f77e6741685a9f5064a290deb 100644 (file)
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -947,7 +947,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
                        if (!ignore_redef)
                                log_error("Re-definition of module `%s' at %s:%d!\n",
                                                (*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum);
-                       log_error("Ignoring re-definition of module `%s' at %s:%d!\n",
+                       log("Ignoring re-definition of module `%s' at %s:%d!\n",
                                        (*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum);
                        continue;
                }