re PR tree-optimization/85693 (Generation of SAD (Sum of Absolute Difference) instruc...

	PR target/85693
	* config/i386/sse.md (usadv64qi): New expander.

From-SVN: r260117

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 0bb6bd2d49a09f80255b0c8292c7fe0cd8038b32..9b4684c0d225390f788fac2f850c415746dd2d4d 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2018-05-10  Uros Bizjak  <ubizjak@gmail.com>
+
+       PR target/85693
+       * config/i386/sse.md (usadv64qi): New expander.
+
 2018-05-10  Segher Boessenkool  <segher@kernel.crashing.org>
 
        * config/rs6000/altivec.md (altivec_vmrghb, altivec_vmrghh,

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index ae6294e559cbb65b1e970975c2b0248a4f5a5f8d..0e625a4cc584c599fa17d348c4074ceb6ec6aa4f 100644 (file)
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -10878,6 +10878,21 @@
   DONE;
 })
 
+(define_expand "usadv64qi"
+  [(match_operand:V16SI 0 "register_operand")
+   (match_operand:V64QI 1 "register_operand")
+   (match_operand:V64QI 2 "nonimmediate_operand")
+   (match_operand:V16SI 3 "nonimmediate_operand")]
+  "TARGET_AVX512BW"
+{
+  rtx t1 = gen_reg_rtx (V8DImode);
+  rtx t2 = gen_reg_rtx (V16SImode);
+  emit_insn (gen_avx512f_psadbw (t1, operands[1], operands[2]));
+  convert_move (t2, t1, 0);
+  emit_insn (gen_addv16si3 (operands[0], t2, operands[3]));
+  DONE;
+})
+
 (define_insn "<mask_codefor>ashr<mode>3<mask_name>"
   [(set (match_operand:VI248_AVX512BW_1 0 "register_operand" "=v,v")
        (ashiftrt:VI248_AVX512BW_1