RISC-V: Pretty print values formed with lui and addiw.

The disassembler has support to pretty print values created by an lui/addi
pair, but there is no support for addiw.  There is also no support for
c.addi and c.addiw.  This patch extends the pretty printing support to
handle these 3 instructions in addition to addi.  Existing testcases serve
as tests for the new feature.

	opcodes/
	* riscv-dis.c (maybe_print_address): New arg wide.  Sign extend when
	wide is true.
	(print_insn_args): Fix calls to maybe_print_address.  Add checks for
	c.addi, c.addiw, and addiw, and call maybe_print_address for them.

	gas/
	* testsuite/gas/riscv/insn.d: Update for disassembler change.
	* testsuite/gas/li32.d, testsuite/gas/li64.d: Likwise.
	* testsuite/gas/lla64.d: Likewise.

diff --git a/gas/testsuite/gas/riscv/insn.d b/gas/testsuite/gas/riscv/insn.d
index 4edacc633686686bce4aa8dc68e56660c1359666..5b36107df2912f7909188a2ad57e2304a21b7063 100644 (file)
--- a/gas/testsuite/gas/riscv/insn.d
+++ b/gas/testsuite/gas/riscv/insn.d
@@ -22,7 +22,7 @@ Disassembly of section .text:
 [^:]+:[        ]+fddff56f[     ]+jal[  ]+a0,0 \<target\>
 [^:]+: R_RISCV_JAL[    ]+target
 [^:]+:[        ]+852e[         ]+mv[   ]+a0,a1
-[^:]+:[        ]+0511[         ]+addi[         ]+a0,a0,4
+[^:]+:[        ]+0511[         ]+addi[         ]+a0,a0,4 # .*
 [^:]+:[        ]+002c[         ]+addi[         ]+a1,sp,8
 [^:]+:[        ]+c0aa[         ]+sw[   ]+a0,64\(sp\)
 [^:]+:[        ]+41a8[         ]+lw[   ]+a0,64\(a1\)
@@ -46,7 +46,7 @@ Disassembly of section .text:
 [^:]+:[        ]+fa5ff56f[     ]+jal[  ]+a0,0 \<target\>
 [^:]+: R_RISCV_JAL[    ]+target
 [^:]+:[        ]+852e[         ]+mv[   ]+a0,a1
-[^:]+:[        ]+0511[         ]+addi[         ]+a0,a0,4
+[^:]+:[        ]+0511[         ]+addi[         ]+a0,a0,4 # .*
 [^:]+:[        ]+002c[         ]+addi[         ]+a1,sp,8
 [^:]+:[        ]+c0aa[         ]+sw[   ]+a0,64\(sp\)
 [^:]+:[        ]+41a8[         ]+lw[   ]+a0,64\(a1\)

diff --git a/gas/testsuite/gas/riscv/li32.d b/gas/testsuite/gas/riscv/li32.d
index 947ea4f754a7b165cdd1bbf423a0850808a05f02..3496384a68ebef923cedfe43e8f195fd2b5c9189 100644 (file)
--- a/gas/testsuite/gas/riscv/li32.d
+++ b/gas/testsuite/gas/riscv/li32.d
@@ -8,10 +8,10 @@ Disassembly of section .text:
 
 0+000 <target>:
 [^:]+:[        ]+6521[         ]+lui[  ]+a0,0x8
-[^:]+:[        ]+0505[         ]+addi[         ]+a0,a0,1
+[^:]+:[        ]+0505[         ]+addi[         ]+a0,a0,1 # .*
 [^:]+:[        ]+6509[         ]+lui[  ]+a0,0x2
 [^:]+:[        ]+f0150513[     ]+addi[         ]+a0,a0,-255 # .*
 [^:]+:[        ]+12345537[     ]+lui[  ]+a0,0x12345
-[^:]+:[        ]+0505[         ]+addi[         ]+a0,a0,1
+[^:]+:[        ]+0505[         ]+addi[         ]+a0,a0,1 # .*
 [^:]+:[        ]+f2345537[     ]+lui[  ]+a0,0xf2345
-[^:]+:[        ]+0505[         ]+addi[         ]+a0,a0,1
+[^:]+:[        ]+0505[         ]+addi[         ]+a0,a0,1 # .*

diff --git a/gas/testsuite/gas/riscv/li64.d b/gas/testsuite/gas/riscv/li64.d
index 498b2e513d98567bb5c1bcb3f95808c550257096..047985708ad533c94c29bdfc6e4d293bc007ead5 100644 (file)
--- a/gas/testsuite/gas/riscv/li64.d
+++ b/gas/testsuite/gas/riscv/li64.d
@@ -8,23 +8,23 @@ Disassembly of section .text:
 
 0000000000000000 <target>:
 [^:]+:[        ]+6521[         ]+lui[  ]+a0,0x8
-[^:]+:[        ]+2505[         ]+addiw[        ]+a0,a0,1
+[^:]+:[        ]+2505[         ]+addiw[        ]+a0,a0,1 # .*
 [^:]+:[        ]+6509[         ]+lui[  ]+a0,0x2
-[^:]+:[        ]+f015051b[     ]+addiw[        ]+a0,a0,-255
+[^:]+:[        ]+f015051b[     ]+addiw[        ]+a0,a0,-255 # .*
 [^:]+:[        ]+12345537[     ]+lui[  ]+a0,0x12345
-[^:]+:[        ]+2505[         ]+addiw[        ]+a0,a0,1
+[^:]+:[        ]+2505[         ]+addiw[        ]+a0,a0,1 # .*
 [^:]+:[        ]+000f2537[     ]+lui[  ]+a0,0xf2
-[^:]+:[        ]+3455051b[     ]+addiw[        ]+a0,a0,837
+[^:]+:[        ]+3455051b[     ]+addiw[        ]+a0,a0,837 # .*
 [^:]+:[        ]+0532[         ]+slli[         ]+a0,a0,0xc
 [^:]+:[        ]+0505[         ]+addi[         ]+a0,a0,1
 [^:]+:[        ]+00f12537[     ]+lui[  ]+a0,0xf12
-[^:]+:[        ]+3455051b[     ]+addiw[        ]+a0,a0,837
+[^:]+:[        ]+3455051b[     ]+addiw[        ]+a0,a0,837 # .*
 [^:]+:[        ]+0532[         ]+slli[         ]+a0,a0,0xc
 [^:]+:[        ]+0505[         ]+addi[         ]+a0,a0,1
 [^:]+:[        ]+ff010537[     ]+lui[  ]+a0,0xff010
-[^:]+:[        ]+f015051b[     ]+addiw[        ]+a0,a0,-255
+[^:]+:[        ]+f015051b[     ]+addiw[        ]+a0,a0,-255 # .*
 [^:]+:[        ]+054e[         ]+slli[         ]+a0,a0,0x13
-[^:]+:[        ]+80150513[     ]+addi[         ]+a0,a0,-2047 # .*
+[^:]+:[        ]+80150513[     ]+addi[         ]+a0,a0,-2047
 [^:]+:[        ]+0536[         ]+slli[         ]+a0,a0,0xd
 [^:]+:[        ]+f0150513[     ]+addi[         ]+a0,a0,-255
 [^:]+:[        ]+0010051b[     ]+addiw[        ]+a0,zero,1
@@ -35,10 +35,10 @@ Disassembly of section .text:
 [^:]+:[        ]+0532[         ]+slli[         ]+a0,a0,0xc
 [^:]+:[        ]+0505[         ]+addi[         ]+a0,a0,1
 [^:]+:[        ]+01fc4537[     ]+lui[  ]+a0,0x1fc4
-[^:]+:[        ]+c915051b[     ]+addiw[        ]+a0,a0,-879
+[^:]+:[        ]+c915051b[     ]+addiw[        ]+a0,a0,-879 # .*
 [^:]+:[        ]+0536[         ]+slli[         ]+a0,a0,0xd
 [^:]+:[        ]+1565[         ]+addi[         ]+a0,a0,-7
 [^:]+:[        ]+0536[         ]+slli[         ]+a0,a0,0xd
-[^:]+:[        ]+34550513[     ]+addi[         ]+a0,a0,837 # .*
+[^:]+:[        ]+34550513[     ]+addi[         ]+a0,a0,837
 [^:]+:[        ]+0532[         ]+slli[         ]+a0,a0,0xc
 [^:]+:[        ]+0505[         ]+addi[         ]+a0,a0,1

diff --git a/gas/testsuite/gas/riscv/lla64.d b/gas/testsuite/gas/riscv/lla64.d
index c3b958186253fb93ee2f661d7c395b35c84e41a5..b25ef67ad2ce7640b83f5c693770c0e36bac1647 100644 (file)
--- a/gas/testsuite/gas/riscv/lla64.d
+++ b/gas/testsuite/gas/riscv/lla64.d
@@ -10,11 +10,11 @@ Disassembly of section .text:
    0:  0010051b                addiw   a0,zero,1
    4:  00001537                lui     a0,0x1
    8:  00001537                lui     a0,0x1
-   c:  0015051b                addiw   a0,a0,1
+   c:  0015051b                addiw   a0,a0,1 # .*
   10:  00001537                lui     a0,0x1
-  14:  fff5051b                addiw   a0,a0,-1
+  14:  fff5051b                addiw   a0,a0,-1 # .*
   18:  80000537                lui     a0,0x80000
-  1c:  fff5051b                addiw   a0,a0,-1
+  1c:  fff5051b                addiw   a0,a0,-1 # .*
   20:  0000051b                sext.w  a0,zero
   24:  fff0051b                addiw   a0,zero,-1
   28:  80000537                lui     a0,0x80000

diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 171aea21c7afe1feebeb688d01b036cc472a68ff..57198c7b6b5e1fa6b3e35e48f2359ce63166c4fd 100644 (file)
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -156,7 +156,8 @@ arg_print (struct disassemble_info *info, unsigned long val,
 }
 
 static void
-maybe_print_address (struct riscv_private_data *pd, int base_reg, int offset)
+maybe_print_address (struct riscv_private_data *pd, int base_reg, int offset,
+                    int wide)
 {
   if (pd->hi_addr[base_reg] != (bfd_vma)-1)
     {
@@ -167,6 +168,10 @@ maybe_print_address (struct riscv_private_data *pd, int base_reg, int offset)
     pd->print_addr = pd->gp + offset;
   else if (base_reg == X_TP || base_reg == 0)
     pd->print_addr = offset;
+
+  /* Sign-extend a 32-bit value to a 64-bit value.  */
+  if (wide)
+    pd->print_addr = (bfd_vma)(int32_t) pd->print_addr;
 }
 
 /* Print insn arguments for 32/64-bit code.  */
@@ -211,6 +216,11 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
              break;
            case 'o':
            case 'j':
+             if (((l & MASK_C_ADDI) == MATCH_C_ADDI) && rd != 0)
+               maybe_print_address (pd, rd, EXTRACT_CITYPE_IMM (l), 0);
+             if (info->mach == bfd_mach_riscv64
+                 && ((l & MASK_C_ADDIW) == MATCH_C_ADDIW) && rd != 0)
+               maybe_print_address (pd, rd, EXTRACT_CITYPE_IMM (l), 1);
              print (info->stream, "%d", (int)EXTRACT_CITYPE_IMM (l));
              break;
            case 'k':
@@ -283,7 +293,7 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
        case 'b':
        case 's':
          if ((l & MASK_JALR) == MATCH_JALR)
-           maybe_print_address (pd, rs1, 0);
+           maybe_print_address (pd, rs1, 0, 0);
          print (info->stream, "%s", riscv_gpr_names[rs1]);
          break;
 
@@ -313,17 +323,20 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
          break;
 
        case 'o':
-         maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l));
+         maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 0);
          /* Fall through.  */
        case 'j':
          if (((l & MASK_ADDI) == MATCH_ADDI && rs1 != 0)
              || (l & MASK_JALR) == MATCH_JALR)
-           maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l));
+           maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 0);
+         if (info->mach == bfd_mach_riscv64
+             && ((l & MASK_ADDIW) == MATCH_ADDIW) && rs1 != 0)
+           maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 1);
          print (info->stream, "%d", (int)EXTRACT_ITYPE_IMM (l));
          break;
 
        case 'q':
-         maybe_print_address (pd, rs1, EXTRACT_STYPE_IMM (l));
+         maybe_print_address (pd, rs1, EXTRACT_STYPE_IMM (l), 0);
          print (info->stream, "%d", (int)EXTRACT_STYPE_IMM (l));
          break;