examples/de1: use of MigIo

diff --git a/examples/de1/constraints.py b/examples/de1/constraints.py
index 8c1f33eef34a8cb8f68b59aaad2c85f0d04e6795..2e8d2ee3ec3c7d950c748a50b8ed568b0fd1e0e6 100644 (file)
--- a/examples/de1/constraints.py
+++ b/examples/de1/constraints.py
@@ -1,5 +1,5 @@
 class Constraints:
-       def __init__(self, in_clk, in_rst_n, spi2csr0, led0):
+       def __init__(self, in_clk, in_rst_n, spi2csr0, led0, sw0):
                self.constraints = []
                def add(signal, pin, vec=-1, iostandard="3.3-V LVTTL", extra="", sch=""):
                        self.constraints.append((signal, vec, pin, iostandard, extra,sch))
@@ -24,6 +24,9 @@ class Constraints:
                # led0
                add_vec(led0,   ["U22", "U21", "V22", "V21",
                                         "W22" , "W21" , "Y22" , "Y21"])
+               # sw0
+               add_vec(sw0,    ["L22", "L21", "M22", "V12",
+                                        "W12" , "U12" , "U11" , "M2"])
        
        def get_ios(self):
                return set([c[0] for c in self.constraints])

diff --git a/examples/de1/top.py b/examples/de1/top.py
index 666e31116b87ac5331b770b17f3de93793bfa05a..e272edaf34e46592e22aabb098acc9eabe6c1484 100644 (file)
--- a/examples/de1/top.py
+++ b/examples/de1/top.py
@@ -42,7 +42,7 @@ from migen.bank.description import *
 import sys
 sys.path.append("../../")
 
-from migScope import trigger, recorder
+from migScope import trigger, recorder, migIo
 import spi2Csr
 
 from timings import *
@@ -74,10 +74,8 @@ RECORDER_ADDR = 0x0400
 #==============================================================================
 def get():
 
-       # Control Reg
-       control_reg0 = RegisterField("control_reg0", 32, reset=0, access_dev=READ_ONLY)
-       regs = [control_reg0]
-       bank0 = csrgen.Bank(regs,address=CONTROL_ADDR)
+       # migIo
+       migIo0 = migIo.MigIo(8,"IO")
 
        # Trigger
        term0 = trigger.Term(trig_width)
@@ -92,7 +90,7 @@ def get():
        # Csr Interconnect
        csrcon0 = csr.Interconnect(spi2csr0.csr, 
                        [
-                               bank0.interface,
+                               migIo0.bank.interface,
                                trigger0.bank.interface,
                                recorder0.bank.interface
                        ])
@@ -107,10 +105,11 @@ def get():
        
        # Led
        led0 = Signal(BV(8))
-       comb += [
-               led0.eq(control_reg0.field.r[:8])
-       ]
-
+       comb += [led0.eq(migIo0.o)]
+       
+       #Switch
+       sw0 = Signal(BV(8))
+       comb += [migIo0.i.eq(sw0)]
        
        
        # Dat / Trig Bus
@@ -135,7 +134,7 @@ def get():
        ]
        frag = autofragment.from_local()
        frag += Fragment(sync=sync,comb=comb)
-       cst = Constraints(in_clk, in_rst_n, spi2csr0, led0)
+       cst = Constraints(in_clk, in_rst_n, spi2csr0, led0, sw0)
        src_verilog, vns = verilog.convert(frag,
                cst.get_ios(),
                name="de1",