Merge remote-tracking branch 'origin/master' into xaig_arrival

diff --cc README.md
index 9e1761ec4d6b46de743bb896d73ef301c2b4b649,e0a95a9d5c604859fd467f76e4ebba381f05ddcc..6ac321c1f88fae100de3d9ae51e403852d0c2cad
--- 1/README.md
--- 2/README.md
+++ b/README.md
@@@ -347,6 -347,23 +347,20 @@@ Verilog Attributes and non-standard fea
    it as the external-facing pin of an I/O pad, and prevents ``iopadmap``
    from inserting another pad cell on it.
  
 -- The port attribute ``abc_scc_break`` indicates a module input port that will
 -  be treated as a primary output during `abc9` techmapping. Doing so eliminates
 -  the possibility of a strongly-connected component (i.e. a combinatorial loop)
 -  existing. Typically, this is specified for sequential inputs on otherwise
 -  combinatorial boxes -- for example, applying ``abc_scc_break`` onto the `D`
 -  port of a LUTRAM cell prevents `abc9` from interpreting any `Q` -> `D` paths
 -  as a combinatorial loop.
 -
+ - The module attribute ``abc_box_id`` specifies a positive integer linking a
+   blackbox or whitebox definition to a corresponding entry in a `abc9`
+   box-file.
+ 
+ - The port attribute ``abc_carry`` marks the carry-in (if an input port) and
+   carry-out (if output port) ports of a box. This information is necessary for
+   `abc9` to preserve the integrity of carry-chains. Specifying this attribute
+   onto a bus port will affect only its most significant bit.
+ 
++- The port attribute ``abc_arrival`` specifies an integer (for output ports
++  only) to be used as the arrival time of this sequential port. It can be used,
++  for example, to specify the clk-to-Q delay of a flip-flop for consideration
++  during techmapping.
++
  - In addition to the ``(* ... *)`` attribute syntax, Yosys supports
    the non-standard ``{* ... *}`` attribute syntax to set default attributes
    for everything that comes after the ``{* ... *}`` statement. (Reset

diff --cc frontends/aiger/aigerparse.cc
Simple merge

diff --cc passes/techmap/abc9.cc
Simple merge