winsys/amdgpu: add RADEON_FLAG_READ_ONLY

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

diff --git a/src/gallium/drivers/radeon/radeon_winsys.h b/src/gallium/drivers/radeon/radeon_winsys.h
index 1d59b282882c3d197ade08f9787e09f1aacc7841..d1c761f4eeab8a136813435c64348cc09b5dd9ea 100644 (file)
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -52,6 +52,7 @@ enum radeon_bo_flag { /* bitfield */
     RADEON_FLAG_NO_SUBALLOC =   (1 << 2),
     RADEON_FLAG_SPARSE =        (1 << 3),
     RADEON_FLAG_NO_INTERPROCESS_SHARING = (1 << 4),
+    RADEON_FLAG_READ_ONLY =     (1 << 5),
 };
 
 enum radeon_bo_usage { /* bitfield */
@@ -653,8 +654,10 @@ static inline void radeon_emit_array(struct radeon_winsys_cs *cs,
 
 enum radeon_heap {
     RADEON_HEAP_VRAM_NO_CPU_ACCESS,
+    RADEON_HEAP_VRAM_READ_ONLY,
     RADEON_HEAP_VRAM,
     RADEON_HEAP_GTT_WC,
+    RADEON_HEAP_GTT_WC_READ_ONLY,
     RADEON_HEAP_GTT,
     RADEON_MAX_SLAB_HEAPS,
     RADEON_MAX_CACHED_HEAPS = RADEON_MAX_SLAB_HEAPS,
@@ -664,9 +667,11 @@ static inline enum radeon_bo_domain radeon_domain_from_heap(enum radeon_heap hea
 {
     switch (heap) {
     case RADEON_HEAP_VRAM_NO_CPU_ACCESS:
+    case RADEON_HEAP_VRAM_READ_ONLY:
     case RADEON_HEAP_VRAM:
         return RADEON_DOMAIN_VRAM;
     case RADEON_HEAP_GTT_WC:
+    case RADEON_HEAP_GTT_WC_READ_ONLY:
     case RADEON_HEAP_GTT:
         return RADEON_DOMAIN_GTT;
     default:
@@ -683,11 +688,21 @@ static inline unsigned radeon_flags_from_heap(enum radeon_heap heap)
                RADEON_FLAG_NO_CPU_ACCESS |
                RADEON_FLAG_NO_INTERPROCESS_SHARING;
 
+    case RADEON_HEAP_VRAM_READ_ONLY:
+        return RADEON_FLAG_GTT_WC |
+               RADEON_FLAG_NO_INTERPROCESS_SHARING |
+               RADEON_FLAG_READ_ONLY;
+
     case RADEON_HEAP_VRAM:
     case RADEON_HEAP_GTT_WC:
         return RADEON_FLAG_GTT_WC |
                RADEON_FLAG_NO_INTERPROCESS_SHARING;
 
+    case RADEON_HEAP_GTT_WC_READ_ONLY:
+        return RADEON_FLAG_GTT_WC |
+               RADEON_FLAG_NO_INTERPROCESS_SHARING |
+               RADEON_FLAG_READ_ONLY;
+
     case RADEON_HEAP_GTT:
     default:
         return RADEON_FLAG_NO_INTERPROCESS_SHARING;
@@ -702,9 +717,11 @@ static inline unsigned radeon_get_pb_cache_bucket_index(enum radeon_heap heap)
     switch (heap) {
     case RADEON_HEAP_VRAM_NO_CPU_ACCESS:
         return 0;
+    case RADEON_HEAP_VRAM_READ_ONLY:
     case RADEON_HEAP_VRAM:
         return 1;
     case RADEON_HEAP_GTT_WC:
+    case RADEON_HEAP_GTT_WC_READ_ONLY:
         return 2;
     case RADEON_HEAP_GTT:
     default:
@@ -728,23 +745,41 @@ static inline int radeon_get_heap_index(enum radeon_bo_domain domain,
     /* Unsupported flags: NO_SUBALLOC, SPARSE. */
     if (flags & ~(RADEON_FLAG_GTT_WC |
                   RADEON_FLAG_NO_CPU_ACCESS |
-                  RADEON_FLAG_NO_INTERPROCESS_SHARING))
+                  RADEON_FLAG_NO_INTERPROCESS_SHARING |
+                  RADEON_FLAG_READ_ONLY))
         return -1;
 
     switch (domain) {
     case RADEON_DOMAIN_VRAM:
-        if (flags & RADEON_FLAG_NO_CPU_ACCESS)
+        switch (flags & (RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_READ_ONLY)) {
+        case RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_READ_ONLY:
+            assert(!"NO_CPU_ACCESS | READ_ONLY doesn't make sense");
+            return -1;
+        case RADEON_FLAG_NO_CPU_ACCESS:
             return RADEON_HEAP_VRAM_NO_CPU_ACCESS;
-        else
+        case RADEON_FLAG_READ_ONLY:
+            return RADEON_HEAP_VRAM_READ_ONLY;
+        case 0:
             return RADEON_HEAP_VRAM;
+        }
+        break;
     case RADEON_DOMAIN_GTT:
-        if (flags & RADEON_FLAG_GTT_WC)
+        switch (flags & (RADEON_FLAG_GTT_WC | RADEON_FLAG_READ_ONLY)) {
+        case RADEON_FLAG_GTT_WC | RADEON_FLAG_READ_ONLY:
+            return RADEON_HEAP_GTT_WC_READ_ONLY;
+        case RADEON_FLAG_GTT_WC:
             return RADEON_HEAP_GTT_WC;
-        else
+        case RADEON_FLAG_READ_ONLY:
+            assert(!"READ_ONLY without WC is disallowed");
+            return -1;
+        case 0:
             return RADEON_HEAP_GTT;
+        }
+        break;
     default:
-        return -1;
+        break;
     }
+    return -1;
 }
 
 #endif

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
index 9ab8f67cbc742fad26b4bfef6016f37fb4502808..d3b3674f12d58e81a08efa98f973fac4e5118da5 100644 (file)
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
@@ -439,7 +439,14 @@ static struct amdgpu_winsys_bo *amdgpu_create_bo(struct amdgpu_winsys *ws,
    if (r)
       goto error_va_alloc;
 
-   r = amdgpu_bo_va_op(buf_handle, 0, size, va, 0, AMDGPU_VA_OP_MAP);
+   unsigned vm_flags = AMDGPU_VM_PAGE_READABLE |
+                       AMDGPU_VM_PAGE_EXECUTABLE;
+
+   if (!(flags & RADEON_FLAG_READ_ONLY))
+       vm_flags |= AMDGPU_VM_PAGE_WRITEABLE;
+
+   r = amdgpu_bo_va_op_raw(ws->dev, buf_handle, 0, size, va, vm_flags,
+                          AMDGPU_VA_OP_MAP);
    if (r)
       goto error_va_map;