Bugfix in hierarchy handling of blackbox module ports

Signed-off-by: Clifford Wolf <clifford@clifford.at>

diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index be04d5536f431cc8f4ce7980bc1774d978b4042a..037a9f3eec6ed17c1a60c5346e20163ded43b345 100644 (file)
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -1067,7 +1067,7 @@ AstModule::~AstModule()
 }
 
 // create a new parametric module (when needed) and return the name of the generated module
-RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters)
+RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, bool)
 {
        std::string stripped_name = name.str();
 

diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h
index a5d5ee30afa7f864f2124f2f9bfc132ab0ea9d0c..d1e2c78d1f306a60102a89b329dce577ef80985d 100644 (file)
--- a/frontends/ast/ast.h
+++ b/frontends/ast/ast.h
@@ -283,7 +283,7 @@ namespace AST
                AstNode *ast;
                bool nolatches, nomeminit, nomem2reg, mem2reg, lib, noopt, icells, autowire;
                virtual ~AstModule();
-               virtual RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters);
+               virtual RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, bool mayfail);
                virtual RTLIL::Module *clone() const;
        };
 

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 3e873054f13b7b5d61f3ad50d5ecb3f4ff4bef65..fb3d9dbe9e78aa637521ab6404d772e83290569f 100644 (file)
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -639,8 +639,10 @@ RTLIL::Module::~Module()
                delete it->second;
 }
 
-RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict<RTLIL::IdString, RTLIL::Const>)
+RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict<RTLIL::IdString, RTLIL::Const>, bool mayfail)
 {
+       if (mayfail)
+               return RTLIL::IdString();
        log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
 }
 

diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index fc29e1e6515fd72448fb56177ff89e6383559539..a251b425273ac07f8f99c5a55336d219beb4923b 100644 (file)
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -906,7 +906,7 @@ public:
 
        Module();
        virtual ~Module();
-       virtual RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters);
+       virtual RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, bool mayfail = false);
        virtual size_t count_id(RTLIL::IdString id);
 
        virtual void sort();

diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index 524d57854e7b9c540e0c5e66fb0ad67fc83834e7..c680dbbd892e477e7fa17b630833a3e2c72c17b4 100644 (file)
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -625,16 +625,15 @@ struct HierarchyPass : public Pass {
                for (auto module : design->modules())
                for (auto cell : module->cells())
                {
-                       if (GetSize(cell->parameters) != 0)
-                               continue;
-
                        Module *m = design->module(cell->type);
 
                        if (m == nullptr)
                                continue;
 
-                       if (m->get_bool_attribute("\\blackbox") && cell->parameters.size()) {
-                               IdString new_m_name = m->derive(design, cell->parameters);
+                       if (m->get_bool_attribute("\\blackbox") && !cell->parameters.empty()) {
+                               IdString new_m_name = m->derive(design, cell->parameters, true);
+                               if (new_m_name.empty())
+                                       continue;
                                if (new_m_name != m->name) {
                                        m = design->module(new_m_name);
                                        blackbox_derivatives.insert(m);