sort out memory_interface_fetch_address

diff --git a/cpu_fetch_stage.py b/cpu_fetch_stage.py
index 1fa8942f08bb61e275b59e98a3ce19f8f5dfc45c..7c699bd13cb9645d61523c7b1bfd346b3dadeca0 100644 (file)
--- a/cpu_fetch_stage.py
+++ b/cpu_fetch_stage.py
@@ -37,7 +37,7 @@ class CPUFetchStage(Module):
         self.clk = ClockSignal()
         self.reset = ResetSignal()
         #output [31:2] memory_interface_fetch_address,
-        self.memory_interface_fetch_address = Signal(32)[2:]
+        self.memory_interface_fetch_address = Signal(32)
         #input [31:0] memory_interface_fetch_data,
         self.memory_interface_fetch_data = Signal(32)
         self.memory_interface_fetch_valid = Signal()
@@ -58,7 +58,7 @@ class CPUFetchStage(Module):
         self.sync += If(self.fetch_action != fetch_action_wait,
                         self.output_pc.eq(fetch_pc))
 
-        self.memory_interface_fetch_address = fetch_pc[2:]
+        self.comb += self.memory_interface_fetch_address.eq(fetch_pc[2:])
 
         #initial output_pc <= reset_vector;
         #initial output_state <= `fetch_output_state_empty;
@@ -111,11 +111,11 @@ class CPUFetchStage(Module):
 
 if __name__ == "__main__":
     example = CPUFetchStage()
-    memory_interface_fetch_address = Signal(32)
+    #memory_interface_fetch_address = Signal(32)
     print(verilog.convert(example,
          { #example.clk,
            #example.reset,
-           memory_interface_fetch_address,
+           example.memory_interface_fetch_address,
            example.memory_interface_fetch_data,
            example.memory_interface_fetch_valid,
            example.fetch_action,