Add Verific adffe/dffsre/aldffe FIXMEs

Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 59fdda06839f0d4b5e89e05dce62dc1f6eaa9339..b8742e61d5c116b3cae5596937f34b9d7c455ff3 100644 (file)
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -1864,6 +1864,7 @@ Cell *VerificClocking::addAdff(IdString name, RTLIL::SigSpec sig_arst, SigSpec s
        log_assert(gclk == false);
        log_assert(disable_sig == State::S0);
 
+       // FIXME: Adffe
        if (enable_sig != State::S1)
                sig_d = module->Mux(NEW_ID, sig_q, sig_d, enable_sig);
 
@@ -1875,6 +1876,7 @@ Cell *VerificClocking::addDffsr(IdString name, RTLIL::SigSpec sig_set, RTLIL::Si
        log_assert(gclk == false);
        log_assert(disable_sig == State::S0);
 
+       // FIXME: Dffsre
        if (enable_sig != State::S1)
                sig_d = module->Mux(NEW_ID, sig_q, sig_d, enable_sig);
 
@@ -1886,6 +1888,7 @@ Cell *VerificClocking::addAldff(IdString name, RTLIL::SigSpec sig_aload, RTLIL::
        log_assert(gclk == false);
        log_assert(disable_sig == State::S0);
 
+       // FIXME: Aldffe
        if (enable_sig != State::S1)
                sig_d = module->Mux(NEW_ID, sig_q, sig_d, enable_sig);