#define GEN7_MI_OPCODE_MI_PREDICATE (0xc << 23)
#define GEN7_MI_OPCODE_MI_URB_CLEAR (0x19 << 23)
#define GEN75_MI_OPCODE_MI_MATH (0x1a << 23)
+#define GEN8_MI_OPCODE_MI_SEMAPHORE_SIGNAL (0x1b << 23)
+#define GEN8_MI_OPCODE_MI_SEMAPHORE_WAIT (0x1c << 23)
#define GEN6_MI_OPCODE_MI_STORE_DATA_IMM (0x20 << 23)
#define GEN6_MI_OPCODE_MI_LOAD_REGISTER_IMM (0x22 << 23)
#define GEN6_MI_OPCODE_MI_STORE_REGISTER_MEM (0x24 << 23)
#define GEN6_MI_OPCODE_MI_REPORT_PERF_COUNT (0x28 << 23)
#define GEN7_MI_OPCODE_MI_LOAD_REGISTER_MEM (0x29 << 23)
#define GEN75_MI_OPCODE_MI_LOAD_REGISTER_REG (0x2a << 23)
+#define GEN75_MI_OPCODE_MI_RS_STORE_DATA_IMM (0x2b << 23)
#define GEN75_MI_OPCODE_MI_LOAD_URB_MEM (0x2c << 23)
#define GEN75_MI_OPCODE_MI_STORE_URB_MEM (0x2d << 23)
+#define GEN8_MI_OPCODE_MI_COPY_MEM_MEM (0x2e << 23)
+#define GEN8_MI_OPCODE_MI_ATOMIC (0x2f << 23)
#define GEN6_MI_OPCODE_MI_BATCH_BUFFER_START (0x31 << 23)
#define GEN6_MI_LENGTH__MASK 0x0000003f
#define GEN6_MI_LENGTH__SHIFT 0
#define GEN75_MI_MATH_DW_SRC2__MASK 0x000007ff
#define GEN75_MI_MATH_DW_SRC2__SHIFT 0
+#define GEN8_MI_SEMAPHORE_SIGNAL__SIZE 2
+#define GEN8_MI_SEMAPHORE_SIGNAL_DW0_POST_SYNC_OP (0x1 << 21)
+#define GEN8_MI_SEMAPHORE_SIGNAL_DW0_ENGINE__MASK 0x00038000
+#define GEN8_MI_SEMAPHORE_SIGNAL_DW0_ENGINE__SHIFT 15
+#define GEN8_MI_SEMAPHORE_SIGNAL_DW0_ENGINE_RCS (0x0 << 15)
+#define GEN8_MI_SEMAPHORE_SIGNAL_DW0_ENGINE_VCS0 (0x1 << 15)
+#define GEN8_MI_SEMAPHORE_SIGNAL_DW0_ENGINE_BCS (0x2 << 15)
+#define GEN8_MI_SEMAPHORE_SIGNAL_DW0_ENGINE_VECS (0x3 << 15)
+#define GEN8_MI_SEMAPHORE_SIGNAL_DW0_ENGINE_VCS1 (0x4 << 15)
+
+
+#define GEN8_MI_SEMAPHORE_WAIT__SIZE 4
+#define GEN8_MI_SEMAPHORE_WAIT_DW0_USE_GGTT (0x1 << 22)
+#define GEN8_MI_SEMAPHORE_WAIT_DW0_WAIT_MODE__MASK 0x00008000
+#define GEN8_MI_SEMAPHORE_WAIT_DW0_WAIT_MODE__SHIFT 15
+#define GEN8_MI_SEMAPHORE_WAIT_DW0_WAIT_MODE_SIGNAL (0x0 << 15)
+#define GEN8_MI_SEMAPHORE_WAIT_DW0_WAIT_MODE_POLL (0x1 << 15)
+#define GEN8_MI_SEMAPHORE_WAIT_DW0_OP__MASK 0x00007000
+#define GEN8_MI_SEMAPHORE_WAIT_DW0_OP__SHIFT 12
+#define GEN8_MI_SEMAPHORE_WAIT_DW0_OP_SAD_GREATER_THAN_SDD (0x0 << 12)
+#define GEN8_MI_SEMAPHORE_WAIT_DW0_OP_SAD_GREATER_THAN_OR_EQUAL_SDD (0x1 << 12)
+#define GEN8_MI_SEMAPHORE_WAIT_DW0_OP_SAD_LESS_THAN_SDD (0x2 << 12)
+#define GEN8_MI_SEMAPHORE_WAIT_DW0_OP_SAD_LESS_THAN_OR_EQUAL_SDD (0x3 << 12)
+#define GEN8_MI_SEMAPHORE_WAIT_DW0_OP_SAD_EQUAL_SDD (0x4 << 12)
+#define GEN8_MI_SEMAPHORE_WAIT_DW0_OP_SAD_NO_EQUAL_SDD (0x5 << 12)
+
+
+#define GEN8_MI_SEMAPHORE_WAIT_DW2_ADDR_ADDR__MASK 0xfffffffc
+#define GEN8_MI_SEMAPHORE_WAIT_DW2_ADDR_ADDR__SHIFT 2
+#define GEN8_MI_SEMAPHORE_WAIT_DW2_ADDR_ADDR__SHR 2
+
+
#define GEN6_MI_STORE_DATA_IMM__SIZE 6
#define GEN6_MI_STORE_DATA_IMM_DW0_USE_GGTT (0x1 << 22)
+#define GEN8_MI_STORE_DATA_IMM_DW0_STORE_QWORD (0x1 << 21)
#define GEN6_MI_STORE_DATA_IMM_DW2_ADDR__MASK 0xfffffffc
#define GEN6_MI_STORE_REGISTER_MEM_DW2_ADDR__SHR 2
-#define GEN6_MI_FLUSH_DW__SIZE 4
+#define GEN6_MI_FLUSH_DW__SIZE 5
+#define GEN6_MI_FLUSH_DW_DW0_WRITE__MASK 0x0000c000
+#define GEN6_MI_FLUSH_DW_DW0_WRITE__SHIFT 14
+#define GEN6_MI_FLUSH_DW_DW0_WRITE_NONE (0x0 << 14)
+#define GEN6_MI_FLUSH_DW_DW0_WRITE_IMM (0x1 << 14)
+#define GEN6_MI_FLUSH_DW_DW0_WRITE_TIMESTAMP (0x3 << 14)
+
+#define GEN6_MI_FLUSH_DW_DW1_USE_GGTT (0x1 << 2)
+#define GEN6_MI_FLUSH_DW_DW1_ADDR__MASK 0xfffffff8
+#define GEN6_MI_FLUSH_DW_DW1_ADDR__SHIFT 3
+#define GEN6_MI_FLUSH_DW_DW1_ADDR__SHR 3
#define GEN75_MI_LOAD_REGISTER_REG_DW2_DST_REG__SHIFT 2
#define GEN75_MI_LOAD_REGISTER_REG_DW2_DST_REG__SHR 2
+#define GEN75_MI_RS_STORE_DATA_IMM__SIZE 6
+#define GEN75_MI_RS_STORE_DATA_IMM_DW0_USE_GGTT (0x1 << 22)
+
+
+#define GEN75_MI_RS_STORE_DATA_IMM_DW2_ADDR__MASK 0xfffffffc
+#define GEN75_MI_RS_STORE_DATA_IMM_DW2_ADDR__SHIFT 2
+#define GEN75_MI_RS_STORE_DATA_IMM_DW2_ADDR__SHR 2
+
+
+
+
#define GEN75_MI_LOAD_URB_MEM__SIZE 4
#define GEN75_MI_LOAD_URB_MEM_DW1_ADDR__MASK 0x00007ffc
#define GEN75_MI_STORE_URB_MEM_DW2_ADDR__SHR 6
+#define GEN8_MI_COPY_MEM_MEM__SIZE 5
+#define GEN8_MI_COPY_MEM_MEM_DW0_USE_GGTT_SRC (0x1 << 22)
+#define GEN8_MI_COPY_MEM_MEM_DW0_USE_GGTT_DST (0x1 << 21)
+
+#define GEN8_MI_COPY_MEM_MEM_DW1_DST_ADDR__MASK 0xfffffffc
+#define GEN8_MI_COPY_MEM_MEM_DW1_DST_ADDR__SHIFT 2
+#define GEN8_MI_COPY_MEM_MEM_DW1_DST_ADDR__SHR 2
+
+
+#define GEN8_MI_COPY_MEM_MEM_DW3_SRC_ADDR__MASK 0xfffffffc
+#define GEN8_MI_COPY_MEM_MEM_DW3_SRC_ADDR__SHIFT 2
+#define GEN8_MI_COPY_MEM_MEM_DW3_SRC_ADDR__SHR 2
+
+
+#define GEN8_MI_ATOMIC__SIZE 11
+#define GEN8_MI_ATOMIC_DW0_USE_GGTT (0x1 << 22)
+#define GEN8_MI_ATOMIC_DW0_POST_SYNC_OP (0x1 << 21)
+#define GEN8_MI_ATOMIC_DW0_SIZE__MASK 0x00180000
+#define GEN8_MI_ATOMIC_DW0_SIZE__SHIFT 19
+#define GEN8_MI_ATOMIC_DW0_SIZE_DWORD (0x0 << 19)
+#define GEN8_MI_ATOMIC_DW0_SIZE_QWORD (0x1 << 19)
+#define GEN8_MI_ATOMIC_DW0_SIZE_OWORD (0x2 << 19)
+#define GEN8_MI_ATOMIC_DW0_INLINE_DATA (0x1 << 18)
+#define GEN8_MI_ATOMIC_DW0_CS_STALL (0x1 << 17)
+#define GEN8_MI_ATOMIC_DW0_RETURN_DATA_CONTROL (0x1 << 16)
+#define GEN8_MI_ATOMIC_DW0_OP__MASK 0x0000ff00
+#define GEN8_MI_ATOMIC_DW0_OP__SHIFT 8
+
+#define GEN8_MI_ATOMIC_DW1_ADDR__MASK 0xfffffffc
+#define GEN8_MI_ATOMIC_DW1_ADDR__SHIFT 2
+#define GEN8_MI_ATOMIC_DW1_ADDR__SHR 2
+
+
+
#define GEN6_MI_BATCH_BUFFER_START__SIZE 3
#define GEN75_MI_BATCH_BUFFER_START_DW0_SECOND_LEVEL (0x1 << 22)
#define GEN75_MI_BATCH_BUFFER_START_DW0_ADD_OFFSET_ENABLE (0x1 << 16)
#define GEN75_MI_BATCH_BUFFER_START_DW0_PREDICATION_ENABLE (0x1 << 15)
#define GEN75_MI_BATCH_BUFFER_START_DW0_NON_PRIVILEGED (0x1 << 13)
#define GEN6_MI_BATCH_BUFFER_START_DW0_CLEAR_COMMAND_BUFFER (0x1 << 11)
+#define GEN75_MI_BATCH_BUFFER_START_DW0_RS_ENABLE (0x1 << 10)
#define GEN6_MI_BATCH_BUFFER_START_DW0_USE_PPGTT (0x1 << 8)
#define GEN6_MI_BATCH_BUFFER_START_DW1_ADDR__MASK 0xfffffffc
GEN8_NUMSAMPLES_2 = 0x1,
GEN6_NUMSAMPLES_4 = 0x2,
GEN7_NUMSAMPLES_8 = 0x3,
- GEN8_NUMSAMPLES_16 = 0x4,
};
enum gen_inputattr_select {
#define GEN7_URB_DW1_OFFSET__MASK 0x3e000000
#define GEN7_URB_DW1_OFFSET__SHIFT 25
+#define GEN75_URB_DW1_OFFSET__MASK 0x7e000000
+#define GEN75_URB_DW1_OFFSET__SHIFT 25
+#define GEN8_URB_DW1_OFFSET__MASK 0xfe000000
+#define GEN8_URB_DW1_OFFSET__SHIFT 25
#define GEN7_URB_DW1_ENTRY_SIZE__MASK 0x01ff0000
#define GEN7_URB_DW1_ENTRY_SIZE__SHIFT 16
#define GEN7_URB_DW1_ENTRY_COUNT__MASK 0x0000ffff
#define GEN7_URB_DW1_ENTRY_COUNT__SHIFT 0
+#define GEN75_3DSTATE_GATHER_CONSTANT_ANY__SIZE 130
+
+
+#define GEN75_GATHER_CONST_DW1_BT_VALID__MASK 0xffff0000
+#define GEN75_GATHER_CONST_DW1_BT_VALID__SHIFT 16
+#define GEN75_GATHER_CONST_DW1_BT_BLOCK__MASK 0x0000f000
+#define GEN75_GATHER_CONST_DW1_BT_BLOCK__SHIFT 12
+
+#define GEN75_GATHER_CONST_DW2_GATHER_BUFFER_OFFSET__MASK 0x007fffc0
+#define GEN75_GATHER_CONST_DW2_GATHER_BUFFER_OFFSET__SHIFT 6
+#define GEN75_GATHER_CONST_DW2_GATHER_BUFFER_OFFSET__SHR 6
+#define GEN8_GATHER_CONST_DW2_DX9_STALL (0x1 << 5)
+#define GEN75_GATHER_CONST_DW2_DX9_ENABLE (0x1 << 4)
+
+#define GEN75_GATHER_CONST_DW_ENTRY_HIGH__MASK 0xffff0000
+#define GEN75_GATHER_CONST_DW_ENTRY_HIGH__SHIFT 16
+#define GEN75_GATHER_CONST_DW_ENTRY_OFFSET__MASK 0x0000ff00
+#define GEN75_GATHER_CONST_DW_ENTRY_OFFSET__SHIFT 8
+#define GEN75_GATHER_CONST_DW_ENTRY_CHANNEL_MASK__MASK 0x000000f0
+#define GEN75_GATHER_CONST_DW_ENTRY_CHANNEL_MASK__SHIFT 4
+#define GEN75_GATHER_CONST_DW_ENTRY_BT_INDEX__MASK 0x0000001f
+#define GEN75_GATHER_CONST_DW_ENTRY_BT_INDEX__SHIFT 0
+
+#define GEN75_3DSTATE_BINDING_TABLE_EDIT_ANY__SIZE 258
+
+
+#define GEN75_BT_EDIT_DW1_BT_BLOCK_CLEAR__MASK 0xffff0000
+#define GEN75_BT_EDIT_DW1_BT_BLOCK_CLEAR__SHIFT 16
+#define GEN75_BT_EDIT_DW1_TARGET__MASK 0x00000003
+#define GEN75_BT_EDIT_DW1_TARGET__SHIFT 0
+#define GEN75_BT_EDIT_DW1_TARGET_CORE0 0x1
+#define GEN75_BT_EDIT_DW1_TARGET_CORE1 0x2
+#define GEN75_BT_EDIT_DW1_TARGET_ALL 0x3
+
+#define GEN75_BT_EDIT_DW_ENTRY_BT_INDEX__MASK 0x00ff0000
+#define GEN75_BT_EDIT_DW_ENTRY_BT_INDEX__SHIFT 16
+#define GEN75_BT_EDIT_DW_ENTRY_SURFACE_STATE_ADDR__MASK 0x0000ffff
+#define GEN75_BT_EDIT_DW_ENTRY_SURFACE_STATE_ADDR__SHIFT 0
+#define GEN75_BT_EDIT_DW_ENTRY_SURFACE_STATE_ADDR__SHR 5
+#define GEN8_BT_EDIT_DW_ENTRY_SURFACE_STATE_ADDR__MASK 0x0000ffff
+#define GEN8_BT_EDIT_DW_ENTRY_SURFACE_STATE_ADDR__SHIFT 0
+#define GEN8_BT_EDIT_DW_ENTRY_SURFACE_STATE_ADDR__SHR 6
+
#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_ANY__SIZE 2
#define GEN75_PCB_ALLOC_DW1_SIZE__MASK 0x0000003f
#define GEN75_PCB_ALLOC_DW1_SIZE__SHIFT 0
+#define GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC__SIZE 3
+
+
+#define GEN75_BT_POOL_ALLOC_DW1_ADDR__MASK 0xfffff000
+#define GEN75_BT_POOL_ALLOC_DW1_ADDR__SHIFT 12
+#define GEN75_BT_POOL_ALLOC_DW1_ADDR__SHR 12
+#define GEN75_BT_POOL_ALLOC_DW1_ENABLE (0x1 << 11)
+#define GEN75_BT_POOL_ALLOC_DW1_MOCS__MASK 0x00000780
+#define GEN75_BT_POOL_ALLOC_DW1_MOCS__SHIFT 7
+#define GEN8_BT_POOL_ALLOC_DW1_MOCS__MASK 0x0000007f
+#define GEN8_BT_POOL_ALLOC_DW1_MOCS__SHIFT 0
+
+#define GEN75_BT_POOL_ALLOC_DW2_END_ADDR__MASK 0xfffff000
+#define GEN75_BT_POOL_ALLOC_DW2_END_ADDR__SHIFT 12
+#define GEN75_BT_POOL_ALLOC_DW2_END_ADDR__SHR 12
+
+
+#define GEN8_BT_POOL_ALLOC_DW3_SIZE__MASK 0xfffff000
+#define GEN8_BT_POOL_ALLOC_DW3_SIZE__SHIFT 12
+#define GEN8_BT_POOL_ALLOC_DW3_SIZE__SHR 12
+
+#define GEN75_3DSTATE_GATHER_POOL_ALLOC__SIZE 3
+
+
+#define GEN75_GATHER_POOL_ALLOC_DW1_ADDR__MASK 0xfffff000
+#define GEN75_GATHER_POOL_ALLOC_DW1_ADDR__SHIFT 12
+#define GEN75_GATHER_POOL_ALLOC_DW1_ADDR__SHR 12
+#define GEN75_GATHER_POOL_ALLOC_DW1_ENABLE (0x1 << 11)
+#define GEN75_GATHER_POOL_ALLOC_DW1_MOCS__MASK 0x0000000f
+#define GEN75_GATHER_POOL_ALLOC_DW1_MOCS__SHIFT 0
+#define GEN8_GATHER_POOL_ALLOC_DW1_MOCS__MASK 0x0000007f
+#define GEN8_GATHER_POOL_ALLOC_DW1_MOCS__SHIFT 0
+
+#define GEN75_GATHER_POOL_ALLOC_DW2_END_ADDR__MASK 0xfffff000
+#define GEN75_GATHER_POOL_ALLOC_DW2_END_ADDR__SHIFT 12
+#define GEN75_GATHER_POOL_ALLOC_DW2_END_ADDR__SHR 12
+
+
+#define GEN8_GATHER_POOL_ALLOC_DW3_SIZE__MASK 0xfffff000
+#define GEN8_GATHER_POOL_ALLOC_DW3_SIZE__SHIFT 12
+#define GEN8_GATHER_POOL_ALLOC_DW3_SIZE__SHR 12
+
#define GEN6_3DSTATE_VERTEX_BUFFERS__SIZE 133
#define GEN8_SGVS_DW1_IID_ENABLE (0x1 << 31)
-#define GEN8_SGVS_DW1_IID_VE_COMP__MASK 0x60000000
-#define GEN8_SGVS_DW1_IID_VE_COMP__SHIFT 29
-#define GEN8_SGVS_DW1_IID_VE_INDEX__MASK 0x003f0000
-#define GEN8_SGVS_DW1_IID_VE_INDEX__SHIFT 16
+#define GEN8_SGVS_DW1_IID_COMP__MASK 0x60000000
+#define GEN8_SGVS_DW1_IID_COMP__SHIFT 29
+#define GEN8_SGVS_DW1_IID_OFFSET__MASK 0x003f0000
+#define GEN8_SGVS_DW1_IID_OFFSET__SHIFT 16
#define GEN8_SGVS_DW1_VID_ENABLE (0x1 << 15)
-#define GEN8_SGVS_DW1_VID_VE_COMP__MASK 0x00006000
-#define GEN8_SGVS_DW1_VID_VE_COMP__SHIFT 13
-#define GEN8_SGVS_DW1_VID_VE_INDEX__MASK 0x0000003f
-#define GEN8_SGVS_DW1_VID_VE_INDEX__SHIFT 0
+#define GEN8_SGVS_DW1_VID_COMP__MASK 0x00006000
+#define GEN8_SGVS_DW1_VID_COMP__SHIFT 13
+#define GEN8_SGVS_DW1_VID_OFFSET__MASK 0x0000003f
+#define GEN8_SGVS_DW1_VID_OFFSET__SHIFT 0
#define GEN8_3DSTATE_VF_TOPOLOGY__SIZE 2
#define GEN7_3DSTATE_POINTERS_ANY__SIZE 2
+#define GEN7_PTR_DW1_ADDR__MASK 0xffffffe0
+#define GEN7_PTR_DW1_ADDR__SHIFT 5
+#define GEN7_PTR_DW1_ADDR__SHR 5
+#define GEN8_PTR_DW1_CHANGED (0x1 << 0)
#define GEN6_3DSTATE_VS__SIZE 9
#define GEN8_VS_DW7_CACHE_DISABLE (0x1 << 1)
#define GEN8_VS_DW7_VS_ENABLE (0x1 << 0)
-#define GEN8_VS_DW8_URB_WRITE_OFFSET__MASK 0x03e00000
-#define GEN8_VS_DW8_URB_WRITE_OFFSET__SHIFT 21
-#define GEN8_VS_DW8_URB_WRITE_LEN__MASK 0x001f0000
-#define GEN8_VS_DW8_URB_WRITE_LEN__SHIFT 16
+#define GEN8_VS_DW8_VUE_OUT_READ_OFFSET__MASK 0x07e00000
+#define GEN8_VS_DW8_VUE_OUT_READ_OFFSET__SHIFT 21
+#define GEN8_VS_DW8_VUE_OUT_LEN__MASK 0x001f0000
+#define GEN8_VS_DW8_VUE_OUT_LEN__SHIFT 16
#define GEN8_VS_DW8_UCP_CLIP_ENABLES__MASK 0x0000ff00
#define GEN8_VS_DW8_UCP_CLIP_ENABLES__SHIFT 8
+#define GEN8_VS_DW8_UCP_CULL_ENABLES__MASK 0x000000ff
+#define GEN8_VS_DW8_UCP_CULL_ENABLES__SHIFT 0
#define GEN7_3DSTATE_HS__SIZE 9
-#define GEN8_HS_DW1_DISPATCH_MAX_THREADS__MASK 0x000000ff
-#define GEN8_HS_DW1_DISPATCH_MAX_THREADS__SHIFT 0
#define GEN8_HS_DW2_HS_ENABLE (0x1 << 31)
#define GEN8_HS_DW2_STATISTICS (0x1 << 29)
+#define GEN8_HS_DW2_MAX_THREADS__MASK 0x0001ff00
+#define GEN8_HS_DW2_MAX_THREADS__SHIFT 8
#define GEN8_HS_DW2_INSTANCE_COUNT__MASK 0x0000000f
#define GEN8_HS_DW2_INSTANCE_COUNT__SHIFT 0
#define GEN8_HS_DW7_URB_READ_OFFSET__MASK 0x000003f0
#define GEN8_HS_DW7_URB_READ_OFFSET__SHIFT 4
-#define GEN8_HS_DW8_URB_SEMAPHORE_ADDR__MASK 0x00001fff
-#define GEN8_HS_DW8_URB_SEMAPHORE_ADDR__SHIFT 0
-#define GEN8_HS_DW8_URB_SEMAPHORE_ADDR__SHR 6
#define GEN7_3DSTATE_TE__SIZE 4
#define GEN8_DS_DW7_MAX_THREADS__MASK 0x3fe00000
#define GEN8_DS_DW7_MAX_THREADS__SHIFT 21
#define GEN8_DS_DW7_STATISTICS (0x1 << 10)
+#define GEN8_DS_DW7_SIMD8_ENABLE (0x1 << 3)
#define GEN8_DS_DW7_COMPUTE_W (0x1 << 2)
#define GEN8_DS_DW7_CACHE_DISABLE (0x1 << 1)
#define GEN8_DS_DW7_DS_ENABLE (0x1 << 0)
-#define GEN8_DS_DW8_URB_WRITE_OFFSET__MASK 0x03e00000
-#define GEN8_DS_DW8_URB_WRITE_OFFSET__SHIFT 21
-#define GEN8_DS_DW8_URB_WRITE_LEN__MASK 0x001f0000
-#define GEN8_DS_DW8_URB_WRITE_LEN__SHIFT 16
+#define GEN8_DS_DW8_VUE_OUT_READ_OFFSET__MASK 0x07e00000
+#define GEN8_DS_DW8_VUE_OUT_READ_OFFSET__SHIFT 21
+#define GEN8_DS_DW8_VUE_OUT_LEN__MASK 0x001f0000
+#define GEN8_DS_DW8_VUE_OUT_LEN__SHIFT 16
#define GEN8_DS_DW8_UCP_CLIP_ENABLES__MASK 0x0000ff00
#define GEN8_DS_DW8_UCP_CLIP_ENABLES__SHIFT 8
+#define GEN8_DS_DW8_UCP_CULL_ENABLES__MASK 0x000000ff
+#define GEN8_DS_DW8_UCP_CULL_ENABLES__SHIFT 0
#define GEN8_GS_DW1_KERNEL_ADDR__SHR 6
-#define GEN8_GS_DW3_EXPECTED_VERTEX_COUNT__MASK 0x0000007f
+#define GEN8_GS_DW3_EXPECTED_VERTEX_COUNT__MASK 0x0000003f
#define GEN8_GS_DW3_EXPECTED_VERTEX_COUNT__SHIFT 0
#define GEN8_GS_DW8_GSCTRL__SHIFT 31
#define GEN8_GS_DW8_GSCTRL_CUT (0x0 << 31)
#define GEN8_GS_DW8_GSCTRL_SID (0x1 << 31)
-#define GEN8_GS_DW8_URB_SEMAPHORE_ADDR__MASK 0x00001fff
-#define GEN8_GS_DW8_URB_SEMAPHORE_ADDR__SHIFT 0
-#define GEN8_GS_DW8_URB_SEMAPHORE_ADDR__SHR 6
-#define GEN9_GS_DW8_MAX_THREADS__MASK 0x00001fff
+#define GEN8_GS_DW8_STATIC_OUTPUT (0x1 << 30)
+#define GEN8_GS_DW8_STATIC_OUTPUT_VERTEX_COUNT__MASK 0x07ff0000
+#define GEN8_GS_DW8_STATIC_OUTPUT_VERTEX_COUNT__SHIFT 16
+#define GEN9_GS_DW8_MAX_THREADS__MASK 0x000001ff
#define GEN9_GS_DW8_MAX_THREADS__SHIFT 0
-#define GEN8_GS_DW9_URB_WRITE_OFFSET__MASK 0x03e00000
-#define GEN8_GS_DW9_URB_WRITE_OFFSET__SHIFT 21
-#define GEN8_GS_DW9_URB_WRITE_LEN__MASK 0x001f0000
-#define GEN8_GS_DW9_URB_WRITE_LEN__SHIFT 16
+#define GEN8_GS_DW9_VUE_OUT_READ_OFFSET__MASK 0x07e00000
+#define GEN8_GS_DW9_VUE_OUT_READ_OFFSET__SHIFT 21
+#define GEN8_GS_DW9_VUE_OUT_LEN__MASK 0x001f0000
+#define GEN8_GS_DW9_VUE_OUT_LEN__SHIFT 16
#define GEN8_GS_DW9_UCP_CLIP_ENABLES__MASK 0x0000ff00
#define GEN8_GS_DW9_UCP_CLIP_ENABLES__SHIFT 8
+#define GEN8_GS_DW9_UCP_CULL_ENABLES__MASK 0x000000ff
+#define GEN8_GS_DW9_UCP_CULL_ENABLES__SHIFT 0
#define GEN7_3DSTATE_STREAMOUT__SIZE 5
#define GEN7_SO_DW1_REORDER_MODE__MASK 0x04000000
#define GEN7_SO_DW1_REORDER_MODE__SHIFT 26
#define GEN7_SO_DW1_STATISTICS (0x1 << 25)
+#define GEN8_SO_DW1_FORCE_RENDERING__MASK 0x01800000
+#define GEN8_SO_DW1_FORCE_RENDERING__SHIFT 23
+#define GEN8_SO_DW1_FORCE_RENDERING_NORMAL (0x0 << 23)
+#define GEN8_SO_DW1_FORCE_RENDERING_OFF (0x2 << 23)
+#define GEN8_SO_DW1_FORCE_RENDERING_ON (0x3 << 23)
#define GEN7_SO_DW1_BUFFER_ENABLES__MASK 0x00000f00
#define GEN7_SO_DW1_BUFFER_ENABLES__SHIFT 8
-#define GEN8_SO_BUF_DW5_OFFSET_ADDR__MASK 0xfffffffc
-#define GEN8_SO_BUF_DW5_OFFSET_ADDR__SHIFT 2
-#define GEN8_SO_BUF_DW5_OFFSET_ADDR__SHR 2
+#define GEN8_SO_BUF_DW5_OFFSET_ADDR_ADDR__MASK 0xfffffffc
+#define GEN8_SO_BUF_DW5_OFFSET_ADDR_ADDR__SHIFT 2
+#define GEN8_SO_BUF_DW5_OFFSET_ADDR_ADDR__SHR 2
#define GEN7_CLIP_DW1_FRONT_WINDING__MASK 0x00100000
#define GEN7_CLIP_DW1_FRONT_WINDING__SHIFT 20
+#define GEN8_CLIP_DW1_FORCE_UCP_CULL_ENABLES (0x1 << 20)
#define GEN7_CLIP_DW1_SUBPIXEL__MASK 0x00080000
#define GEN7_CLIP_DW1_SUBPIXEL__SHIFT 19
#define GEN7_CLIP_DW1_SUBPIXEL_8BITS (0x0 << 19)
#define GEN7_CLIP_DW1_EARLY_CULL_ENABLE (0x1 << 18)
#define GEN7_CLIP_DW1_CULL_MODE__MASK 0x00030000
#define GEN7_CLIP_DW1_CULL_MODE__SHIFT 16
+#define GEN8_CLIP_DW1_FORCE_UCP_CLIP_ENABLES (0x1 << 17)
+#define GEN8_CLIP_DW1_FORCE_CLIP_MODE (0x1 << 16)
#define GEN6_CLIP_DW1_STATISTICS (0x1 << 10)
#define GEN6_CLIP_DW1_UCP_CULL_ENABLES__MASK 0x000000ff
#define GEN6_CLIP_DW1_UCP_CULL_ENABLES__SHIFT 0
#define GEN7_SF_DW3_TRIFAN_PROVOKE__MASK 0x06000000
#define GEN7_SF_DW3_TRIFAN_PROVOKE__SHIFT 25
#define GEN7_SF_DW3_TRUE_AA_LINE_DISTANCE (0x1 << 14)
+#define GEN8_SF_DW3_SMOOTH_POINT_ENABLE (0x1 << 13)
#define GEN7_SF_DW3_SUBPIXEL__MASK 0x00001000
#define GEN7_SF_DW3_SUBPIXEL__SHIFT 12
#define GEN7_SF_DW3_SUBPIXEL_8BITS (0x0 << 12)
#define GEN7_3DSTATE_SBE_DW1__SIZE 13
-#define GEN8_SBE_DW1_USE_URB_READ_LEN (0x1 << 29)
-#define GEN8_SBE_DW1_USE_URB_READ_OFFSET (0x1 << 28)
+#define GEN8_SBE_DW1_FORCE_URB_READ_LEN (0x1 << 29)
+#define GEN8_SBE_DW1_FORCE_URB_READ_OFFSET (0x1 << 28)
#define GEN7_SBE_DW1_ATTR_SWIZZLE__MASK 0x10000000
#define GEN7_SBE_DW1_ATTR_SWIZZLE__SHIFT 28
#define GEN7_SBE_DW1_ATTR_SWIZZLE_0_15 (0x0 << 28)
#define GEN7_SBE_DW1_POINT_SPRITE_TEXCOORD__SHIFT 20
#define GEN7_SBE_DW1_POINT_SPRITE_TEXCOORD_UPPERLEFT (0x0 << 20)
#define GEN7_SBE_DW1_POINT_SPRITE_TEXCOORD_LOWERLEFT (0x1 << 20)
+#define GEN8_SBE_DW1_PID_OVERRIDE_W (0x1 << 19)
+#define GEN8_SBE_DW1_PID_OVERRIDE_Z (0x1 << 18)
+#define GEN8_SBE_DW1_PID_OVERRIDE_Y (0x1 << 17)
+#define GEN8_SBE_DW1_PID_OVERRIDE_X (0x1 << 16)
#define GEN7_SBE_DW1_URB_READ_LEN__MASK 0x0000f800
#define GEN7_SBE_DW1_URB_READ_LEN__SHIFT 11
#define GEN7_SBE_DW1_URB_READ_OFFSET__MASK 0x000003f0
#define GEN7_SBE_DW1_URB_READ_OFFSET__SHIFT 4
#define GEN8_SBE_DW1_URB_READ_OFFSET__MASK 0x000007e0
#define GEN8_SBE_DW1_URB_READ_OFFSET__SHIFT 5
+#define GEN8_SBE_DW1_PID_OVERRIDE_ATTR__MASK 0x0000001f
+#define GEN8_SBE_DW1_PID_OVERRIDE_ATTR__SHIFT 0
#define GEN8_3DSTATE_SBE_SWIZ_DW1_DW8__SIZE 8
#define GEN8_SBE_SWIZ_HIGH__MASK 0xffff0000
#define GEN8_SBE_SWIZ_HIGH__SHIFT 16
-#define GEN8_SBE_SWIZ_OVERRIDE_W (0x1 << 15)
-#define GEN8_SBE_SWIZ_OVERRIDE_Z (0x1 << 14)
-#define GEN8_SBE_SWIZ_OVERRIDE_Y (0x1 << 13)
-#define GEN8_SBE_SWIZ_OVERRIDE_X (0x1 << 12)
+#define GEN8_SBE_SWIZ_CONST_OVERRIDE_W (0x1 << 15)
+#define GEN8_SBE_SWIZ_CONST_OVERRIDE_Z (0x1 << 14)
+#define GEN8_SBE_SWIZ_CONST_OVERRIDE_Y (0x1 << 13)
+#define GEN8_SBE_SWIZ_CONST_OVERRIDE_X (0x1 << 12)
+#define GEN8_SBE_SWIZ_SWIZZLE_CONTROL (0x1 << 11)
#define GEN8_SBE_SWIZ_CONST__MASK 0x00000600
#define GEN8_SBE_SWIZ_CONST__SHIFT 9
#define GEN8_SBE_SWIZ_CONST_0000 (0x0 << 9)
#define GEN9_RASTER_DW1_Z_TEST_FAR_ENABLE (0x1 << 26)
+#define GEN8_RASTER_DW1_API__MASK 0x00c00000
+#define GEN8_RASTER_DW1_API__SHIFT 22
+#define GEN8_RASTER_DW1_API_DX9_OGL (0x0 << 22)
+#define GEN8_RASTER_DW1_API_DX10 (0x1 << 22)
+#define GEN8_RASTER_DW1_API_DX10_1 (0x2 << 22)
#define GEN8_RASTER_DW1_FRONT_WINDING__MASK 0x00200000
#define GEN8_RASTER_DW1_FRONT_WINDING__SHIFT 21
+#define GEN8_RASTER_DW1_FORCED_SAMPLE_COUNT__MASK 0x001c0000
+#define GEN8_RASTER_DW1_FORCED_SAMPLE_COUNT__SHIFT 18
+#define GEN8_RASTER_DW1_FORCED_SAMPLE_COUNT_NUMRASTSAMPLES_0 (0x0 << 18)
+#define GEN8_RASTER_DW1_FORCED_SAMPLE_COUNT_NUMRASTSAMPLES_1 (0x1 << 18)
+#define GEN8_RASTER_DW1_FORCED_SAMPLE_COUNT_NUMRASTSAMPLES_2 (0x2 << 18)
+#define GEN8_RASTER_DW1_FORCED_SAMPLE_COUNT_NUMRASTSAMPLES_4 (0x3 << 18)
+#define GEN8_RASTER_DW1_FORCED_SAMPLE_COUNT_NUMRASTSAMPLES_8 (0x4 << 18)
+#define GEN8_RASTER_DW1_FORCED_SAMPLE_COUNT_NUMRASTSAMPLES_16 (0x5 << 18)
#define GEN8_RASTER_DW1_CULL_MODE__MASK 0x00030000
#define GEN8_RASTER_DW1_CULL_MODE__SHIFT 16
+#define GEN8_RASTER_DW1_FORCE_MULTISAMPLE_ENABLE (0x1 << 14)
#define GEN8_RASTER_DW1_SMOOTH_POINT_ENABLE (0x1 << 13)
-#define GEN8_RASTER_DW1_API_MULTISAMPLE_ENABLE (0x1 << 12)
+#define GEN8_RASTER_DW1_DX_MULTISAMPLE_ENABLE (0x1 << 12)
+#define GEN8_RASTER_DW1_DX_MSRASTMODE__MASK 0x00000c00
+#define GEN8_RASTER_DW1_DX_MSRASTMODE__SHIFT 10
#define GEN8_RASTER_DW1_DEPTH_OFFSET_SOLID (0x1 << 9)
#define GEN8_RASTER_DW1_DEPTH_OFFSET_WIREFRAME (0x1 << 8)
#define GEN8_RASTER_DW1_DEPTH_OFFSET_POINT (0x1 << 7)
#define GEN7_WM_DW1_STATISTICS (0x1 << 31)
-#define GEN7_WM_DW1_DEPTH_CLEAR (0x1 << 30)
+#define GEN7_WM_DW1_LEGACY_DEPTH_CLEAR (0x1 << 30)
#define GEN7_WM_DW1_PS_DISPATCH_ENABLE (0x1 << 29)
-#define GEN7_WM_DW1_DEPTH_RESOLVE (0x1 << 28)
-#define GEN7_WM_DW1_HIZ_RESOLVE (0x1 << 27)
+#define GEN7_WM_DW1_LEGACY_DEPTH_RESOLVE (0x1 << 28)
+#define GEN7_WM_DW1_LEGACY_HIZ_RESOLVE (0x1 << 27)
#define GEN7_WM_DW1_LEGACY_LINE_RAST (0x1 << 26)
#define GEN7_WM_DW1_PS_KILL_PIXEL (0x1 << 25)
#define GEN7_WM_DW1_PSCDEPTH__MASK 0x01800000
#define GEN7_WM_DW1_EDSC__SHIFT 21
#define GEN7_WM_DW1_PS_USE_DEPTH (0x1 << 20)
#define GEN7_WM_DW1_PS_USE_W (0x1 << 19)
+#define GEN8_WM_DW1_FORCE_DISPATCH_ENABLE__MASK 0x00180000
+#define GEN8_WM_DW1_FORCE_DISPATCH_ENABLE__SHIFT 19
+#define GEN8_WM_DW1_FORCE_DISPATCH_ENABLE_NORMAL (0x0 << 19)
+#define GEN8_WM_DW1_FORCE_DISPATCH_ENABLE_OFF (0x1 << 19)
+#define GEN8_WM_DW1_FORCE_DISPATCH_ENABLE_ON (0x2 << 19)
#define GEN7_WM_DW1_ZW_INTERP__MASK 0x00060000
#define GEN7_WM_DW1_ZW_INTERP__SHIFT 17
#define GEN7_WM_DW1_BARYCENTRIC_INTERP__MASK 0x0001f800
#define GEN7_WM_DW1_POINT_RASTRULE_UPPER_RIGHT (0x1 << 2)
#define GEN7_WM_DW1_MSRASTMODE__MASK 0x00000003
#define GEN7_WM_DW1_MSRASTMODE__SHIFT 0
+#define GEN8_WM_DW1_FORCE_KILL_PIXEL__MASK 0x00000003
+#define GEN8_WM_DW1_FORCE_KILL_PIXEL__SHIFT 0
+#define GEN8_WM_DW1_FORCE_KILL_PIXEL_NORMAL 0x0
+#define GEN8_WM_DW1_FORCE_KILL_PIXEL_OFF 0x1
+#define GEN8_WM_DW1_FORCE_KILL_PIXEL_ON 0x2
#define GEN7_WM_DW2_MSDISPMODE__MASK 0x80000000
#define GEN7_WM_DW2_MSDISPMODE__SHIFT 31
#define GEN8_3DSTATE_WM_CHROMAKEY__SIZE 2
+#define GEN8_CHROMAKEY_DW1_KILL_ENABLE (0x1 << 31)
#define GEN8_3DSTATE_WM_DEPTH_STENCIL__SIZE 4
#define GEN8_WM_HZ_DW1_STENCIL_CLEAR (0x1 << 31)
#define GEN8_WM_HZ_DW1_DEPTH_CLEAR (0x1 << 30)
+#define GEN8_WM_HZ_DW1_SCISSOR_ENABLE (0x1 << 29)
#define GEN8_WM_HZ_DW1_DEPTH_RESOLVE (0x1 << 28)
#define GEN8_WM_HZ_DW1_HIZ_RESOLVE (0x1 << 27)
#define GEN8_WM_HZ_DW1_PIXEL_OFFSET_ENABLE (0x1 << 26)
#define GEN8_PS_BLEND_DW1_ALPHA_TO_COVERAGE (0x1 << 31)
#define GEN8_PS_BLEND_DW1_WRITABLE_RT (0x1 << 30)
-#define GEN8_PS_BLEND_DW1_BLEND_ENABLE (0x1 << 29)
-#define GEN8_PS_BLEND_DW1_SRC_ALPHA_FACTOR__MASK 0x1f000000
-#define GEN8_PS_BLEND_DW1_SRC_ALPHA_FACTOR__SHIFT 24
-#define GEN8_PS_BLEND_DW1_DST_ALPHA_FACTOR__MASK 0x00f80000
-#define GEN8_PS_BLEND_DW1_DST_ALPHA_FACTOR__SHIFT 19
-#define GEN8_PS_BLEND_DW1_SRC_COLOR_FACTOR__MASK 0x0007c000
-#define GEN8_PS_BLEND_DW1_SRC_COLOR_FACTOR__SHIFT 14
-#define GEN8_PS_BLEND_DW1_DST_COLOR_FACTOR__MASK 0x00003e00
-#define GEN8_PS_BLEND_DW1_DST_COLOR_FACTOR__SHIFT 9
+#define GEN8_PS_BLEND_DW1_RT0_BLEND_ENABLE (0x1 << 29)
+#define GEN8_PS_BLEND_DW1_RT0_SRC_ALPHA_FACTOR__MASK 0x1f000000
+#define GEN8_PS_BLEND_DW1_RT0_SRC_ALPHA_FACTOR__SHIFT 24
+#define GEN8_PS_BLEND_DW1_RT0_DST_ALPHA_FACTOR__MASK 0x00f80000
+#define GEN8_PS_BLEND_DW1_RT0_DST_ALPHA_FACTOR__SHIFT 19
+#define GEN8_PS_BLEND_DW1_RT0_SRC_COLOR_FACTOR__MASK 0x0007c000
+#define GEN8_PS_BLEND_DW1_RT0_SRC_COLOR_FACTOR__SHIFT 14
+#define GEN8_PS_BLEND_DW1_RT0_DST_COLOR_FACTOR__MASK 0x00003e00
+#define GEN8_PS_BLEND_DW1_RT0_DST_COLOR_FACTOR__SHIFT 9
#define GEN8_PS_BLEND_DW1_ALPHA_TEST_ENABLE (0x1 << 8)
-#define GEN8_PS_BLEND_DW1_INDEPENDENT_ALPHA_ENABLE (0x1 << 7)
+#define GEN8_PS_BLEND_DW1_RT0_INDEPENDENT_ALPHA_ENABLE (0x1 << 7)
#define GEN6_3DSTATE_CONSTANT_ANY__SIZE 11
#define GEN6_CONSTANT_DW_ADDR_ADDR__SHR 5
+#define GEN8_CONSTANT_DW0_MOCS__MASK 0x00007f00
+#define GEN8_CONSTANT_DW0_MOCS__SHIFT 8
#define GEN7_CONSTANT_DW1_BUFFER1_READ_LEN__MASK 0xffff0000
#define GEN7_CONSTANT_DW1_BUFFER1_READ_LEN__SHIFT 16
#define GEN6_3DSTATE_DRAWING_RECTANGLE__SIZE 4
+#define GEN8_DRAWING_RECTANGLE_DW0_CORE_MODE_SELECT__MASK 0x0000c000
+#define GEN8_DRAWING_RECTANGLE_DW0_CORE_MODE_SELECT__SHIFT 14
#define GEN6_DRAWING_RECTANGLE_DW1_MIN_Y__MASK 0xffff0000
#define GEN6_DRAWING_RECTANGLE_DW1_MIN_Y__SHIFT 16
#define GEN8_DEPTH_DW5_MOCS__MASK 0x0000007f
#define GEN8_DEPTH_DW5_MOCS__SHIFT 0
-#define GEN8_DEPTH_DW6_OFFSET_Y__MASK 0xffff0000
-#define GEN8_DEPTH_DW6_OFFSET_Y__SHIFT 16
-#define GEN8_DEPTH_DW6_OFFSET_X__MASK 0x0000ffff
-#define GEN8_DEPTH_DW6_OFFSET_X__SHIFT 0
#define GEN8_DEPTH_DW7_RT_VIEW_EXTENT__MASK 0xffe00000
#define GEN8_DEPTH_DW7_RT_VIEW_EXTENT__SHIFT 21
#define GEN8_DEPTH_DW7_QPITCH__MASK 0x00007fff
#define GEN8_DEPTH_DW7_QPITCH__SHIFT 0
+#define GEN8_DEPTH_DW7_QPITCH__SHR 2
#define GEN6_3DSTATE_POLY_STIPPLE_OFFSET__SIZE 2
#define GEN6_3DSTATE_LINE_STIPPLE__SIZE 3
+#define GEN6_LINE_STIPPLE_DW1_CURRENT_MODIFY_ENABLE (0x1 << 31)
+#define GEN6_LINE_STIPPLE_DW1_CURRENT_REPEAT_COUNTER__MASK 0x3fe00000
+#define GEN6_LINE_STIPPLE_DW1_CURRENT_REPEAT_COUNTER__SHIFT 21
+#define GEN6_LINE_STIPPLE_DW1_CURRENT_STIPPLE_INDEX__MASK 0x000f0000
+#define GEN6_LINE_STIPPLE_DW1_CURRENT_STIPPLE_INDEX__SHIFT 16
#define GEN6_LINE_STIPPLE_DW1_PATTERN__MASK 0x0000ffff
#define GEN6_LINE_STIPPLE_DW1_PATTERN__SHIFT 0
#define GEN6_3DSTATE_AA_LINE_PARAMETERS__SIZE 3
+#define GEN8_AA_LINE_DW1_POINT_BIAS__MASK 0xff000000
+#define GEN8_AA_LINE_DW1_POINT_BIAS__SHIFT 24
+#define GEN8_AA_LINE_DW1_POINT_BIAS__RADIX 8
#define GEN6_AA_LINE_DW1_BIAS__MASK 0x00ff0000
#define GEN6_AA_LINE_DW1_BIAS__SHIFT 16
#define GEN6_AA_LINE_DW1_BIAS__RADIX 8
+#define GEN8_AA_LINE_DW1_POINT_SLOPE__MASK 0x0000ff00
+#define GEN8_AA_LINE_DW1_POINT_SLOPE__SHIFT 8
+#define GEN8_AA_LINE_DW1_POINT_SLOPE__RADIX 8
#define GEN6_AA_LINE_DW1_SLOPE__MASK 0x000000ff
#define GEN6_AA_LINE_DW1_SLOPE__SHIFT 0
#define GEN6_AA_LINE_DW1_SLOPE__RADIX 8
+#define GEN8_AA_LINE_DW2_POINT_CAP_BIAS__MASK 0xff000000
+#define GEN8_AA_LINE_DW2_POINT_CAP_BIAS__SHIFT 24
+#define GEN8_AA_LINE_DW2_POINT_CAP_BIAS__RADIX 8
#define GEN6_AA_LINE_DW2_CAP_BIAS__MASK 0x00ff0000
#define GEN6_AA_LINE_DW2_CAP_BIAS__SHIFT 16
#define GEN6_AA_LINE_DW2_CAP_BIAS__RADIX 8
+#define GEN8_AA_LINE_DW2_POINT_CAP_SLOPE__MASK 0x0000ff00
+#define GEN8_AA_LINE_DW2_POINT_CAP_SLOPE__SHIFT 8
+#define GEN8_AA_LINE_DW2_POINT_CAP_SLOPE__RADIX 8
#define GEN6_AA_LINE_DW2_CAP_SLOPE__MASK 0x000000ff
#define GEN6_AA_LINE_DW2_CAP_SLOPE__SHIFT 0
#define GEN6_AA_LINE_DW2_CAP_SLOPE__RADIX 8
#define GEN6_3DSTATE_MULTISAMPLE__SIZE 4
-#define GEN75_MULTISAMPLE_DW1_DX9_MULTISAMPLE_ENABLE (0x1 << 5)
+#define GEN75_MULTISAMPLE_DW1_PIXEL_OFFSET_ENABLE (0x1 << 5)
#define GEN6_MULTISAMPLE_DW1_PIXEL_LOCATION__MASK 0x00000010
#define GEN6_MULTISAMPLE_DW1_PIXEL_LOCATION__SHIFT 4
#define GEN6_MULTISAMPLE_DW1_NUM_SAMPLES__MASK 0x0000000e
#define GEN8_STENCIL_DW4_QPITCH__MASK 0x00007fff
#define GEN8_STENCIL_DW4_QPITCH__SHIFT 0
+#define GEN8_STENCIL_DW4_QPITCH__SHR 2
#define GEN6_3DSTATE_HIER_DEPTH_BUFFER__SIZE 5
#define GEN8_HIZ_DW4_QPITCH__MASK 0x00007fff
#define GEN8_HIZ_DW4_QPITCH__SHIFT 0
+#define GEN8_HIZ_DW4_QPITCH__SHR 2
#define GEN6_3DSTATE_CLEAR_PARAMS__SIZE 3
projects / mesa.git / commitdiff