Fix width of D

diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc
index 3cfaa93715bab55c6d5ca483c9e496e9f029176c..adc09a6e42e0ab95fec70b8079f471df7d97a236 100644 (file)
--- a/passes/pmgen/xilinx_dsp.cc
+++ b/passes/pmgen/xilinx_dsp.cc
@@ -48,7 +48,7 @@ static Cell* addDsp(Module *module) {
        cell->setParam(ID(USE_SIMD), Const("ONE48"));
        cell->setParam(ID(USE_DPORT), Const("FALSE"));
 
-       cell->setPort(ID(D), Const(0, 24));
+       cell->setPort(ID(D), Const(0, 25));
        cell->setPort(ID(INMODE), Const(0, 5));
        cell->setPort(ID(ALUMODE), Const(0, 4));
        cell->setPort(ID(OPMODE), Const(0, 7));