split out instructions from openpower/isa/branch.mdwn

diff --git a/openpower/isa/branch.mdwn b/openpower/isa/branch.mdwn
index 5867ea87292138c48259a3fbb8d74103f886d9c0..dd2b56d28d0bf4bf2a3cf54ced4daae3a2b52c28 100644 (file)
--- a/openpower/isa/branch.mdwn
+++ b/openpower/isa/branch.mdwn
@@ -20,111 +20,12 @@
 <!-- If LK=1 then the effective address of the instruction following the Branch -->
 <!-- instruction is placed into the Link Register. -->
 
-# Branch
+[[!inline pagenames="openpower/isa/branch/b" raw="yes"]]
 
-I-Form
+[[!inline pagenames="openpower/isa/branch/bc" raw="yes"]]
 
-* b target_addr (AA=0 LK=0)
-* ba target_addr (AA=1 LK=0)
-* bl target_addr (AA=0 LK=1)
-* bla target_addr (AA=1 LK=1)
+[[!inline pagenames="openpower/isa/branch/bclr" raw="yes"]]
 
-Pseudo-code:
+[[!inline pagenames="openpower/isa/branch/bcctr" raw="yes"]]
 
-    if AA then NIA  <-iea EXTS(LI || 0b00)
-    else       NIA  <-iea CIA + EXTS(LI || 0b00)
-    if LK then LR <-iea  CIA + 4
-
-Special Registers Altered:
-
-    LR                       (if LK=1)
-
-# Branch Conditional
-
-B-Form
-
-* bc BO,BI,target_addr (AA=0 LK=0)
-* bca BO,BI,target_addr (AA=1 LK=0)
-* bcl BO,BI,target_addr (AA=0 LK=1)
-* bcla BO,BI,target_addr (AA=1 LK=1)
-
-Pseudo-code:
-
-    if (mode_is_64bit) then M <- 0
-    else M <- 32
-    if ¬BO[2] then CTR <- CTR - 1
-    ctr_ok <- BO[2] | ((CTR[M:63] != 0) ^ BO[3])
-    cond_ok <- BO[0] | ¬(CR[BI+32] ^ BO[1])
-    if ctr_ok & cond_ok then
-      if AA then NIA <-iea EXTS(BD || 0b00)
-      else       NIA <-iea CIA + EXTS(BD || 0b00)
-    if LK then LR  <-iea  CIA + 4
-
-Special Registers Altered:
-
-    CTR                    (if BO2=0)
-    LR                       (if LK=1)
-
-# Branch Conditional to Link Register
-
-XL-Form
-
-* bclr BO,BI,BH (LK=0)
-* bclrl BO,BI,BH (LK=1)
-
-Pseudo-code:
-
-    if (mode_is_64bit) then M <- 0
-    else M <- 32
-    if ¬BO[2]  then CTR <- CTR - 1
-    ctr_ok <- BO[2] | ((CTR[M:63] != 0) ^ BO[3])
-    cond_ok <- BO[0] | ¬(CR[BI+32] ^  BO[1])
-    if ctr_ok & cond_ok then NIA <-iea LR[0:61] || 0b00
-    if LK then LR <-iea CIA + 4
-
-Special Registers Altered:
-
-    CTR                    (if BO2=0)
-    LR                       (if LK=1)
-
-# Branch Conditional to Count Register
-
-XL-Form
-
-* bcctr BO,BI,BH (LK=0)
-* bcctrl BO,BI,BH (LK=1)
-
-Pseudo-code:
-
-    cond_ok <- BO[0] | ¬(CR[BI+32] ^ BO[1])
-    if cond_ok then NIA <-iea CTR[0:61] || 0b00
-    if LK then LR <-iea CIA + 4
-
-Special Registers Altered:
-
-    LR                     (if LK=1)
-
-# Branch Conditional to Branch Target Address Register
-
-XL-Form
-
-* bctar BO,BI,BH (LK=0)
-* bctarl BO,BI,BH (LK=1)
-
-Pseudo-code:
-
-    if (mode_is_64bit) then M <- 0
-    else M <- 32
-    if ¬BO[2] then CTR <- CTR - 1
-    ctr_ok <- BO[2]  | ((CTR[M:63] != 0) ^ BO[3])
-    cond_ok <- BO[0] | ¬(CR[BI+32] ^ BO[1])
-    if ctr_ok & cond_ok then NIA <-iea TAR[0:61]  || 0b00
-    if LK then LR <-iea  CIA + 4
-
-Special Registers Altered:
-
-    CTR                    (if BO2=0)
-    LR                       (if LK=1)
-
-
-<!-- Checked March 2021 -->
+[[!inline pagenames="openpower/isa/branch/bctar" raw="yes"]]

diff --git a/openpower/isa/branch/b.mdwn b/openpower/isa/branch/b.mdwn
new file mode 100644 (file)
index 0000000..ca7efda
--- /dev/null
+++ b/openpower/isa/branch/b.mdwn
@@ -0,0 +1,16 @@
+# Branch
+
+I-Form
+
+* b target_addr (AA=0 LK=0)
+* ba target_addr (AA=1 LK=0)
+* bl target_addr (AA=0 LK=1)
+* bla target_addr (AA=1 LK=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/branch/b_code" raw="yes"]]
+
+Special Registers Altered:
+
+    LR                       (if LK=1)

diff --git a/openpower/isa/branch/b_code.mdwn b/openpower/isa/branch/b_code.mdwn
new file mode 100644 (file)
index 0000000..0491ce5
--- /dev/null
+++ b/openpower/isa/branch/b_code.mdwn
@@ -0,0 +1,3 @@
+    if AA then NIA  <-iea EXTS(LI || 0b00)
+    else       NIA  <-iea CIA + EXTS(LI || 0b00)
+    if LK then LR <-iea  CIA + 4

diff --git a/openpower/isa/branch/bc.mdwn b/openpower/isa/branch/bc.mdwn
new file mode 100644 (file)
index 0000000..ed0c842
--- /dev/null
+++ b/openpower/isa/branch/bc.mdwn
@@ -0,0 +1,17 @@
+# Branch Conditional
+
+B-Form
+
+* bc BO,BI,target_addr (AA=0 LK=0)
+* bca BO,BI,target_addr (AA=1 LK=0)
+* bcl BO,BI,target_addr (AA=0 LK=1)
+* bcla BO,BI,target_addr (AA=1 LK=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/branch/bc_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CTR                    (if BO2=0)
+    LR                       (if LK=1)

diff --git a/openpower/isa/branch/bc_code.mdwn b/openpower/isa/branch/bc_code.mdwn
new file mode 100644 (file)
index 0000000..dfc9b6a
--- /dev/null
+++ b/openpower/isa/branch/bc_code.mdwn
@@ -0,0 +1,9 @@
+    if (mode_is_64bit) then M <- 0
+    else M <- 32
+    if ¬BO[2] then CTR <- CTR - 1
+    ctr_ok <- BO[2] | ((CTR[M:63] != 0) ^ BO[3])
+    cond_ok <- BO[0] | ¬(CR[BI+32] ^ BO[1])
+    if ctr_ok & cond_ok then
+      if AA then NIA <-iea EXTS(BD || 0b00)
+      else       NIA <-iea CIA + EXTS(BD || 0b00)
+    if LK then LR  <-iea  CIA + 4

diff --git a/openpower/isa/branch/bcctr.mdwn b/openpower/isa/branch/bcctr.mdwn
new file mode 100644 (file)
index 0000000..4addc1c
--- /dev/null
+++ b/openpower/isa/branch/bcctr.mdwn
@@ -0,0 +1,14 @@
+# Branch Conditional to Count Register
+
+XL-Form
+
+* bcctr BO,BI,BH (LK=0)
+* bcctrl BO,BI,BH (LK=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/branch/bcctr_code" raw="yes"]]
+
+Special Registers Altered:
+
+    LR                     (if LK=1)

diff --git a/openpower/isa/branch/bcctr_code.mdwn b/openpower/isa/branch/bcctr_code.mdwn
new file mode 100644 (file)
index 0000000..d6a8c81
--- /dev/null
+++ b/openpower/isa/branch/bcctr_code.mdwn
@@ -0,0 +1,3 @@
+    cond_ok <- BO[0] | ¬(CR[BI+32] ^ BO[1])
+    if cond_ok then NIA <-iea CTR[0:61] || 0b00
+    if LK then LR <-iea CIA + 4

diff --git a/openpower/isa/branch/bclr.mdwn b/openpower/isa/branch/bclr.mdwn
new file mode 100644 (file)
index 0000000..2670013
--- /dev/null
+++ b/openpower/isa/branch/bclr.mdwn
@@ -0,0 +1,15 @@
+# Branch Conditional to Link Register
+
+XL-Form
+
+* bclr BO,BI,BH (LK=0)
+* bclrl BO,BI,BH (LK=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/branch/bclr_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CTR                    (if BO2=0)
+    LR                       (if LK=1)

diff --git a/openpower/isa/branch/bclr_code.mdwn b/openpower/isa/branch/bclr_code.mdwn
new file mode 100644 (file)
index 0000000..ea8a5aa
--- /dev/null
+++ b/openpower/isa/branch/bclr_code.mdwn
@@ -0,0 +1,7 @@
+    if (mode_is_64bit) then M <- 0
+    else M <- 32
+    if ¬BO[2]  then CTR <- CTR - 1
+    ctr_ok <- BO[2] | ((CTR[M:63] != 0) ^ BO[3])
+    cond_ok <- BO[0] | ¬(CR[BI+32] ^  BO[1])
+    if ctr_ok & cond_ok then NIA <-iea LR[0:61] || 0b00
+    if LK then LR <-iea CIA + 4

diff --git a/openpower/isa/branch/bctar.mdwn b/openpower/isa/branch/bctar.mdwn
new file mode 100644 (file)
index 0000000..7cabee2
--- /dev/null
+++ b/openpower/isa/branch/bctar.mdwn
@@ -0,0 +1,18 @@
+# Branch Conditional to Branch Target Address Register
+
+XL-Form
+
+* bctar BO,BI,BH (LK=0)
+* bctarl BO,BI,BH (LK=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/branch/bctar_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CTR                    (if BO2=0)
+    LR                       (if LK=1)
+
+
+<!-- Checked March 2021 -->

diff --git a/openpower/isa/branch/bctar_code.mdwn b/openpower/isa/branch/bctar_code.mdwn
new file mode 100644 (file)
index 0000000..04319a7
--- /dev/null
+++ b/openpower/isa/branch/bctar_code.mdwn
@@ -0,0 +1,7 @@
+    if (mode_is_64bit) then M <- 0
+    else M <- 32
+    if ¬BO[2] then CTR <- CTR - 1
+    ctr_ok <- BO[2]  | ((CTR[M:63] != 0) ^ BO[3])
+    cond_ok <- BO[0] | ¬(CR[BI+32] ^ BO[1])
+    if ctr_ok & cond_ok then NIA <-iea TAR[0:61]  || 0b00
+    if LK then LR <-iea  CIA + 4