mips.c (mips_issue_rate): Return 4 for 74K processors.

gcc/
2007-07-03  David Ung  <davidu@mips.com>

	* config/mips/mips.c (mips_issue_rate): Return 4 for 74K processors.

From-SVN: r126268

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index e58836cad6dbe04762ac29110169420c54b7e11d..e63b3341dced2dff0837225d4798823e408fe45a 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,7 @@
+2007-07-03  David Ung  <davidu@mips.com>
+
+       * config/mips/mips.c (mips_issue_rate): Return 4 for 74K processors.
+
 2007-07-03  David Ung  <davidu@mips.com>
            Richard Sandiford  <richard@codesourcery.com>
 

diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 3331b9e7a683929dc00659215052b7a8af90f80e..0cb1d1a8c6547a7b6eab689d426969bc5329d277 100644 (file)
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -10813,6 +10813,12 @@ mips_issue_rate (void)
     case PROCESSOR_74KF2_1:
     case PROCESSOR_74KF1_1:
     case PROCESSOR_74KF3_2:
+      /* The 74k is not strictly quad-issue cpu, but can be seen as one
+        by the scheduler.  It can issue 1 ALU, 1 AGEN and 2 FPU insns,
+        but in reality only a maximum of 3 insns can be issued as the
+        floating point load/stores also require a slot in the AGEN pipe.  */
+     return 4;
+
     case PROCESSOR_R4130:
     case PROCESSOR_R5400:
     case PROCESSOR_R5500: