back.pysim: delay clock processes by one half period.

Makes it easier to see initial delta cycles.

diff --git a/nmigen/back/pysim.py b/nmigen/back/pysim.py
index 3975443897c670b0a070bf5862848fe391455ba2..478a73843f5dde375ddc0a26774da5e7ec5d2daa 100644 (file)
--- a/nmigen/back/pysim.py
+++ b/nmigen/back/pysim.py
@@ -231,6 +231,7 @@ class Simulator:
         half_period = period / 2
         def clk_process():
             yield Passive()
+            yield Delay(half_period)
             while True:
                 yield clk.eq(1)
                 yield Delay(half_period)