+2016-11-17 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * gcc.target/arc/abitest.S: New file.
+ * gcc.target/arc/abitest.h: Likewise.
+ * gcc.target/arc/va_args-1.c: Likewise.
+ * gcc.target/arc/va_args-2.c: Likewise.
+ * gcc.target/arc/va_args-3.c: Likewise.
+ * gcc.target/arc/mcrc.c: Deleted.
+ * gcc.target/arc/mdsp-packa.c: Likewise.
+ * gcc.target/arc/mdvbf.c: Likewise.
+ * gcc.target/arc/mmac-24.c: Likewise.
+ * gcc.target/arc/mmac-d16.c: Likewise.
+ * gcc.target/arc/mno-crc.c: Likewise.
+ * gcc.target/arc/mno-dsp-packa.c: Likewise.
+ * gcc.target/arc/mno-dvbf.c: Likewise.
+ * gcc.target/arc/mno-mac-24.c: Likewise.
+ * gcc.target/arc/mno-mac-d16.c: Likewise.
+ * gcc.target/arc/mno-rtsc.c: Likewise.
+ * gcc.target/arc/mno-xy.c: Likewise.
+ * gcc.target/arc/mrtsc.c: Likewise.
+ * gcc.target/arc/arc.exp (check_effective_target_arcem): New
+ function.
+ (check_effective_target_arc700): Likewise.
+ (check_effective_target_arc6xx): Likewise.
+ (check_effective_target_arcmpy): Likewise.
+ (check_effective_target_archs): Likewise.
+ (check_effective_target_clmcpu): Likewise.
+ (check_effective_target_barrelshifter): Likewise.
+ * gcc.target/arc/barrel-shifter-1.c: Changed.
+ * gcc.target/arc/builtin_simd.c: Test only for ARC700 cpus.
+ * gcc.target/arc/cmem-1.c: Changed.
+ * gcc.target/arc/cmem-2.c: Likewise.
+ * gcc.target/arc/cmem-3.c: Likewise.
+ * gcc.target/arc/cmem-4.c: Likewise.
+ * gcc.target/arc/cmem-5.c: Likewise.
+ * gcc.target/arc/cmem-6.c: Likewise.
+ * gcc.target/arc/cmem-7.c: Likewise.
+ * gcc.target/arc/interrupt-1.c: Test for RTIE as well.
+ * gcc.target/arc/interrupt-2.c: Skip it for ARCv2 cores.
+ * gcc.target/arc/interrupt-3.c: Match also ARCv2 warnings.
+ * gcc.target/arc/jump-around-jump.c: Update options.
+ * gcc.target/arc/mARC601.c: Changed.
+ * gcc.target/arc/mcpu-arc600.c: Changed.
+ * gcc.target/arc/mcpu-arc601.c: Changed.
+ * gcc.target/arc/mcpu-arc700.c: Changed.
+ * gcc.target/arc/mdpfp.c: Skip for ARCv2 cores.
+ * gcc.target/arc/movb-1.c: Changed.
+ * gcc.target/arc/movb-2.c: Likewise.
+ * gcc.target/arc/movb-3.c: Likewise.
+ * gcc.target/arc/movb-4.c: Likewise.
+ * gcc.target/arc/movb-5.c: Likewise.
+ * gcc.target/arc/movb_cl-1.c: Likewise.
+ * gcc.target/arc/movb_cl-2.c: Likewise.
+ * gcc.target/arc/movbi_cl-1.c: Likewise.
+ * gcc.target/arc/movh_cl-1.c: Likewise.
+ * gcc.target/arc/mspfp.c: Skip for ARC HS cores.
+ * gcc.target/arc/mul64.c: Enable it only for ARC600.
+ * gcc.target/arc/mulsi3_highpart-1.c: Scan for ARCv2 instructions.
+ * gcc.target/arc/mulsi3_highpart-2.c: Skip it for ARCv1 cores.
+ * gcc.target/arc/no-dpfp-lrsr.c: Skip it for ARC HS.
+ * gcc.target/arc/trsub.c: Only for ARC EM cores.
+ * gcc.target/arc/builtin_simdarc.c: Changed.
+ * gcc.target/arc/extzv-1.c: Likewise.
+ * gcc.target/arc/insv-1.c: Likewise.
+ * gcc.target/arc/insv-2.c: Likewise.
+ * gcc.target/arc/mA6.c: Likewise.
+ * gcc.target/arc/mA7.c: Likewise.
+ * gcc.target/arc/mARC600.c: Likewise.
+ * gcc.target/arc/mARC700.c: Likewise.
+ * gcc.target/arc/mcpu-arc600.c: Likewise.
+ * gcc.target/arc/mcpu-arc700.c: Likewise.
+ * gcc.target/arc/movl-1.c: Likewise.
+ * gcc.target/arc/nps400-1.c: Likewise.
+ * gcc.target/arc/trsub.c: Likewise.
+ * gcc.target/arc/barrel-shifter-2.c: Check for barrel shifter
+ configuration.
+ * gcc.target/arc/mlock.c: Skip for arc6xx configurations.
+ * gcc.target/arc/mswape.c: Likewise.
+
2016-11-17 Paolo Carlini <paolo.carlini@oracle.com>
PR c++/68180
--- /dev/null
+/* { dg-do assemble } */
+#ifndef ENTRY
+#define ENTRY(nm) \
+ .text ` \
+ .align 4 ` \
+ .globl nm ` \
+ .type nm,@function ` \
+nm:
+#endif
+
+#ifndef END
+#define END(name) .size name,.-name
+#endif
+
+ENTRY(tsyscall)
+ENTRY(clone)
+ add r0,r0,r1
+ add r0,r0,r2
+ add r0,r0,r3
+ add r0,r0,r4
+ add r0,r0,r5
+ j_s.d [blink]
+ add r0,r0,r6
+END(tsyscall)
+END(clone)
+
+ENTRY(abidi)
+ add.f r0,r1,1
+ j_s.d [blink]
+ adc r1,r2,0
+END(abidi)
--- /dev/null
+#ifndef _DG_ABITEST_H
+#define _DG_ABITEST_H 1
+
+#ifdef __ASSEMBLER__
+
+#define ENTRY(nm) \
+ .text ` \
+ .align 4 ` \
+ .globl nm ` \
+ .type nm,@function ` \
+nm:
+
+#define END(name) .size name,.-name
+
+#endif /* __ASSEMBLER __*/
+
+#endif /*_DG_ABITEST_H*/
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3 of the License, or
# (at your option) any later version.
-#
+#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
-#
+#
# You should have received a copy of the GNU General Public License
# along with GCC; see the file COPYING3. If not see
# <http://www.gnu.org/licenses/>.
# Load support procs.
load_lib gcc-dg.exp
+# Return 1 if this is a compiler supporting ARCv2 EM as default processor
+proc check_effective_target_arcem { } {
+ return [check_no_compiler_messages arcem assembly {
+ #if !defined(__ARCEM__)
+ #error No ARC EM
+ #endif
+ }]
+}
+
+# Return 1 if we compile for ARC700
+proc check_effective_target_arc700 { } {
+ return [check_no_compiler_messages arc700 assembly {
+ #if !defined(__ARC700__)
+ #error No ARC 700
+ #endif
+ }]
+}
+
+# Return 1 if we compile for ARC6xx
+proc check_effective_target_arc6xx { } {
+ return [check_no_compiler_messages arc6xx assembly {
+ #if !defined(__ARC600__) && !defined(__ARC601__)
+ #error No ARC 6xx
+ #endif
+ }]
+}
+
+# Return 1 if we have mpy
+proc check_effective_target_arcmpy { } {
+ return [check_no_compiler_messages arcmpy assembly {
+ #if !defined(__ARC_MPY__)
+ #error No MPY
+ #endif
+ }]
+}
+
+# Return 1 if this is a compiler supporting ARC HS as default processor
+proc check_effective_target_archs { } {
+ return [check_no_compiler_messages archs assembly {
+ #if !defined(__ARCHS__)
+ #error No ARC HS
+ #endif
+ }]
+}
+
+proc check_cl { flags } {
+ return [check_no_compiler_messages check_$flags assembly {
+ #if !defined(__arc__)
+ #error Extra mcpu options
+ #endif
+ } "$flags"]
+}
+
+# Return 1 if there are no extra mcpu options given via command line
+proc check_effective_target_clmcpu { } {
+ if { [check_cl "-mcpu=arc700"]
+ && [check_cl "-mcpu=arcem" ] } {
+ return 1
+ }
+ return 0
+}
+
+proc check_effective_target_barrelshifter { } {
+ return [check_no_compiler_messages barrelshifter assembly {
+ #if !defined(__ARC_BARREL_SHIFTER__)
+ #error No barrel shifter for this confi
+ #endif
+ }]
+}
+
# If a testcase doesn't have special options, use these.
global DEFAULT_CFLAGS
if ![info exists DEFAULT_CFLAGS] then {
/* { dg-do compile } */
-/* { dg-options "-O2 -mcpu=ARC601 -mbarrel-shifter" } */
+/* { dg-options "-O2 -mbarrel-shifter" } */
int i;
int f (void)
/* { dg-do compile } */
+/* { dg-skip-if "" { ! { barrelshifter } } } */
int i;
int f (void)
/* { dg-do compile } */
+/* { dg-skip-if "" { ! { clmcpu } } } */
/* { dg-options "-O2 -Werror-implicit-function-declaration -mARC700 -msimd" } */
#define STEST1(name, rettype, op1) \
/* { dg-do compile } */
+/* { dg-skip-if "" { ! { clmcpu } } } */
/* { dg-options "-mcpu=archs -O2 -Werror-implicit-function-declaration -mmpy-option=9" } */
#define STEST(name, rettype, op1type, op2type) \
/* { dg-do compile } */
+/* { dg-skip-if "" { ! { clmcpu } } } */
/* { dg-options "-mcpu=nps400 -mcmem" } */
#define CMEM_SECTION_ATTR __attribute__ ((section (".cmem")));
/* { dg-do compile } */
+/* { dg-skip-if "" { ! { clmcpu } } } */
/* { dg-options "-mcpu=nps400 -mcmem" } */
#define CMEM_SECTION_ATTR __attribute__ ((section (".cmem")));
/* { dg-do compile } */
+/* { dg-skip-if "" { ! { clmcpu } } } */
/* { dg-options "-mcpu=nps400 -mcmem" } */
#define CMEM_SECTION_ATTR __attribute__ ((section (".cmem_private")));
/* { dg-do compile } */
+/* { dg-skip-if "" { ! { clmcpu } } } */
/* { dg-options "-mcpu=nps400 -mcmem" } */
#define CMEM_SECTION_ATTR __attribute__ ((section (".cmem_private")));
/* { dg-do compile } */
+/* { dg-skip-if "" { ! { clmcpu } } } */
/* { dg-options "-mcpu=nps400 -mcmem" } */
#define CMEM_SECTION_ATTR __attribute__ ((section (".cmem_shared")));
/* { dg-do compile } */
+/* { dg-skip-if "" { ! { clmcpu } } } */
/* { dg-options "-mcpu=nps400 -mcmem" } */
#define CMEM_SECTION_ATTR __attribute__ ((section (".cmem_shared")));
/* { dg-do compile } */
+/* { dg-skip-if "" { ! { clmcpu } } } */
/* { dg-options "-mcpu=nps400 -mcmem" } */
struct some_struct
/* { dg-do compile } */
+/* { dg-skip-if "" { ! { clmcpu } } } */
/* { dg-options "-mcpu=nps400 -O2 -mbitops" } */
struct foo { unsigned a: 3, b: 5, c: 24; };
/* { dg-do compile } */
+/* { dg-skip-if "" { ! { clmcpu } } } */
/* { dg-options "-mcpu=nps400 -O2 -mbitops" } */
/* ??? Irrespective of insn set, generated code for this is a mess. */
/* { dg-do compile } */
+/* { dg-skip-if "" { ! { clmcpu } } } */
/* { dg-options "-mcpu=nps400 -O2 -mbitops" } */
struct foo { unsigned a: 3, b: 8, c: 21; } bar;
+#if defined (__ARCHS__) || defined (__ARCEM__)
+void __attribute__ ((interrupt("ilink")))
+#else
void __attribute__ ((interrupt("ilink1")))
+#endif
handler1 (void)
{
}
-/* { dg-final { scan-assembler-times "j.*\[ilink1\]" 1 } } */
+/* { dg-final { scan-assembler-times "j.*\[ilink1\]" 1 { target { arc700 || arc6xx } } } } */
+/* { dg-final { scan-assembler-times "rtie" 1 { target { arcem || archs } } } } */
+/* { dg-skip-if "ilink2 is not an ARCv2 register" { archs || arcem } } */
void __attribute__ ((interrupt("ilink2")))
handler1 (void)
{
void __attribute__ ((interrupt("you load too")))
handler1 (void)
-{ /* { dg-warning "is not \"ilink1\" or \"ilink2\"" } */
+{ /* { dg-warning "is not \"ilink" } */
}
void __attribute__ ((interrupt(42)))
/* { dg-do compile } */
-/* { dg-options "-Os -mlock -mswape -mrtsc -fno-reorder-blocks" } */
+/* { dg-options "-Os -mlock -mswape -fno-reorder-blocks" } */
/* This caused an ICE in arc_ifcvt when the 1->3 state change was not
implemented for TYPE_UNCOND_BRANCH in arc_ccfsm_post_advance. */
/* { dg-do compile } */
+/* { dg-skip-if "" { ! { clmcpu } } } */
/* { dg-options "-mA6" } */
/* { dg-final { scan-assembler ".cpu ARC600" } } */
/* { dg-do compile } */
+/* { dg-skip-if "" { ! { clmcpu } } } */
/* { dg-options "-mA7" } */
/* { dg-final { scan-assembler ".cpu ARC700" } } */
/* { dg-do compile } */
+/* { dg-skip-if "" { ! { clmcpu } } } */
/* { dg-options "-mARC600" } */
/* { dg-final { scan-assembler ".cpu ARC600" } } */
/* { dg-do compile } */
+/* { dg-skip-if "" { ! { clmcpu } } } */
/* { dg-options "-mARC601" } */
-/* { dg-final { scan-assembler ".cpu ARC601" } } */
+/* { dg-final { scan-assembler ".cpu ARC60.*" } } */
/* { dg-do compile } */
+/* { dg-skip-if "" { ! { clmcpu } } } */
/* { dg-options "-mARC700" } */
/* { dg-final { scan-assembler ".cpu ARC700" } } */
/* { dg-do compile } */
-/* { dg-options "-mcpu=ARC600" } */
+/* { dg-skip-if "" { ! { clmcpu } } } */
+/* { dg-options "-mcpu=arc600" } */
/* { dg-final { scan-assembler ".cpu ARC600" } } */
/* { dg-do compile } */
-/* { dg-options "-mcpu=ARC601" } */
+/* { dg-skip-if "" { ! { clmcpu } } } */
+/* { dg-options "-mcpu=arc601" } */
-/* { dg-final { scan-assembler ".cpu ARC601" } } */
+/* { dg-final { scan-assembler ".cpu ARC60.*" } } */
/* { dg-do compile } */
-/* { dg-options "-mcpu=ARC700" } */
+/* { dg-skip-if "" { ! { clmcpu } } } */
+/* { dg-options "-mcpu=arc700" } */
/* { dg-final { scan-assembler ".cpu ARC700" } } */
+++ /dev/null
-/* { dg-options "-mcrc" } */
-/* { dg-do assemble } */
-
-int f (int i)
-{
- __asm__("crc %1, %1, %1" : "=r"(i) : "r"(i));
- return i;
-}
/* { dg-do compile } */
+/* { dg-skip-if "FPX cannot execute on ARC HS" { archs } } */
/* { dg-options "-O2 -mdpfp" } */
double i;
+++ /dev/null
-/* { dg-do compile } */
-/* { dg-options "-mdsp-packa" } */
-/* { dg-do assemble } */
-
-int f (int i)
-{
- __asm__("minidl %1, %1, %1" : "=r"(i) : "r"(i));
- return i;
-}
+++ /dev/null
-/* { dg-do compile } */
-/* { dg-options "-mdvbf" } */
-/* { dg-do assemble } */
-
-int f (int i)
-{
- __asm__("vbfdw %1, %1" : "=r"(i) : "r"(i));
- return i;
-}
/* { dg-options "-mlock" } */
/* { dg-do assemble } */
+/* { dg-skip-if "" { arc6xx } } */
int f (void *p)
{
+++ /dev/null
-/* { dg-options "-mmac-24" } */
-/* { dg-do assemble } */
-
-int f (int i)
-{
- __asm__("mult %1, %1, %1" : "=r"(i) : "r"(i));
- return i;
-}
+++ /dev/null
-/* { dg-do compile } */
-/* { dg-options "-mmac-d16" } */
-/* { dg-do assemble } */
-
-int f (int i)
-{
- __asm__("muldw %1, %1, %1" : "=r"(i) : "r"(i));
- return i;
-}
+++ /dev/null
-/* { dg-do compile } */
-/* { dg-options "-mno-crc" } */
-/* Would also like to assemble and check that we get the expected
- "Error: bad instruction" assembler messages, but at the moment our
- testharness can't do that. */
-
-int f (int i)
-{
- __asm__("crc %1, %1, %1" : "=r"(i) : "r"(i));
- return i;
-}
+++ /dev/null
-/* { dg-do compile } */
-/* { dg-options "-mno-dsp-packa" } */
-/* Would also like to assemble and check that we get the expected
- "Error: bad instruction" assembler messages, but at the moment our
- testharness can't do that. */
-
-int f (int i)
-{
- __asm__("minidl %1, %1, %1" : "=r"(i) : "r"(i));
- return i;
-}
+++ /dev/null
-/* { dg-do compile } */
-/* { dg-options "-mno-dvbf" } */
-/* Would also like to assemble and check that we get the expected
- "Error: bad instruction" assembler messages, but at the moment our
- testharness can't do that. */
-
-int f (int i)
-{
- __asm__("vbfdw %1, %1" : "=r"(i) : "r"(i));
- return i;
-}
+++ /dev/null
-/* { dg-do compile } */
-/* { dg-options "-mno-mac-24" } */
-/* Would also like to assemble and check that we get the expected
- "Error: bad instruction" assembler messages, but at the moment our
- testharness can't do that. */
-
-int f (int i)
-{
- __asm__("mult %1, %1, %1" : "=r"(i) : "r"(i));
- return i;
-}
+++ /dev/null
-/* { dg-do compile } */
-/* { dg-options "-mno-mac-d16" } */
-/* Would also like to assemble and check that we get the expected
- "Error: bad instruction" assembler messages, but at the moment our
- testharness can't do that. */
-
-int f (int i)
-{
- __asm__("muldw %1, %1, %1" : "=r"(i) : "r"(i));
- return i;
-}
+++ /dev/null
-/* { dg-do compile } */
-/* { dg-options "-mno-rtsc" } */
-/* Would also like to assemble and check that we get the expected
- "Error: bad instruction" assembler messages, but at the moment our
- testharness can't do that. */
-
-int f (int i)
-{
- __asm__("rtsc %1, %1" : "=r"(i) : "r"(i));
- return i;
-}
+++ /dev/null
-/* { dg-do compile } */
-/* { dg-options "-mno-xy" } */
-/* Would also like to assemble and check that we get the expected
- "Error: bad instruction" assembler messages, but at the moment our
- testharness can't do that. */
-
-void f (int i)
-{
- __asm__("add x0_u0, x0_u0, %0" : : "r" (i));
-}
/* { dg-do compile } */
+/* { dg-skip-if "" { ! { clmcpu } } } */
/* { dg-options "-mcpu=nps400 -O2 -mbitops" } */
struct { unsigned a: 5, b: 8, c: 19; } foo;
/* { dg-do compile } */
+/* { dg-skip-if "" { ! { clmcpu } } } */
/* { dg-options "-mcpu=nps400 -O2 -mbitops" } */
struct { unsigned a: 23, b: 9; } foo;
/* { dg-do compile } */
+/* { dg-skip-if "" { ! { clmcpu } } } */
/* { dg-options "-mcpu=nps400 -O2 -mbitops" } */
struct { int a: 23, b: 9; } foo;
/* { dg-do compile } */
+/* { dg-skip-if "" { ! { clmcpu } } } */
/* { dg-options "-mcpu=nps400 -O2 -mbitops" } */
struct { int a: 13, b: 19; } foo;
/* { dg-do compile } */
+/* { dg-skip-if "" { ! { clmcpu } } } */
/* { dg-options "-mcpu=nps400 -O2 -mbitops" } */
struct { int a: 23, b: 9; } foo;
/* { dg-do compile } */
+/* { dg-skip-if "" { ! { clmcpu } } } */
/* { dg-options "-mcpu=nps400 -O2 -mbitops" } */
int
/* { dg-do compile } */
+/* { dg-skip-if "" { ! { clmcpu } } } */
/* { dg-options "-mcpu=nps400 -O2 -mbitops" } */
extern void g (void);
/* { dg-do compile } */
+/* { dg-skip-if "" { ! { clmcpu } } } */
/* { dg-options "-mcpu=nps400 -O2 -mbitops" } */
int
/* { dg-do compile } */
+/* { dg-skip-if "" { ! { clmcpu } } } */
/* { dg-options "-mcpu=nps400 -O2 -mbitops" } */
struct thing
/* { dg-do compile } */
+/* { dg-skip-if "" { ! { clmcpu } } } */
/* { dg-options "-mcpu=nps400 -O2 -mbitops" } */
int
+++ /dev/null
-/* { dg-options "-mrtsc" } */
-/* { dg-do assemble } */
-
-int f (int i)
-{
- __asm__("rtsc %1, %1" : "=r"(i) : "r"(i));
- return i;
-}
/* { dg-do compile } */
+/* { dg-skip-if "FPX is not an ARC HS extension" { archs } } */
/* { dg-options "-O2 -mspfp" } */
float i;
/* { dg-options "-mswape" } */
/* { dg-do assemble } */
+/* { dg-skip-if "" { arc6xx } } */
int f (int i)
{
/* { dg-do compile } */
-/* { dg-options "-O2 -mcpu=ARC600 -mmul64" } */
+/* { dg-skip-if "MUL64 is ARC600 extension" { ! { arc6xx } } } */
+/* { dg-options "-O2 -mmul64" } */
+
#include <stdint.h>
int64_t i;
/* { dg-do run } */
-/* { dg-options "-O2 -mARC700 --save-temps" } */
+/* { dg-options "-save-temps -O2" } */
#include <stdlib.h>
return 0;
}
-/* { dg-final { scan-assembler "mpyhu\[ \t\]" } } */
+/* { dg-final { scan-assembler "mpyhu\[ \t\]" { target { arc700 } } } } */
+/* { dg-final { scan-assembler "mpy.u\[ \t\]" { target { { ! { arc700 } } && arcmpy } } } } */
/* { dg-do run } */
-/* { dg-options "-O2 -mARC700 --save-temps -mno-mpy" } */
+/* { dg-skip-if "ARC700 always has mpy option on" { arc700 } } */
+/* { dg-skip-if "ARC600 doesn't have mpy instruction" { arc6xx } } */
+/* { dg-options "-O2 --save-temps -mmpy-option=0" } */
#include <stdlib.h>
/* { dg-do compile } */
+/* { dg-skip-if "FPX cannot execute on ARC HS" { archs } } */
/* { dg-options "-O2 -mdpfp -mno-dpfp-lrsr" } */
double i;
/* { dg-do compile } */
+/* { dg-skip-if "" { ! { clmcpu } } } */
/* { dg-options "-mcpu=nps400 -mq-class -mbitops -munaligned-access -mcmem -O2 -fno-strict-aliasing" } */
enum npsdp_mem_space_type {
/* Tests if we generate rsub instructions when compiling using
floating point assist instructions. */
/* { dg-do compile } */
+/* { dg-skip-if "" { ! { clmcpu } } } */
/* { dg-options "-mfpu=fpuda -mcpu=arcem" } */
double foo (double a)
--- /dev/null
+/* { dg-do run } */
+/* { dg-options "-O2" } */
+/* { dg-additional-sources "abitest.S" } */
+
+extern long tsyscall (long int sysnum, ...);
+
+int main (void)
+{
+ long a;
+
+ a = tsyscall (1, 2, 3, 4, 5, 6, 7);
+
+ if (a != 28)
+ return 1;
+ return 0;
+}
--- /dev/null
+/* { dg-do run } */
+/* { dg-options "-O2" } */
+/* { dg-additional-sources "abitest.S" } */
+
+extern int clone(int (*fn)(void *), void *child_stack,
+ int flags, void *arg, ...);
+
+int main (void)
+{
+ int a = clone ((void *) 1, (void *)2, 3, (void *) 4, 5, 6, 7);
+ if (a != 28)
+ return 1;
+ return 0;
+}
--- /dev/null
+/* { dg-do run } */
+/* { dg-options "-O2" } */
+/* { dg-additional-sources "abitest.S" } */
+
+extern long long abidi (int a, ...);
+
+int main (void)
+{
+ long long a = 1;
+ a = abidi (10, a);
+
+ if (a != 2)
+ return 1;
+ return 0;
+}
projects / gcc.git / commitdiff