Use WRITE_RD/WRITE_FRD macros to write registers

diff --git a/riscv/decode.h b/riscv/decode.h
index 3d20b62735e175991207a594d18674a7a8a31315..bde921f08db4a03b14c63ff8c5d4e4110603765f 100644 (file)
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -69,22 +69,6 @@ private:
   reg_t imm_sign() { return int64_t(int32_t(b) >> 31); }
 };
 
-template <class T>
-class write_port_t
-{
-public:
-  write_port_t(T& _t) : t(_t) {}
-  T& operator = (const T& rhs)
-  {
-    return t = rhs;
-  }
-  operator T()
-  {
-    return t;
-  }
-private:
-  T& t;
-};
 template <class T, size_t N, bool zero_reg>
 class regfile_t
 {
@@ -93,11 +77,9 @@ public:
   {
     memset(data, 0, sizeof(data));
   }
-  write_port_t<T> write_port(size_t i)
+  void write(size_t i, T value)
   {
-    if (zero_reg)
-      const_cast<T&>(data[0]) = 0;
-    return write_port_t<T>(data[i]);
+    data[i] = value;
   }
   const T& operator [] (size_t i) const
   {
@@ -113,11 +95,11 @@ private:
 #define MMU (*p->get_mmu())
 #define RS1 p->get_state()->XPR[insn.rs1()]
 #define RS2 p->get_state()->XPR[insn.rs2()]
-#define RD p->get_state()->XPR.write_port(insn.rd())
+#define WRITE_RD(value) p->get_state()->XPR.write(insn.rd(), value)
 #define FRS1 p->get_state()->FPR[insn.rs1()]
 #define FRS2 p->get_state()->FPR[insn.rs2()]
 #define FRS3 p->get_state()->FPR[insn.rs3()]
-#define FRD p->get_state()->FPR.write_port(insn.rd())
+#define WRITE_FRD(value) p->get_state()->FPR.write(insn.rd(), value)
 #define SHAMT (insn.i_imm() & 0x3F)
 #define BRANCH_TARGET (pc + insn.sb_imm())
 #define JUMP_TARGET (pc + insn.uj_imm())

diff --git a/riscv/insns/add.h b/riscv/insns/add.h
index 34d49ff31b932d4f48904e08336e2745ea8560e5..d7a5c98d21867debe16657aad778d6b1be191c7e 100644 (file)
--- a/riscv/insns/add.h
+++ b/riscv/insns/add.h
@@ -1 +1 @@
-RD = sext_xprlen(RS1 + RS2);
+WRITE_RD(sext_xprlen(RS1 + RS2));

diff --git a/riscv/insns/addi.h b/riscv/insns/addi.h
index d6994bac679ad82c6af6fc0d375f4c0ba33907f5..c861a97c80ba3a81871f9ef3893d10bf7c387e85 100644 (file)
--- a/riscv/insns/addi.h
+++ b/riscv/insns/addi.h
@@ -1 +1 @@
-RD = sext_xprlen(RS1 + insn.i_imm());
+WRITE_RD(sext_xprlen(RS1 + insn.i_imm()));

diff --git a/riscv/insns/addiw.h b/riscv/insns/addiw.h
index a0608ed989946e3e48fd60954c4e9355e01b84fa..71ab2923e7b5015a8aec2741c8516d5cf1c13652 100644 (file)
--- a/riscv/insns/addiw.h
+++ b/riscv/insns/addiw.h
@@ -1,2 +1,2 @@
 require_xpr64;
-RD = sext32(insn.i_imm() + RS1);
+WRITE_RD(sext32(insn.i_imm() + RS1));

diff --git a/riscv/insns/addw.h b/riscv/insns/addw.h
index 4e2ed561677827fb72ffe7753d2d16823b88f017..f2d98d94c75ee89d26d249d29d88a3701efdbd96 100644 (file)
--- a/riscv/insns/addw.h
+++ b/riscv/insns/addw.h
@@ -1,2 +1,2 @@
 require_xpr64;
-RD = sext32(RS1 + RS2);
+WRITE_RD(sext32(RS1 + RS2));

diff --git a/riscv/insns/amoadd_d.h b/riscv/insns/amoadd_d.h
index bba975ce1fbccaf7357f02b71244bc8512dcc91a..532902ea94a2a2121ffc85e1fc23854cb3f8722f 100644 (file)
--- a/riscv/insns/amoadd_d.h
+++ b/riscv/insns/amoadd_d.h
@@ -1,4 +1,4 @@
 require_xpr64;
 reg_t v = MMU.load_uint64(RS1);
 MMU.store_uint64(RS1, RS2 + v);
-RD = v;
+WRITE_RD(v);

diff --git a/riscv/insns/amoadd_w.h b/riscv/insns/amoadd_w.h
index 07c9c9a9e9591a7c0c0f6aacdade8b8beaefa358..8eb9e2b020186d78a375a70c0c85fed2a68d769e 100644 (file)
--- a/riscv/insns/amoadd_w.h
+++ b/riscv/insns/amoadd_w.h
@@ -1,3 +1,3 @@
 reg_t v = MMU.load_int32(RS1);
 MMU.store_uint32(RS1, RS2 + v);
-RD = v;
+WRITE_RD(v);

diff --git a/riscv/insns/amoand_d.h b/riscv/insns/amoand_d.h
index 1bb34029d3258cc9539dcb724f0478944e5ffeca..8a672ba56f52cf1770a378f1415989cf4b872102 100644 (file)
--- a/riscv/insns/amoand_d.h
+++ b/riscv/insns/amoand_d.h
@@ -1,4 +1,4 @@
 require_xpr64;
 reg_t v = MMU.load_uint64(RS1);
 MMU.store_uint64(RS1, RS2 & v);
-RD = v;
+WRITE_RD(v);

diff --git a/riscv/insns/amoand_w.h b/riscv/insns/amoand_w.h
index 91866dcfef7d3f46ba994c5265063c8bd279f369..32ea7f70fa9a643c598e663898b655c8269011cd 100644 (file)
--- a/riscv/insns/amoand_w.h
+++ b/riscv/insns/amoand_w.h
@@ -1,3 +1,3 @@
 reg_t v = MMU.load_int32(RS1);
 MMU.store_uint32(RS1, RS2 & v);
-RD = v;
+WRITE_RD(v);

diff --git a/riscv/insns/amomax_d.h b/riscv/insns/amomax_d.h
index dfd2b336b02b528528242b822e6884ddb20a07c7..7b97e7b073e5e4296a3317d710b5c39128fed632 100644 (file)
--- a/riscv/insns/amomax_d.h
+++ b/riscv/insns/amomax_d.h
@@ -1,4 +1,4 @@
 require_xpr64;
 sreg_t v = MMU.load_int64(RS1);
 MMU.store_uint64(RS1, std::max(sreg_t(RS2),v));
-RD = v;
+WRITE_RD(v);

diff --git a/riscv/insns/amomax_w.h b/riscv/insns/amomax_w.h
index 1f68a8bf78c7615b61c300027ff98d99a2fe96ef..a2551161bce4e60c6f3df915e3eb06e1cf1c8b42 100644 (file)
--- a/riscv/insns/amomax_w.h
+++ b/riscv/insns/amomax_w.h
@@ -1,3 +1,3 @@
 int32_t v = MMU.load_int32(RS1);
 MMU.store_uint32(RS1, std::max(int32_t(RS2),v));
-RD = v;
+WRITE_RD(v);

diff --git a/riscv/insns/amomaxu_d.h b/riscv/insns/amomaxu_d.h
index 8d50a0aa3031a87fbecc003c42e1a80d10f91f15..ef003c6e16f0f075b18dc245a92cf236d084a720 100644 (file)
--- a/riscv/insns/amomaxu_d.h
+++ b/riscv/insns/amomaxu_d.h
@@ -1,4 +1,4 @@
 require_xpr64;
 reg_t v = MMU.load_uint64(RS1);
 MMU.store_uint64(RS1, std::max(RS2,v));
-RD = v;
+WRITE_RD(v);

diff --git a/riscv/insns/amomaxu_w.h b/riscv/insns/amomaxu_w.h
index d507e4f87167a30eb2121ab97fd0dee3f31656f7..448814bb3b8f084bf12cbde8a1147ddfacda9a58 100644 (file)
--- a/riscv/insns/amomaxu_w.h
+++ b/riscv/insns/amomaxu_w.h
@@ -1,3 +1,3 @@
 uint32_t v = MMU.load_int32(RS1);
 MMU.store_uint32(RS1, std::max(uint32_t(RS2),v));
-RD = (int32_t)v;
+WRITE_RD((int32_t)v);

diff --git a/riscv/insns/amomin_d.h b/riscv/insns/amomin_d.h
index a20ace885c34fbf87cb2b2ba80536f0b6017b6f5..62915bb0df945b7c9cd42a8ba144b348b319201f 100644 (file)
--- a/riscv/insns/amomin_d.h
+++ b/riscv/insns/amomin_d.h
@@ -1,4 +1,4 @@
 require_xpr64;
 sreg_t v = MMU.load_int64(RS1);
 MMU.store_uint64(RS1, std::min(sreg_t(RS2),v));
-RD = v;
+WRITE_RD(v);

diff --git a/riscv/insns/amomin_w.h b/riscv/insns/amomin_w.h
index d8f95af6627c4e83d316179bde716a76866e7b3c..28efa15e42f9bdea91a744fba8b85c96322b623d 100644 (file)
--- a/riscv/insns/amomin_w.h
+++ b/riscv/insns/amomin_w.h
@@ -1,3 +1,3 @@
 int32_t v = MMU.load_int32(RS1);
 MMU.store_uint32(RS1, std::min(int32_t(RS2),v));
-RD = v;
+WRITE_RD(v);

diff --git a/riscv/insns/amominu_d.h b/riscv/insns/amominu_d.h
index 4f83c0f59ab878f641af434da86a654ccdfd820b..5543d5ed14b0245594190ed6597559e1c211e09a 100644 (file)
--- a/riscv/insns/amominu_d.h
+++ b/riscv/insns/amominu_d.h
@@ -1,4 +1,4 @@
 require_xpr64;
 reg_t v = MMU.load_uint64(RS1);
 MMU.store_uint64(RS1, std::min(RS2,v));
-RD = v;
+WRITE_RD(v);

diff --git a/riscv/insns/amominu_w.h b/riscv/insns/amominu_w.h
index a3a537a94f98844993daad8fea39aebcdfe498b3..459b20161ccb5f47c915a7bad5f669b37751b7f7 100644 (file)
--- a/riscv/insns/amominu_w.h
+++ b/riscv/insns/amominu_w.h
@@ -1,3 +1,3 @@
 uint32_t v = MMU.load_int32(RS1);
 MMU.store_uint32(RS1, std::min(uint32_t(RS2),v));
-RD = (int32_t)v;
+WRITE_RD((int32_t)v);

diff --git a/riscv/insns/amoor_d.h b/riscv/insns/amoor_d.h
index 87b6f2a6f6b2616026393a4f06802e6eb66330c0..500803f6876d590bbb7a2150a9e6f681464f9d96 100644 (file)
--- a/riscv/insns/amoor_d.h
+++ b/riscv/insns/amoor_d.h
@@ -1,4 +1,4 @@
 require_xpr64;
 reg_t v = MMU.load_uint64(RS1);
 MMU.store_uint64(RS1, RS2 | v);
-RD = v;
+WRITE_RD(v);

diff --git a/riscv/insns/amoor_w.h b/riscv/insns/amoor_w.h
index 0733fad203d4b9382f8fad58b759dbd418796fa9..c178f9af1cc8e8f61bd4a638efbb2118dc9d7227 100644 (file)
--- a/riscv/insns/amoor_w.h
+++ b/riscv/insns/amoor_w.h
@@ -1,3 +1,3 @@
 reg_t v = MMU.load_int32(RS1);
 MMU.store_uint32(RS1, RS2 | v);
-RD = v;
+WRITE_RD(v);

diff --git a/riscv/insns/amoswap_d.h b/riscv/insns/amoswap_d.h
index 3423b91de2dab5464aad40dc6c0dbc6b17df7253..f03d2aabba95716c3d2bbde10d1a39dc3741e9ef 100644 (file)
--- a/riscv/insns/amoswap_d.h
+++ b/riscv/insns/amoswap_d.h
@@ -1,4 +1,4 @@
 require_xpr64;
 reg_t v = MMU.load_uint64(RS1);
 MMU.store_uint64(RS1, RS2);
-RD = v;
+WRITE_RD(v);

diff --git a/riscv/insns/amoswap_w.h b/riscv/insns/amoswap_w.h
index b888235c494173a3e92a552e2f2ef3477e339568..148b5bcac1b0924d125f6ba93771ea788f3604eb 100644 (file)
--- a/riscv/insns/amoswap_w.h
+++ b/riscv/insns/amoswap_w.h
@@ -1,3 +1,3 @@
 reg_t v = MMU.load_int32(RS1);
 MMU.store_uint32(RS1, RS2);
-RD = v;
+WRITE_RD(v);

diff --git a/riscv/insns/amoxor_d.h b/riscv/insns/amoxor_d.h
index 25d4fcb580a6197cbfd769a0aeea0e3cf6dc666f..c78e7e3939a1a169ee138e5e81f0800b820e0039 100644 (file)
--- a/riscv/insns/amoxor_d.h
+++ b/riscv/insns/amoxor_d.h
@@ -1,4 +1,4 @@
 require_xpr64;
 reg_t v = MMU.load_uint64(RS1);
 MMU.store_uint64(RS1, RS2 ^ v);
-RD = v;
+WRITE_RD(v);

diff --git a/riscv/insns/amoxor_w.h b/riscv/insns/amoxor_w.h
index f59a43e59f71d1ab8302b38224074134fe1e77c4..3a87b6e4550f559455b90a5d0985461466cbb84f 100644 (file)
--- a/riscv/insns/amoxor_w.h
+++ b/riscv/insns/amoxor_w.h
@@ -1,3 +1,3 @@
 reg_t v = MMU.load_int32(RS1);
 MMU.store_uint32(RS1, RS2 ^ v);
-RD = v;
+WRITE_RD(v);

diff --git a/riscv/insns/and.h b/riscv/insns/and.h
index 88ac1d8738b7fc2b335d3b27e9b4472a92ee4126..86b488314ff8ad737a232cd319dcd511e10935f9 100644 (file)
--- a/riscv/insns/and.h
+++ b/riscv/insns/and.h
@@ -1 +1 @@
-RD = RS1 & RS2;
+WRITE_RD(RS1 & RS2);

diff --git a/riscv/insns/andi.h b/riscv/insns/andi.h
index 713692ea925f77f389c7a1e1b397174cc40becb1..bcc51e44071ab6bdff0ac53fd81bf3d1acf0764d 100644 (file)
--- a/riscv/insns/andi.h
+++ b/riscv/insns/andi.h
@@ -1 +1 @@
-RD = insn.i_imm() & RS1;
+WRITE_RD(insn.i_imm() & RS1);

diff --git a/riscv/insns/auipc.h b/riscv/insns/auipc.h
index b58a0c924e1f9392c0f51a6716e6ac0dcab1b748..4d91bfc39c4bd1968facce5d310fedb4b799a54a 100644 (file)
--- a/riscv/insns/auipc.h
+++ b/riscv/insns/auipc.h
@@ -1 +1 @@
-RD = sext_xprlen(insn.u_imm() + (pc >> 12 << 12));
+WRITE_RD(sext_xprlen(insn.u_imm() + (pc >> 12 << 12)));

diff --git a/riscv/insns/clearpcr.h b/riscv/insns/clearpcr.h
index 33e0c318ee23beee7525d8049c1a946036e2294b..ac646872a0d942d06c144463ba92737ae1883f94 100644 (file)
--- a/riscv/insns/clearpcr.h
+++ b/riscv/insns/clearpcr.h
@@ -1,2 +1,2 @@
 require_supervisor;
-RD = p->set_pcr(insn.rs1(), p->get_pcr(insn.rs1()) & ~insn.i_imm());
+WRITE_RD(p->set_pcr(insn.rs1(), p->get_pcr(insn.rs1()) & ~insn.i_imm()));

diff --git a/riscv/insns/div.h b/riscv/insns/div.h
index 8412f6120a810792976f8cc97df34592ffd2a9ff..261880fe3761b725fdf4d642c3cccfab2c46b3d4 100644 (file)
--- a/riscv/insns/div.h
+++ b/riscv/insns/div.h
@@ -1,8 +1,8 @@
 sreg_t lhs = sext_xprlen(RS1);
 sreg_t rhs = sext_xprlen(RS2);
 if(rhs == 0)
-  RD = UINT64_MAX;
+  WRITE_RD(UINT64_MAX);
 else if(lhs == INT64_MIN && rhs == -1)
-  RD = lhs;
+  WRITE_RD(lhs);
 else
-  RD = sext_xprlen(lhs / rhs);
+  WRITE_RD(sext_xprlen(lhs / rhs));

diff --git a/riscv/insns/divu.h b/riscv/insns/divu.h
index 4346349d3a45254e51c81c10b51d2c66903d2162..fd878a2f3e8a50bef036289924d0f5ddc7ceea7f 100644 (file)
--- a/riscv/insns/divu.h
+++ b/riscv/insns/divu.h
@@ -1,6 +1,6 @@
 reg_t lhs = zext_xprlen(RS1);
 reg_t rhs = zext_xprlen(RS2);
 if(rhs == 0)
-  RD = UINT64_MAX;
+  WRITE_RD(UINT64_MAX);
 else
-  RD = sext_xprlen(lhs / rhs);
+  WRITE_RD(sext_xprlen(lhs / rhs));

diff --git a/riscv/insns/divuw.h b/riscv/insns/divuw.h
index 7f6e32115c9d7bcd7ef1b98b93cdbbed302406e0..a7176580ba5c90909f812bd15cbd5735a23f081e 100644 (file)
--- a/riscv/insns/divuw.h
+++ b/riscv/insns/divuw.h
@@ -2,6 +2,6 @@ require_xpr64;
 reg_t lhs = zext32(RS1);
 reg_t rhs = zext32(RS2);
 if(rhs == 0)
-  RD = UINT64_MAX;
+  WRITE_RD(UINT64_MAX);
 else
-  RD = sext32(lhs / rhs);
+  WRITE_RD(sext32(lhs / rhs));

diff --git a/riscv/insns/divw.h b/riscv/insns/divw.h
index b51d9b7cbc100e2d443de550b47664d6fe8a6d83..24f22fdbebf191badc79f77af853414dd7f2e3bf 100644 (file)
--- a/riscv/insns/divw.h
+++ b/riscv/insns/divw.h
@@ -2,6 +2,6 @@ require_xpr64;
 sreg_t lhs = sext32(RS1);
 sreg_t rhs = sext32(RS2);
 if(rhs == 0)
-  RD = UINT64_MAX;
+  WRITE_RD(UINT64_MAX);
 else
-  RD = sext32(lhs / rhs);
+  WRITE_RD(sext32(lhs / rhs));

diff --git a/riscv/insns/fadd_d.h b/riscv/insns/fadd_d.h
index dcc6413528851a1a21a777df63895d297055af74..e06efb85b868a19c04d75f96f9623c08d0a5e897 100644 (file)
--- a/riscv/insns/fadd_d.h
+++ b/riscv/insns/fadd_d.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f64_mulAdd(FRS1, 0x3ff0000000000000ULL, FRS2);
+WRITE_FRD(f64_mulAdd(FRS1, 0x3ff0000000000000ULL, FRS2));
 set_fp_exceptions;

diff --git a/riscv/insns/fadd_s.h b/riscv/insns/fadd_s.h
index 952d1a73d55dcb29b861c399a5d598bd40151005..c43135dec2459771da04798050886f8c81abb735 100644 (file)
--- a/riscv/insns/fadd_s.h
+++ b/riscv/insns/fadd_s.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f32_mulAdd(FRS1, 0x3f800000, FRS2);
+WRITE_FRD(f32_mulAdd(FRS1, 0x3f800000, FRS2));
 set_fp_exceptions;

diff --git a/riscv/insns/fcvt_d_l.h b/riscv/insns/fcvt_d_l.h
index 68c04827a3704c45deea1bb47e9fee49aca62661..eab849aceb51f4cb476dc79166195d5ace600c9d 100644 (file)
--- a/riscv/insns/fcvt_d_l.h
+++ b/riscv/insns/fcvt_d_l.h
@@ -1,5 +1,5 @@
 require_xpr64;
 require_fp;
 softfloat_roundingMode = RM;
-FRD = i64_to_f64(RS1);
+WRITE_FRD(i64_to_f64(RS1));
 set_fp_exceptions;

diff --git a/riscv/insns/fcvt_d_lu.h b/riscv/insns/fcvt_d_lu.h
index 203275863ff1253f44136f9b29115db7f1324393..bef89ebd3ec4c2f96d3f6fda2763ee05af2352b3 100644 (file)
--- a/riscv/insns/fcvt_d_lu.h
+++ b/riscv/insns/fcvt_d_lu.h
@@ -1,5 +1,5 @@
 require_xpr64;
 require_fp;
 softfloat_roundingMode = RM;
-FRD = ui64_to_f64(RS1);
+WRITE_FRD(ui64_to_f64(RS1));
 set_fp_exceptions;

diff --git a/riscv/insns/fcvt_d_s.h b/riscv/insns/fcvt_d_s.h
index 6b1a09cc5e604cbd31ff3bbc97631ca74fc334f1..0024330730e45a108db4fcd044c54a27e7ad86d1 100644 (file)
--- a/riscv/insns/fcvt_d_s.h
+++ b/riscv/insns/fcvt_d_s.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f32_to_f64(FRS1);
+WRITE_FRD(f32_to_f64(FRS1));
 set_fp_exceptions;

diff --git a/riscv/insns/fcvt_d_w.h b/riscv/insns/fcvt_d_w.h
index 52abd7597125b82d88418351fbd7b3cee3e0f737..ce56974aa7c0e1b6249c86d65c9a8631ef959345 100644 (file)
--- a/riscv/insns/fcvt_d_w.h
+++ b/riscv/insns/fcvt_d_w.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = i32_to_f64((int32_t)RS1);
+WRITE_FRD(i32_to_f64((int32_t)RS1));
 set_fp_exceptions;

diff --git a/riscv/insns/fcvt_d_wu.h b/riscv/insns/fcvt_d_wu.h
index 61a8a788a34d41e6aa79e943b35cb09f5dc89993..4c562481e200f869f06e6c5aeaf4848331f7ed0b 100644 (file)
--- a/riscv/insns/fcvt_d_wu.h
+++ b/riscv/insns/fcvt_d_wu.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = ui32_to_f64((uint32_t)RS1);
+WRITE_FRD(ui32_to_f64((uint32_t)RS1));
 set_fp_exceptions;

diff --git a/riscv/insns/fcvt_l_d.h b/riscv/insns/fcvt_l_d.h
index 206ba4fc4c4eebf75a67f8677531c76322cba1c6..bf03b714b1883671458919bf7252edd6c88a0739 100644 (file)
--- a/riscv/insns/fcvt_l_d.h
+++ b/riscv/insns/fcvt_l_d.h
@@ -1,5 +1,5 @@
 require_xpr64;
 require_fp;
 softfloat_roundingMode = RM;
-RD = f64_to_i64(FRS1, RM, true);
+WRITE_RD(f64_to_i64(FRS1, RM, true));
 set_fp_exceptions;

diff --git a/riscv/insns/fcvt_l_s.h b/riscv/insns/fcvt_l_s.h
index e05f4761c5e81573ea39ab332ac8ffacdae57fa0..1259234ec4a48c15d48c6eae578aa6358ace6441 100644 (file)
--- a/riscv/insns/fcvt_l_s.h
+++ b/riscv/insns/fcvt_l_s.h
@@ -1,5 +1,5 @@
 require_xpr64;
 require_fp;
 softfloat_roundingMode = RM;
-RD = f32_to_i64(FRS1, RM, true);
+WRITE_RD(f32_to_i64(FRS1, RM, true));
 set_fp_exceptions;

diff --git a/riscv/insns/fcvt_lu_d.h b/riscv/insns/fcvt_lu_d.h
index 44c3dd6ba426c12cefa03728d0c0f77d6329b0e2..d69b36b1e2e7f293b27c4a2686082c3ae289f9dd 100644 (file)
--- a/riscv/insns/fcvt_lu_d.h
+++ b/riscv/insns/fcvt_lu_d.h
@@ -1,5 +1,5 @@
 require_xpr64;
 require_fp;
 softfloat_roundingMode = RM;
-RD = f64_to_ui64(FRS1, RM, true);
+WRITE_RD(f64_to_ui64(FRS1, RM, true));
 set_fp_exceptions;

diff --git a/riscv/insns/fcvt_lu_s.h b/riscv/insns/fcvt_lu_s.h
index 13de43689ebbef7178e00249659507fada835046..e40605bd29c8b212c13ddff42b312a9f324eba7f 100644 (file)
--- a/riscv/insns/fcvt_lu_s.h
+++ b/riscv/insns/fcvt_lu_s.h
@@ -1,5 +1,5 @@
 require_xpr64;
 require_fp;
 softfloat_roundingMode = RM;
-RD = f32_to_ui64(FRS1, RM, true);
+WRITE_RD(f32_to_ui64(FRS1, RM, true));
 set_fp_exceptions;

diff --git a/riscv/insns/fcvt_s_d.h b/riscv/insns/fcvt_s_d.h
index e5289c4b0d1866f19744089b0d93b6ef9aef3c7a..28a1d6969df2092d300991f5e5bb6d6f42308ce8 100644 (file)
--- a/riscv/insns/fcvt_s_d.h
+++ b/riscv/insns/fcvt_s_d.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f64_to_f32(FRS1);
+WRITE_FRD(f64_to_f32(FRS1));
 set_fp_exceptions;

diff --git a/riscv/insns/fcvt_s_l.h b/riscv/insns/fcvt_s_l.h
index f149229d860a3078453fb1dedef65267ddd4ab00..98570ab94ca8cc47ce31a59e67c5fddf86bedb79 100644 (file)
--- a/riscv/insns/fcvt_s_l.h
+++ b/riscv/insns/fcvt_s_l.h
@@ -1,5 +1,5 @@
 require_xpr64;
 require_fp;
 softfloat_roundingMode = RM;
-FRD = i64_to_f32(RS1);
+WRITE_FRD(i64_to_f32(RS1));
 set_fp_exceptions;

diff --git a/riscv/insns/fcvt_s_lu.h b/riscv/insns/fcvt_s_lu.h
index d9d0946ac0bff976ccd2ddf05d50fe86b70fa5c5..921bfcfbb4ffb6c9698c1b066fb0ca65980bc721 100644 (file)
--- a/riscv/insns/fcvt_s_lu.h
+++ b/riscv/insns/fcvt_s_lu.h
@@ -1,5 +1,5 @@
 require_xpr64;
 require_fp;
 softfloat_roundingMode = RM;
-FRD = ui64_to_f32(RS1);
+WRITE_FRD(ui64_to_f32(RS1));
 set_fp_exceptions;

diff --git a/riscv/insns/fcvt_s_w.h b/riscv/insns/fcvt_s_w.h
index dedebb549b49cdbedf424e384ba4c3164d2bf672..05445fa27a7bb4aaee125eac7caafe9f7e06390d 100644 (file)
--- a/riscv/insns/fcvt_s_w.h
+++ b/riscv/insns/fcvt_s_w.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = i32_to_f32((int32_t)RS1);
+WRITE_FRD(i32_to_f32((int32_t)RS1));
 set_fp_exceptions;

diff --git a/riscv/insns/fcvt_s_wu.h b/riscv/insns/fcvt_s_wu.h
index abb782c38126d777928907cc3ba724215121ed49..ca8d2b603f5fcc60e698cd29cf35b2e923a005dc 100644 (file)
--- a/riscv/insns/fcvt_s_wu.h
+++ b/riscv/insns/fcvt_s_wu.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = ui32_to_f32((uint32_t)RS1);
+WRITE_FRD(ui32_to_f32((uint32_t)RS1));
 set_fp_exceptions;

diff --git a/riscv/insns/fcvt_w_d.h b/riscv/insns/fcvt_w_d.h
index 88dc3d33c53253ff9e00bc836efe2a73ea3e7407..a5186b5a57a16e7067565f7e58719e7bffe99966 100644 (file)
--- a/riscv/insns/fcvt_w_d.h
+++ b/riscv/insns/fcvt_w_d.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-RD = sext32(f64_to_i32(FRS1, RM, true));
+WRITE_RD(sext32(f64_to_i32(FRS1, RM, true)));
 set_fp_exceptions;

diff --git a/riscv/insns/fcvt_w_s.h b/riscv/insns/fcvt_w_s.h
index f14cc19a37798d4e2032cf69bc2b233b02c50c8c..1d82deb72727468fcfc150800f58d87a5f67cc7d 100644 (file)
--- a/riscv/insns/fcvt_w_s.h
+++ b/riscv/insns/fcvt_w_s.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-RD = sext32(f32_to_i32(FRS1, RM, true));
+WRITE_RD(sext32(f32_to_i32(FRS1, RM, true)));
 set_fp_exceptions;

diff --git a/riscv/insns/fcvt_wu_d.h b/riscv/insns/fcvt_wu_d.h
index 43ad6f63d30c497d5154b70af4c0f4c2a8717356..5cf44d153721eb525241c9253b4a616d5e897ff0 100644 (file)
--- a/riscv/insns/fcvt_wu_d.h
+++ b/riscv/insns/fcvt_wu_d.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-RD = sext32(f64_to_ui32(FRS1, RM, true));
+WRITE_RD(sext32(f64_to_ui32(FRS1, RM, true)));
 set_fp_exceptions;

diff --git a/riscv/insns/fcvt_wu_s.h b/riscv/insns/fcvt_wu_s.h
index ff7a11cf73062f48969529d581b8c42048b80039..5b4c4444bab2d0cceb8eebdbde5e1f8eb9124ec1 100644 (file)
--- a/riscv/insns/fcvt_wu_s.h
+++ b/riscv/insns/fcvt_wu_s.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-RD = sext32(f32_to_ui32(FRS1, RM, true));
+WRITE_RD(sext32(f32_to_ui32(FRS1, RM, true)));
 set_fp_exceptions;

diff --git a/riscv/insns/fdiv_d.h b/riscv/insns/fdiv_d.h
index aa00c98dcae8ae2e77c30f0e3ed933fa52619c1e..e21570278522f29d4cdc21afd403c3e2baea8377 100644 (file)
--- a/riscv/insns/fdiv_d.h
+++ b/riscv/insns/fdiv_d.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f64_div(FRS1, FRS2);
+WRITE_FRD(f64_div(FRS1, FRS2));
 set_fp_exceptions;

diff --git a/riscv/insns/fdiv_s.h b/riscv/insns/fdiv_s.h
index 8c765875180928f81f702fd28c119ed94b168e57..2644d08828d2c2be8570df6aabbf9ea18d1a57ca 100644 (file)
--- a/riscv/insns/fdiv_s.h
+++ b/riscv/insns/fdiv_s.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f32_div(FRS1, FRS2);
+WRITE_FRD(f32_div(FRS1, FRS2));
 set_fp_exceptions;

diff --git a/riscv/insns/feq_d.h b/riscv/insns/feq_d.h
index 9db876060e2d2cab82419356644baea24e26165f..516fb5965cb1dac9525b17428fe73770c1015581 100644 (file)
--- a/riscv/insns/feq_d.h
+++ b/riscv/insns/feq_d.h
@@ -1,3 +1,3 @@
 require_fp;
-RD = f64_eq(FRS1, FRS2);
+WRITE_RD(f64_eq(FRS1, FRS2));
 set_fp_exceptions;

diff --git a/riscv/insns/feq_s.h b/riscv/insns/feq_s.h
index 658e8f6fe3dfb6af50be851bd69f86e5bfe41625..b44da24e02b794536ff9535652427d7e97beb49b 100644 (file)
--- a/riscv/insns/feq_s.h
+++ b/riscv/insns/feq_s.h
@@ -1,3 +1,3 @@
 require_fp;
-RD = f32_eq(FRS1, FRS2);
+WRITE_RD(f32_eq(FRS1, FRS2));
 set_fp_exceptions;

diff --git a/riscv/insns/fld.h b/riscv/insns/fld.h
index 54d4a779e9eefe9840ae27eb8126b9baf2647610..1bc83cfdeef0d5c50c220591021ef1dbb93c0072 100644 (file)
--- a/riscv/insns/fld.h
+++ b/riscv/insns/fld.h
@@ -1,2 +1,2 @@
 require_fp;
-FRD = MMU.load_int64(RS1 + insn.i_imm());
+WRITE_FRD(MMU.load_int64(RS1 + insn.i_imm()));

diff --git a/riscv/insns/fle_d.h b/riscv/insns/fle_d.h
index da7618725c8c6cfd1d18f7d5b44fe3699b717eba..72dcc7e650560d450c357cb43b83e6d373ab64d5 100644 (file)
--- a/riscv/insns/fle_d.h
+++ b/riscv/insns/fle_d.h
@@ -1,3 +1,3 @@
 require_fp;
-RD = f64_le(FRS1, FRS2);
+WRITE_RD(f64_le(FRS1, FRS2));
 set_fp_exceptions;

diff --git a/riscv/insns/fle_s.h b/riscv/insns/fle_s.h
index 9c83a17f00135d71f5d6a2fa23bafe4732af74a5..9c85b4a586b750fc74657dd652555300a7e9c227 100644 (file)
--- a/riscv/insns/fle_s.h
+++ b/riscv/insns/fle_s.h
@@ -1,3 +1,3 @@
 require_fp;
-RD = f32_le(FRS1, FRS2);
+WRITE_RD(f32_le(FRS1, FRS2));
 set_fp_exceptions;

diff --git a/riscv/insns/flt_d.h b/riscv/insns/flt_d.h
index 01d135a93de845723f52517502feea8c98613aba..335e4a80125d47d0d1e0ead1097c0c3123cbeb4f 100644 (file)
--- a/riscv/insns/flt_d.h
+++ b/riscv/insns/flt_d.h
@@ -1,3 +1,3 @@
 require_fp;
-RD = f64_lt(FRS1, FRS2);
+WRITE_RD(f64_lt(FRS1, FRS2));
 set_fp_exceptions;

diff --git a/riscv/insns/flt_s.h b/riscv/insns/flt_s.h
index 52eee5d34600f7ac8efca0f2bd974801fa526b27..7a2178521c0e930a80cc256f6fe21fced6e50750 100644 (file)
--- a/riscv/insns/flt_s.h
+++ b/riscv/insns/flt_s.h
@@ -1,3 +1,3 @@
 require_fp;
-RD = f32_lt(FRS1, FRS2);
+WRITE_RD(f32_lt(FRS1, FRS2));
 set_fp_exceptions;

diff --git a/riscv/insns/flw.h b/riscv/insns/flw.h
index 1559ecc51237f96b31bbcb1b9e9aba145ff179ae..a5f7d16eaab263ec39022ea4f342d5cc5affbbb4 100644 (file)
--- a/riscv/insns/flw.h
+++ b/riscv/insns/flw.h
@@ -1,2 +1,2 @@
 require_fp;
-FRD = MMU.load_int32(RS1 + insn.i_imm());
+WRITE_FRD(MMU.load_int32(RS1 + insn.i_imm()));

diff --git a/riscv/insns/fmadd_d.h b/riscv/insns/fmadd_d.h
index f67853eef3ebdab480a54d453c19f0a8e4df422e..8640e7f46e17fa4b2447c45803c42f49d87560e7 100644 (file)
--- a/riscv/insns/fmadd_d.h
+++ b/riscv/insns/fmadd_d.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f64_mulAdd(FRS1, FRS2, FRS3);
+WRITE_FRD(f64_mulAdd(FRS1, FRS2, FRS3));
 set_fp_exceptions;

diff --git a/riscv/insns/fmadd_s.h b/riscv/insns/fmadd_s.h
index 19db6421fd2f66d121f69d0df12b17514cdfabf2..f8b0a5f1ada3112efb31645ee769f20a5e3ede8c 100644 (file)
--- a/riscv/insns/fmadd_s.h
+++ b/riscv/insns/fmadd_s.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f32_mulAdd(FRS1, FRS2, FRS3);
+WRITE_FRD(f32_mulAdd(FRS1, FRS2, FRS3));
 set_fp_exceptions;

diff --git a/riscv/insns/fmax_d.h b/riscv/insns/fmax_d.h
index cbbb34343b79f983f902da3254b0fa8a4e92f72a..a26aeabb4c6537d9fcf3990df9febcff9aec29be 100644 (file)
--- a/riscv/insns/fmax_d.h
+++ b/riscv/insns/fmax_d.h
@@ -1,4 +1,4 @@
 require_fp;
-FRD = isNaNF64UI(FRS2) || f64_le_quiet(FRS2,FRS1) /* && FRS1 not NaN */
-      ? FRS1 : FRS2;
+WRITE_FRD(isNaNF64UI(FRS2) || f64_le_quiet(FRS2,FRS1) /* && FRS1 not NaN */
+      ? FRS1 : FRS2);
 set_fp_exceptions;

diff --git a/riscv/insns/fmax_s.h b/riscv/insns/fmax_s.h
index 8df665f8dc84f4458f59db6255fa158284087097..b16134bbf8fed3482a7c595fcf524a7db87cf545 100644 (file)
--- a/riscv/insns/fmax_s.h
+++ b/riscv/insns/fmax_s.h
@@ -1,4 +1,4 @@
 require_fp;
-FRD = isNaNF32UI(FRS2) || f32_le_quiet(FRS2,FRS1) /* && FRS1 not NaN */
-      ? FRS1 : FRS2;
+WRITE_FRD(isNaNF32UI(FRS2) || f32_le_quiet(FRS2,FRS1) /* && FRS1 not NaN */
+      ? FRS1 : FRS2);
 set_fp_exceptions;

diff --git a/riscv/insns/fmin_d.h b/riscv/insns/fmin_d.h
index 3d3d454e0dd27a7373b9c60ff212854d352094b0..c095adee4587f860f26e0a2dce8963a94bf366b5 100644 (file)
--- a/riscv/insns/fmin_d.h
+++ b/riscv/insns/fmin_d.h
@@ -1,4 +1,4 @@
 require_fp;
-FRD = isNaNF64UI(FRS2) || f64_lt_quiet(FRS1,FRS2) /* && FRS1 not NaN */
-      ? FRS1 : FRS2;
+WRITE_FRD(isNaNF64UI(FRS2) || f64_lt_quiet(FRS1,FRS2) /* && FRS1 not NaN */
+      ? FRS1 : FRS2);
 set_fp_exceptions;

diff --git a/riscv/insns/fmin_s.h b/riscv/insns/fmin_s.h
index 994c86089d029a6ba55e057a476548813a23f79f..e2fdc5c3bcec4276ca28af21c2a86b679a3116eb 100644 (file)
--- a/riscv/insns/fmin_s.h
+++ b/riscv/insns/fmin_s.h
@@ -1,4 +1,4 @@
 require_fp;
-FRD = isNaNF32UI(FRS2) || f32_lt_quiet(FRS1,FRS2) /* && FRS1 not NaN */
-      ? FRS1 : FRS2;
+WRITE_FRD(isNaNF32UI(FRS2) || f32_lt_quiet(FRS1,FRS2) /* && FRS1 not NaN */
+      ? FRS1 : FRS2);
 set_fp_exceptions;

diff --git a/riscv/insns/fmsub_d.h b/riscv/insns/fmsub_d.h
index b1e93408f85abc46b8b99fb21405577dcf43152c..13e9fcc6623f61e43f0fcd5e9aec0bfc4027d89f 100644 (file)
--- a/riscv/insns/fmsub_d.h
+++ b/riscv/insns/fmsub_d.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f64_mulAdd(FRS1, FRS2, FRS3 ^ (uint64_t)INT64_MIN);
+WRITE_FRD(f64_mulAdd(FRS1, FRS2, FRS3 ^ (uint64_t)INT64_MIN));
 set_fp_exceptions;

diff --git a/riscv/insns/fmsub_s.h b/riscv/insns/fmsub_s.h
index d3349f5a32eb82ceeb453c269996f08027bed82e..c6aa418521cdc9952538c5774201f9a733506c37 100644 (file)
--- a/riscv/insns/fmsub_s.h
+++ b/riscv/insns/fmsub_s.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f32_mulAdd(FRS1, FRS2, FRS3 ^ (uint32_t)INT32_MIN);
+WRITE_FRD(f32_mulAdd(FRS1, FRS2, FRS3 ^ (uint32_t)INT32_MIN));
 set_fp_exceptions;

diff --git a/riscv/insns/fmul_d.h b/riscv/insns/fmul_d.h
index a1462d3e1631b0f74a8f914c7f75ca3fd2acabe6..e2ca1c2a68445ee74b9af3adc0c8e8072583d7fb 100644 (file)
--- a/riscv/insns/fmul_d.h
+++ b/riscv/insns/fmul_d.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f64_mulAdd(FRS1, FRS2, (FRS1 ^ FRS2) & (uint64_t)INT64_MIN);
+WRITE_FRD(f64_mulAdd(FRS1, FRS2, (FRS1 ^ FRS2) & (uint64_t)INT64_MIN));
 set_fp_exceptions;

diff --git a/riscv/insns/fmul_s.h b/riscv/insns/fmul_s.h
index a954c3d1438f691fcae83246089906f2f3519681..f564803475ca4cb6b78f324b140793e288138470 100644 (file)
--- a/riscv/insns/fmul_s.h
+++ b/riscv/insns/fmul_s.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f32_mulAdd(FRS1, FRS2, (FRS1 ^ FRS2) & (uint32_t)INT32_MIN);
+WRITE_FRD(f32_mulAdd(FRS1, FRS2, (FRS1 ^ FRS2) & (uint32_t)INT32_MIN));
 set_fp_exceptions;

diff --git a/riscv/insns/fmv_d_x.h b/riscv/insns/fmv_d_x.h
index 29792ec425b41048e960568fc37f712dcc13eeae..35c1977c82610e38ef5a4184bbf76fda658c8ca9 100644 (file)
--- a/riscv/insns/fmv_d_x.h
+++ b/riscv/insns/fmv_d_x.h
@@ -1,3 +1,3 @@
 require_xpr64;
 require_fp;
-FRD = RS1;
+WRITE_FRD(RS1);

diff --git a/riscv/insns/fmv_s_x.h b/riscv/insns/fmv_s_x.h
index 54546ea23805f62dd3fd4a2b05169348ca6a411a..f3eac828625486d3590c9138761ebfa07b6bd7cd 100644 (file)
--- a/riscv/insns/fmv_s_x.h
+++ b/riscv/insns/fmv_s_x.h
@@ -1,2 +1,2 @@
 require_fp;
-FRD = RS1;
+WRITE_FRD(RS1);

diff --git a/riscv/insns/fmv_x_d.h b/riscv/insns/fmv_x_d.h
index a067fd9dfce3131c7f29d238265904dc19892335..5bcf2b5909ccf79795e89c7f16a97e980007a40b 100644 (file)
--- a/riscv/insns/fmv_x_d.h
+++ b/riscv/insns/fmv_x_d.h
@@ -1,3 +1,3 @@
 require_xpr64;
 require_fp;
-RD = FRS1;
+WRITE_RD(FRS1);

diff --git a/riscv/insns/fmv_x_s.h b/riscv/insns/fmv_x_s.h
index d3d59b280fd0cc103703386b473124b2170c678b..46a94886e6b63fe7658b70ff1aab4aad2e1856a4 100644 (file)
--- a/riscv/insns/fmv_x_s.h
+++ b/riscv/insns/fmv_x_s.h
@@ -1,2 +1,2 @@
 require_fp;
-RD = sext32(FRS1);
+WRITE_RD(sext32(FRS1));

diff --git a/riscv/insns/fnmadd_d.h b/riscv/insns/fnmadd_d.h
index 9529aebe46b0cdc35e4e615ba8accbb61b8828cc..705470bf9294e2f4afe6cfaaa9914d656d86c5d9 100644 (file)
--- a/riscv/insns/fnmadd_d.h
+++ b/riscv/insns/fnmadd_d.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f64_mulAdd(FRS1 ^ (uint64_t)INT64_MIN, FRS2, FRS3 ^ (uint64_t)INT64_MIN);
+WRITE_FRD(f64_mulAdd(FRS1 ^ (uint64_t)INT64_MIN, FRS2, FRS3 ^ (uint64_t)INT64_MIN));
 set_fp_exceptions;

diff --git a/riscv/insns/fnmadd_s.h b/riscv/insns/fnmadd_s.h
index 2052b938ddd568786445ea793e6bb45fd600a768..2df321b5f9eb4088f6d9f5e304f372be45407833 100644 (file)
--- a/riscv/insns/fnmadd_s.h
+++ b/riscv/insns/fnmadd_s.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f32_mulAdd(FRS1 ^ (uint32_t)INT32_MIN, FRS2, FRS3 ^ (uint32_t)INT32_MIN);
+WRITE_FRD(f32_mulAdd(FRS1 ^ (uint32_t)INT32_MIN, FRS2, FRS3 ^ (uint32_t)INT32_MIN));
 set_fp_exceptions;

diff --git a/riscv/insns/fnmsub_d.h b/riscv/insns/fnmsub_d.h
index 31a5b394036c9a6b488eda0149fe99ba493a85f1..c38d2bf0608ebde7311967fce9b0da777b08b9d9 100644 (file)
--- a/riscv/insns/fnmsub_d.h
+++ b/riscv/insns/fnmsub_d.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f64_mulAdd(FRS1 ^ (uint64_t)INT64_MIN, FRS2, FRS3);
+WRITE_FRD(f64_mulAdd(FRS1 ^ (uint64_t)INT64_MIN, FRS2, FRS3));
 set_fp_exceptions;

diff --git a/riscv/insns/fnmsub_s.h b/riscv/insns/fnmsub_s.h
index 811a35a6ef2c4f5ca1c3fec69ce3487f43154d71..c3fa995869ba3b2d98762f10da123a0d83bde52f 100644 (file)
--- a/riscv/insns/fnmsub_s.h
+++ b/riscv/insns/fnmsub_s.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f32_mulAdd(FRS1 ^ (uint32_t)INT32_MIN, FRS2, FRS3);
+WRITE_FRD(f32_mulAdd(FRS1 ^ (uint32_t)INT32_MIN, FRS2, FRS3));
 set_fp_exceptions;

diff --git a/riscv/insns/frsr.h b/riscv/insns/frsr.h
index ef121e391d5535448a1f54d8a1c243df4abda610..4d807693550470e9b7eac3b6c6dbe46e7b92de16 100644 (file)
--- a/riscv/insns/frsr.h
+++ b/riscv/insns/frsr.h
@@ -1,2 +1,2 @@
 require_fp;
-RD = p->get_fsr();
+WRITE_RD(p->get_fsr());

diff --git a/riscv/insns/fsgnj_d.h b/riscv/insns/fsgnj_d.h
index f66e804dccf3e6032467281f8fc1d8b995ea8014..74ef3f6c652422aaac9dd2661ae3d611d49ded29 100644 (file)
--- a/riscv/insns/fsgnj_d.h
+++ b/riscv/insns/fsgnj_d.h
@@ -1,2 +1,2 @@
 require_fp;
-FRD = (FRS1 &~ INT64_MIN) | (FRS2 & INT64_MIN);
+WRITE_FRD((FRS1 &~ INT64_MIN) | (FRS2 & INT64_MIN));

diff --git a/riscv/insns/fsgnj_s.h b/riscv/insns/fsgnj_s.h
index 35609ac41c22f8ab9122688e832555b3c31c3861..4f852b43e1b86c7a580aa93f086c3250db906a15 100644 (file)
--- a/riscv/insns/fsgnj_s.h
+++ b/riscv/insns/fsgnj_s.h
@@ -1,2 +1,2 @@
 require_fp;
-FRD = (FRS1 &~ (uint32_t)INT32_MIN) | (FRS2 & (uint32_t)INT32_MIN);
+WRITE_FRD((FRS1 &~ (uint32_t)INT32_MIN) | (FRS2 & (uint32_t)INT32_MIN));

diff --git a/riscv/insns/fsgnjn_d.h b/riscv/insns/fsgnjn_d.h
index 22de215b20adfe97a85d4a85513b38fb944ce5ba..e214f1d7c3649a0b8d6c73b7265734e904c2b08a 100644 (file)
--- a/riscv/insns/fsgnjn_d.h
+++ b/riscv/insns/fsgnjn_d.h
@@ -1,2 +1,2 @@
 require_fp;
-FRD = (FRS1 &~ INT64_MIN) | ((~FRS2) & INT64_MIN);
+WRITE_FRD((FRS1 &~ INT64_MIN) | ((~FRS2) & INT64_MIN));

diff --git a/riscv/insns/fsgnjn_s.h b/riscv/insns/fsgnjn_s.h
index dd66d71a73bb00f23827c4301afeb34b71ae44df..b098150c79ba8fd2776911c08e1c3304608b569c 100644 (file)
--- a/riscv/insns/fsgnjn_s.h
+++ b/riscv/insns/fsgnjn_s.h
@@ -1,2 +1,2 @@
 require_fp;
-FRD = (FRS1 &~ (uint32_t)INT32_MIN) | ((~FRS2) & (uint32_t)INT32_MIN);
+WRITE_FRD((FRS1 &~ (uint32_t)INT32_MIN) | ((~FRS2) & (uint32_t)INT32_MIN));

diff --git a/riscv/insns/fsgnjx_d.h b/riscv/insns/fsgnjx_d.h
index 331b6e4f4c8ac496b52dd16c2cba717d70f19d05..2bcef6f306a84573a5d4e81ea8e69483da89ad2c 100644 (file)
--- a/riscv/insns/fsgnjx_d.h
+++ b/riscv/insns/fsgnjx_d.h
@@ -1,2 +1,2 @@
 require_fp;
-FRD = FRS1 ^ (FRS2 & INT64_MIN);
+WRITE_FRD(FRS1 ^ (FRS2 & INT64_MIN));

diff --git a/riscv/insns/fsgnjx_s.h b/riscv/insns/fsgnjx_s.h
index b4554066e59de99f3c409da64039bdcfa52c35e9..69b2d98c4b0c4c0de47ba7d6377e660b55e55978 100644 (file)
--- a/riscv/insns/fsgnjx_s.h
+++ b/riscv/insns/fsgnjx_s.h
@@ -1,2 +1,2 @@
 require_fp;
-FRD = FRS1 ^ (FRS2 & (uint32_t)INT32_MIN);
+WRITE_FRD(FRS1 ^ (FRS2 & (uint32_t)INT32_MIN));

diff --git a/riscv/insns/fsqrt_d.h b/riscv/insns/fsqrt_d.h
index 7647c9c8d630f0dcf2b075998e3c881cbe241c28..0ff5daa84544f3e04b4bcfa267def13eb9da4de3 100644 (file)
--- a/riscv/insns/fsqrt_d.h
+++ b/riscv/insns/fsqrt_d.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f64_sqrt(FRS1);
+WRITE_FRD(f64_sqrt(FRS1));
 set_fp_exceptions;

diff --git a/riscv/insns/fsqrt_s.h b/riscv/insns/fsqrt_s.h
index 426f24171118de816f72a09c0ce16ef88d747c33..ea1f31ac85bbca49be63e4655e1b3507f944a7b5 100644 (file)
--- a/riscv/insns/fsqrt_s.h
+++ b/riscv/insns/fsqrt_s.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f32_sqrt(FRS1);
+WRITE_FRD(f32_sqrt(FRS1));
 set_fp_exceptions;

diff --git a/riscv/insns/fssr.h b/riscv/insns/fssr.h
index a9acca6c4d4b0bab34043a2bcd402fa36e7c5688..5695d8cec5099574f0be099afff2c3fc73adcc20 100644 (file)
--- a/riscv/insns/fssr.h
+++ b/riscv/insns/fssr.h
@@ -1,2 +1,2 @@
 require_fp;
-RD = p->set_fsr(RS1);
+WRITE_RD(p->set_fsr(RS1));

diff --git a/riscv/insns/fsub_d.h b/riscv/insns/fsub_d.h
index fcabe0e537849df5702edb1952b5c4a7c92f5134..238ee9e8fb536148dabb0002820ec75310bcd28d 100644 (file)
--- a/riscv/insns/fsub_d.h
+++ b/riscv/insns/fsub_d.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f64_mulAdd(FRS1, 0x3ff0000000000000ULL, FRS2 ^ (uint64_t)INT64_MIN);
+WRITE_FRD(f64_mulAdd(FRS1, 0x3ff0000000000000ULL, FRS2 ^ (uint64_t)INT64_MIN));
 set_fp_exceptions;

diff --git a/riscv/insns/fsub_s.h b/riscv/insns/fsub_s.h
index 1ff72d2e1714eb91dee0f11dfd75bd22751effd0..a30b4f9b82f250b7eef205b6f320e2b24f51c007 100644 (file)
--- a/riscv/insns/fsub_s.h
+++ b/riscv/insns/fsub_s.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f32_mulAdd(FRS1, 0x3f800000, FRS2 ^ (uint32_t)INT32_MIN);
+WRITE_FRD(f32_mulAdd(FRS1, 0x3f800000, FRS2 ^ (uint32_t)INT32_MIN));
 set_fp_exceptions;

diff --git a/riscv/insns/jal.h b/riscv/insns/jal.h
index 9caac55d6006847c504d4d80f63fd29d2d68ee94..2694deef1c7394c969283afea3f55340dd3dd868 100644 (file)
--- a/riscv/insns/jal.h
+++ b/riscv/insns/jal.h
@@ -1,2 +1,2 @@
-RD = npc;
+WRITE_RD(npc);
 set_pc(JUMP_TARGET);

diff --git a/riscv/insns/jalr.h b/riscv/insns/jalr.h
index fa6d7f1fdb04b4e70307c309f4ab7a46022c9853..3924aa45f3cf54536d6c292acd1cec22a950eb3d 100644 (file)
--- a/riscv/insns/jalr.h
+++ b/riscv/insns/jalr.h
@@ -1,3 +1,3 @@
 reg_t temp = RS1;
-RD = npc;
+WRITE_RD(npc);
 set_pc((temp + insn.i_imm()) & ~1);

diff --git a/riscv/insns/lb.h b/riscv/insns/lb.h
index 36acd7bd719063ccf3012ea48ed5efe02e5205fa..0f0999caa385317e543baca04266e73d63febe7f 100644 (file)
--- a/riscv/insns/lb.h
+++ b/riscv/insns/lb.h
@@ -1 +1 @@
-RD = MMU.load_int8(RS1 + insn.i_imm());
+WRITE_RD(MMU.load_int8(RS1 + insn.i_imm()));

diff --git a/riscv/insns/lbu.h b/riscv/insns/lbu.h
index f1e94723fa76dc2d2609e188efca51dff0febe65..64d4a688b97d57d3ede6a7b9545157f52f0b145e 100644 (file)
--- a/riscv/insns/lbu.h
+++ b/riscv/insns/lbu.h
@@ -1 +1 @@
-RD = MMU.load_uint8(RS1 + insn.i_imm());
+WRITE_RD(MMU.load_uint8(RS1 + insn.i_imm()));

diff --git a/riscv/insns/ld.h b/riscv/insns/ld.h
index e57daac9b483430fd06b0de5f35b7f255321be9e..d36e172e758d3d167edb69f2019b6b26f5e7fd5e 100644 (file)
--- a/riscv/insns/ld.h
+++ b/riscv/insns/ld.h
@@ -1,2 +1,2 @@
 require_xpr64;
-RD = MMU.load_int64(RS1 + insn.i_imm());
+WRITE_RD(MMU.load_int64(RS1 + insn.i_imm()));

diff --git a/riscv/insns/lh.h b/riscv/insns/lh.h
index b158ada1b499cec3ed10268cd1d24bc71c915bef..0d458e0ee1004337d7dd08953a8d8f126cb55a4f 100644 (file)
--- a/riscv/insns/lh.h
+++ b/riscv/insns/lh.h
@@ -1 +1 @@
-RD = MMU.load_int16(RS1 + insn.i_imm());
+WRITE_RD(MMU.load_int16(RS1 + insn.i_imm()));

diff --git a/riscv/insns/lhu.h b/riscv/insns/lhu.h
index 842a7527f65e2ae5dcf898cf234ed834298716e7..9d240702adc5c03077bf48d3ba2f5dd1d7d3161d 100644 (file)
--- a/riscv/insns/lhu.h
+++ b/riscv/insns/lhu.h
@@ -1 +1 @@
-RD = MMU.load_uint16(RS1 + insn.i_imm());
+WRITE_RD(MMU.load_uint16(RS1 + insn.i_imm()));

diff --git a/riscv/insns/lr_d.h b/riscv/insns/lr_d.h
index 3d2aacee9d2946aaa20f57a8d4f49ab91220fd48..4e8ac181d7d17c9246a2244dc007b2c10469f2d5 100644 (file)
--- a/riscv/insns/lr_d.h
+++ b/riscv/insns/lr_d.h
@@ -1,3 +1,3 @@
 require_xpr64;
 p->get_state()->load_reservation = RS1;
-RD = MMU.load_int64(RS1);
+WRITE_RD(MMU.load_int64(RS1));

diff --git a/riscv/insns/lr_w.h b/riscv/insns/lr_w.h
index 7ff48ea813098c17f4ebf35a7957ebbc4037d2f0..2b954195b79b9eca3ca5289b1b1efaf0db6880c5 100644 (file)
--- a/riscv/insns/lr_w.h
+++ b/riscv/insns/lr_w.h
@@ -1,2 +1,2 @@
 p->get_state()->load_reservation = RS1;
-RD = MMU.load_int32(RS1);
+WRITE_RD(MMU.load_int32(RS1));

diff --git a/riscv/insns/lui.h b/riscv/insns/lui.h
index 8dce543216513ed543c57cd3661046d8973bf83d..c7b5264e0042407f23c9e58154c6356c8538150a 100644 (file)
--- a/riscv/insns/lui.h
+++ b/riscv/insns/lui.h
@@ -1 +1 @@
-RD = insn.u_imm();
+WRITE_RD(insn.u_imm());

diff --git a/riscv/insns/lw.h b/riscv/insns/lw.h
index 1b4ea3519d9daac9665899cdbf21cd04a073acfc..4e8ed040d19e2e2a646c1ea4e97abe113a998720 100644 (file)
--- a/riscv/insns/lw.h
+++ b/riscv/insns/lw.h
@@ -1 +1 @@
-RD = MMU.load_int32(RS1 + insn.i_imm());
+WRITE_RD(MMU.load_int32(RS1 + insn.i_imm()));

diff --git a/riscv/insns/lwu.h b/riscv/insns/lwu.h
index 6c4ad769da911f5f2117708a965a89ae62b5e0fa..5535baf15b9a41ad0d5c1733191a8ca11b6e66bd 100644 (file)
--- a/riscv/insns/lwu.h
+++ b/riscv/insns/lwu.h
@@ -1,2 +1,2 @@
 require_xpr64;
-RD = MMU.load_uint32(RS1 + insn.i_imm());
+WRITE_RD(MMU.load_uint32(RS1 + insn.i_imm()));

diff --git a/riscv/insns/mfpcr.h b/riscv/insns/mfpcr.h
index f711931d466794056c1657652053e3fe1a18a8c3..a539115323d14f8478c55fbfa6c05881d1e68b36 100644 (file)
--- a/riscv/insns/mfpcr.h
+++ b/riscv/insns/mfpcr.h
@@ -1,2 +1,2 @@
 require_supervisor;
-RD = p->get_pcr(insn.rs1());
+WRITE_RD(p->get_pcr(insn.rs1()));

diff --git a/riscv/insns/mtpcr.h b/riscv/insns/mtpcr.h
index 2d4121f5da1f10e2d2db17d5c9248480b76461a0..ca22db174256a407b16308060e46f7de9a465bc7 100644 (file)
--- a/riscv/insns/mtpcr.h
+++ b/riscv/insns/mtpcr.h
@@ -1,2 +1,2 @@
 require_supervisor;
-RD = p->set_pcr(insn.rs1(), RS2);
+WRITE_RD(p->set_pcr(insn.rs1(), RS2));

diff --git a/riscv/insns/mul.h b/riscv/insns/mul.h
index 770d73388a2380b142e4f6b8524a60bef24628a5..9725bfd7a0fc89f926028297ab9fd4ae310330b3 100644 (file)
--- a/riscv/insns/mul.h
+++ b/riscv/insns/mul.h
@@ -1 +1 @@
-RD = sext_xprlen(RS1 * RS2);
+WRITE_RD(sext_xprlen(RS1 * RS2));

diff --git a/riscv/insns/mulh.h b/riscv/insns/mulh.h
index f771a621d7d0c95777acf8f0ff20150b435d8b45..f63869d7b60aef8605ed86bbe9676460ac345178 100644 (file)
--- a/riscv/insns/mulh.h
+++ b/riscv/insns/mulh.h
@@ -2,7 +2,7 @@ if(xpr64)
 {
   int64_t a = RS1;
   int64_t b = RS2;
-  RD = (int128_t(a) * int128_t(b)) >> 64;
+  WRITE_RD((int128_t(a) * int128_t(b)) >> 64);
 }
 else
-  RD = sext32((sext32(RS1) * sext32(RS2)) >> 32);
+  WRITE_RD(sext32((sext32(RS1) * sext32(RS2)) >> 32));

diff --git a/riscv/insns/mulhsu.h b/riscv/insns/mulhsu.h
index c832657ead0e131f0b5d51d6feabe7af6bc31142..d62256eacb0272722ff80d1c3ff2a6820e7e5c55 100644 (file)
--- a/riscv/insns/mulhsu.h
+++ b/riscv/insns/mulhsu.h
@@ -2,7 +2,7 @@ if(xpr64)
 {
   int64_t a = RS1;
   uint64_t b = RS2;
-  RD = (int128_t(a) * uint128_t(b)) >> 64;
+  WRITE_RD((int128_t(a) * uint128_t(b)) >> 64);
 }
 else
-  RD = sext32((sext32(RS1) * reg_t((uint32_t)RS2)) >> 32);
+  WRITE_RD(sext32((sext32(RS1) * reg_t((uint32_t)RS2)) >> 32));

diff --git a/riscv/insns/mulhu.h b/riscv/insns/mulhu.h
index 63344263fe3588a5195eb09fdb5ea075f431d9b1..2d6f48c7e6db30d1a4361afc724f37c0f0b5ba77 100644 (file)
--- a/riscv/insns/mulhu.h
+++ b/riscv/insns/mulhu.h
@@ -1,4 +1,4 @@
 if(xpr64)
-  RD = (uint128_t(RS1) * uint128_t(RS2)) >> 64;
+  WRITE_RD((uint128_t(RS1) * uint128_t(RS2)) >> 64);
 else
-  RD = sext32(((uint64_t)(uint32_t)RS1 * (uint64_t)(uint32_t)RS2) >> 32);
+  WRITE_RD(sext32(((uint64_t)(uint32_t)RS1 * (uint64_t)(uint32_t)RS2) >> 32));

diff --git a/riscv/insns/mulw.h b/riscv/insns/mulw.h
index 7b0a934b68e20ee022e7c871e88dfb8210a413a4..9f74fcfd57f8e9848f96c8067484dee7f91580a6 100644 (file)
--- a/riscv/insns/mulw.h
+++ b/riscv/insns/mulw.h
@@ -1,2 +1,2 @@
 require_xpr64;
-RD = sext32(RS1 * RS2);
+WRITE_RD(sext32(RS1 * RS2));

diff --git a/riscv/insns/or.h b/riscv/insns/or.h
index 07bcac3555c41da7eacc84775e17b7bb4d5830a7..3f2fffc22e2a2ca0ae6663c79f31d27f5cf94ffb 100644 (file)
--- a/riscv/insns/or.h
+++ b/riscv/insns/or.h
@@ -1 +1 @@
-RD = RS1 | RS2;
+WRITE_RD(RS1 | RS2);

diff --git a/riscv/insns/ori.h b/riscv/insns/ori.h
index 695a56ba0ecec63e8c7528c1708b038c4c113394..6403c39b5b476fa98948a6aa44dbbbdb1b430a74 100644 (file)
--- a/riscv/insns/ori.h
+++ b/riscv/insns/ori.h
@@ -1 +1 @@
-RD = insn.i_imm() | RS1;
+WRITE_RD(insn.i_imm() | RS1);

diff --git a/riscv/insns/rdcycle.h b/riscv/insns/rdcycle.h
index 7ebe9863bf1bfec81c9b9fc5e099fb6a26f0faa1..5467f8a83cf001cfe47b12421fd77a5fb3a90efa 100644 (file)
--- a/riscv/insns/rdcycle.h
+++ b/riscv/insns/rdcycle.h
@@ -1 +1 @@
-RD = sext_xprlen(p->get_state()->cycle);
+WRITE_RD(sext_xprlen(p->get_state()->cycle));

diff --git a/riscv/insns/rem.h b/riscv/insns/rem.h
index 8094b5bba1715b3c59db12b7e99073f2644d7069..fa98ac6893f8a2919c3a974a916889cc8757427b 100644 (file)
--- a/riscv/insns/rem.h
+++ b/riscv/insns/rem.h
@@ -1,8 +1,8 @@
 sreg_t lhs = sext_xprlen(RS1);
 sreg_t rhs = sext_xprlen(RS2);
 if(rhs == 0)
-  RD = lhs;
+  WRITE_RD(lhs);
 else if(lhs == INT64_MIN && rhs == -1)
-  RD = 0;
+  WRITE_RD(0);
 else
-  RD = sext_xprlen(lhs % rhs);
+  WRITE_RD(sext_xprlen(lhs % rhs));

diff --git a/riscv/insns/remu.h b/riscv/insns/remu.h
index 1057789e80633bf1eea7cd2a29adc8607af9bdda..646bb3a65fa9ccd053b666eb070b81c45ac75139 100644 (file)
--- a/riscv/insns/remu.h
+++ b/riscv/insns/remu.h
@@ -1,6 +1,6 @@
 reg_t lhs = zext_xprlen(RS1);
 reg_t rhs = zext_xprlen(RS2);
 if(rhs == 0)
-  RD = sext_xprlen(RS1);
+  WRITE_RD(sext_xprlen(RS1));
 else
-  RD = sext_xprlen(lhs % rhs);
+  WRITE_RD(sext_xprlen(lhs % rhs));

diff --git a/riscv/insns/remuw.h b/riscv/insns/remuw.h
index 1ef810ceae22cfd4530a3c3a0078732fc352bb2f..bec7059c1ebea7196027a02b9da31f50e5edc399 100644 (file)
--- a/riscv/insns/remuw.h
+++ b/riscv/insns/remuw.h
@@ -2,6 +2,6 @@ require_xpr64;
 reg_t lhs = zext32(RS1);
 reg_t rhs = zext32(RS2);
 if(rhs == 0)
-  RD = sext32(lhs);
+  WRITE_RD(sext32(lhs));
 else
-  RD = sext32(lhs % rhs);
+  WRITE_RD(sext32(lhs % rhs));

diff --git a/riscv/insns/remw.h b/riscv/insns/remw.h
index cc89fa740678ca8bfc6a92ab09fc7b22e34b7d2f..b8f4597c29055ba43a557c32d83a0954f0c19b82 100644 (file)
--- a/riscv/insns/remw.h
+++ b/riscv/insns/remw.h
@@ -2,6 +2,6 @@ require_xpr64;
 sreg_t lhs = sext32(RS1);
 sreg_t rhs = sext32(RS2);
 if(rhs == 0)
-  RD = lhs;
+  WRITE_RD(lhs);
 else
-  RD = sext32(lhs % rhs);
+  WRITE_RD(sext32(lhs % rhs));

diff --git a/riscv/insns/sc_d.h b/riscv/insns/sc_d.h
index 9ad962c6bd810736e1baf2885eba19da89a3d18d..3b4824445c77a6a148fde9a231ba5d52852e8b3c 100644 (file)
--- a/riscv/insns/sc_d.h
+++ b/riscv/insns/sc_d.h
@@ -2,7 +2,7 @@ require_xpr64;
 if (RS1 == p->get_state()->load_reservation)
 {
   MMU.store_uint64(RS1, RS2);
-  RD = 0;
+  WRITE_RD(0);
 }
 else
-  RD = 1;
+  WRITE_RD(1);

diff --git a/riscv/insns/sc_w.h b/riscv/insns/sc_w.h
index 3ad79ac24f72241877530ddb8ed9e9bb2d98774c..729973d478c12486da0c6f3271c2c4da9abd2042 100644 (file)
--- a/riscv/insns/sc_w.h
+++ b/riscv/insns/sc_w.h
@@ -1,7 +1,7 @@
 if (RS1 == p->get_state()->load_reservation)
 {
   MMU.store_uint32(RS1, RS2);
-  RD = 0;
+  WRITE_RD(0);
 }
 else
-  RD = 1;
+  WRITE_RD(1);

diff --git a/riscv/insns/setpcr.h b/riscv/insns/setpcr.h
index 287667073ded742027a13f31f5bd21b7a2680f08..f001827193c67e90bd32209d764d36dffc325099 100644 (file)
--- a/riscv/insns/setpcr.h
+++ b/riscv/insns/setpcr.h
@@ -1,2 +1,2 @@
 require_supervisor;
-RD = p->set_pcr(insn.rs1(), p->get_pcr(insn.rs1()) | insn.i_imm());
+WRITE_RD(p->set_pcr(insn.rs1(), p->get_pcr(insn.rs1()) | insn.i_imm()));

diff --git a/riscv/insns/sll.h b/riscv/insns/sll.h
index 86eb96682ca3a1818f29ed18310415a9647fcaf1..48c0acfca7284b1e2db889feb6adc0e5853085f2 100644 (file)
--- a/riscv/insns/sll.h
+++ b/riscv/insns/sll.h
@@ -1 +1 @@
-RD = sext_xprlen(RS1 << (RS2 & (xprlen-1)));
+WRITE_RD(sext_xprlen(RS1 << (RS2 & (xprlen-1))));

diff --git a/riscv/insns/slli.h b/riscv/insns/slli.h
index 151d97023f8be409106d7679606ec87efbd9eb5b..ff9c8c39bf9d6d3521c11e55bdcd240d1f8e98ad 100644 (file)
--- a/riscv/insns/slli.h
+++ b/riscv/insns/slli.h
@@ -1,8 +1,8 @@
 if(xpr64)
-  RD = RS1 << SHAMT;
+  WRITE_RD(RS1 << SHAMT);
 else
 {
   if(SHAMT & 0x20)
     throw trap_illegal_instruction();
-  RD = sext32(RS1 << SHAMT);
+  WRITE_RD(sext32(RS1 << SHAMT));
 }

diff --git a/riscv/insns/slliw.h b/riscv/insns/slliw.h
index 8ef4ae782fb2b2f67df810ad64437fbbd5af8a1a..fdb51be695fb267cf9a17e41a8116e82581e5a89 100644 (file)
--- a/riscv/insns/slliw.h
+++ b/riscv/insns/slliw.h
@@ -1,2 +1,2 @@
 require_xpr64;
-RD = sext32(RS1 << SHAMT);
+WRITE_RD(sext32(RS1 << SHAMT));

diff --git a/riscv/insns/sllw.h b/riscv/insns/sllw.h
index f3356d89f826b8c0d2a920e08d04be14b831fb13..25e717af502038056ab50919f13107bc9f70cef7 100644 (file)
--- a/riscv/insns/sllw.h
+++ b/riscv/insns/sllw.h
@@ -1,2 +1,2 @@
 require_xpr64;
-RD = sext32(RS1 << (RS2 & 0x1F));
+WRITE_RD(sext32(RS1 << (RS2 & 0x1F)));

diff --git a/riscv/insns/slt.h b/riscv/insns/slt.h
index 5c50534a97b13500dc376a7f86ad14c1115b16c0..dd6e58ec8ea7e7e44a68c8373f7fbc17a3b17063 100644 (file)
--- a/riscv/insns/slt.h
+++ b/riscv/insns/slt.h
@@ -1 +1 @@
-RD = sreg_t(cmp_trunc(RS1)) < sreg_t(cmp_trunc(RS2));
+WRITE_RD(sreg_t(cmp_trunc(RS1)) < sreg_t(cmp_trunc(RS2)));

diff --git a/riscv/insns/slti.h b/riscv/insns/slti.h
index 51873f3b7c0a62d45fd6c483812b5abc8768c501..18d32daed429634c035bc0c27ecf9a05cf739b9a 100644 (file)
--- a/riscv/insns/slti.h
+++ b/riscv/insns/slti.h
@@ -1 +1 @@
-RD = sreg_t(cmp_trunc(RS1)) < sreg_t(cmp_trunc(insn.i_imm()));
+WRITE_RD(sreg_t(cmp_trunc(RS1)) < sreg_t(cmp_trunc(insn.i_imm())));

diff --git a/riscv/insns/sltiu.h b/riscv/insns/sltiu.h
index 924fc929d32ae7c8ffa0d1f9ab5c7bfea6b0e873..ff4eae1586b7ff5d75029472982389e248e7baba 100644 (file)
--- a/riscv/insns/sltiu.h
+++ b/riscv/insns/sltiu.h
@@ -1 +1 @@
-RD = cmp_trunc(RS1) < cmp_trunc(insn.i_imm());
+WRITE_RD(cmp_trunc(RS1) < cmp_trunc(insn.i_imm()));

diff --git a/riscv/insns/sltu.h b/riscv/insns/sltu.h
index 2c5bdc33da9a0fd69e74ecb541509e212a57f763..3a353fd05977de64e8d88e3325ebee6f90b15f45 100644 (file)
--- a/riscv/insns/sltu.h
+++ b/riscv/insns/sltu.h
@@ -1 +1 @@
-RD = cmp_trunc(RS1) < cmp_trunc(RS2);
+WRITE_RD(cmp_trunc(RS1) < cmp_trunc(RS2));

diff --git a/riscv/insns/sra.h b/riscv/insns/sra.h
index 7102da0c0ff46540004ea27aaf250e6c5c045a5d..45c96574f511b35c681c8a2a91597f6cd3c45b02 100644 (file)
--- a/riscv/insns/sra.h
+++ b/riscv/insns/sra.h
@@ -1 +1 @@
-RD = sext_xprlen(sext_xprlen(RS1) >> (RS2 & (xprlen-1)));
+WRITE_RD(sext_xprlen(sext_xprlen(RS1) >> (RS2 & (xprlen-1))));

diff --git a/riscv/insns/srai.h b/riscv/insns/srai.h
index 7360d5fcd6cbb50022cfa2bc2c8acab1c705b5cb..7fdbdf33c8cbcf579c5544aca3b48ed5a5cfd7ce 100644 (file)
--- a/riscv/insns/srai.h
+++ b/riscv/insns/srai.h
@@ -1,8 +1,8 @@
 if(xpr64)
-  RD = sreg_t(RS1) >> SHAMT;
+  WRITE_RD(sreg_t(RS1) >> SHAMT);
 else
 {
   if(SHAMT & 0x20)
     throw trap_illegal_instruction();
-  RD = sext32(int32_t(RS1) >> SHAMT);
+  WRITE_RD(sext32(int32_t(RS1) >> SHAMT));
 }

diff --git a/riscv/insns/sraiw.h b/riscv/insns/sraiw.h
index f43b3fb46fa3e5b62ec0fa738f14f770517450de..242c97eb45ee2be48020896017ed0de6821b55ba 100644 (file)
--- a/riscv/insns/sraiw.h
+++ b/riscv/insns/sraiw.h
@@ -1,2 +1,2 @@
 require_xpr64;
-RD = sext32(int32_t(RS1) >> SHAMT);
+WRITE_RD(sext32(int32_t(RS1) >> SHAMT));

diff --git a/riscv/insns/sraw.h b/riscv/insns/sraw.h
index d1783741bbe19fff75e4fcf68d52b527b04a608c..29640bfb2a6865eff0aa98d50425f2453f7dc563 100644 (file)
--- a/riscv/insns/sraw.h
+++ b/riscv/insns/sraw.h
@@ -1,2 +1,2 @@
 require_xpr64;
-RD = sext32(int32_t(RS1) >> (RS2 & 0x1F));
+WRITE_RD(sext32(int32_t(RS1) >> (RS2 & 0x1F)));

diff --git a/riscv/insns/srl.h b/riscv/insns/srl.h
index 8230d2724b9c1d480c20a38c90dba7cbc7372249..9b1eb2194baf3831b85c04555285917892b2c2f1 100644 (file)
--- a/riscv/insns/srl.h
+++ b/riscv/insns/srl.h
@@ -1,4 +1,4 @@
 if(xpr64)
-  RD = RS1 >> (RS2 & 0x3F);
+  WRITE_RD(RS1 >> (RS2 & 0x3F));
 else
-  RD = sext32((uint32_t)RS1 >> (RS2 & 0x1F));
+  WRITE_RD(sext32((uint32_t)RS1 >> (RS2 & 0x1F)));

diff --git a/riscv/insns/srli.h b/riscv/insns/srli.h
index f5b8c0285bef1a9ae524cb52d7d73ed2654f33a4..fee136c5698f8d7016fc70a884c0a63b970b6c82 100644 (file)
--- a/riscv/insns/srli.h
+++ b/riscv/insns/srli.h
@@ -1,8 +1,8 @@
 if(xpr64)
-  RD = RS1 >> SHAMT;
+  WRITE_RD(RS1 >> SHAMT);
 else
 {
   if(SHAMT & 0x20)
     throw trap_illegal_instruction();
-  RD = sext32((uint32_t)RS1 >> SHAMT);
+  WRITE_RD(sext32((uint32_t)RS1 >> SHAMT));
 }

diff --git a/riscv/insns/srliw.h b/riscv/insns/srliw.h
index 2ee1be0b57e521cb50c3e53c7e01c2acec73055d..0b6f9b833fcc71c3480cd8106b7b4379727f5c37 100644 (file)
--- a/riscv/insns/srliw.h
+++ b/riscv/insns/srliw.h
@@ -1,2 +1,2 @@
 require_xpr64;
-RD = sext32((uint32_t)RS1 >> SHAMT);
+WRITE_RD(sext32((uint32_t)RS1 >> SHAMT));

diff --git a/riscv/insns/srlw.h b/riscv/insns/srlw.h
index b206f7c86a24951364c0d5792f1bd191854ab9e1..21ca5028aa01afcfda686c05d416ee071c703f38 100644 (file)
--- a/riscv/insns/srlw.h
+++ b/riscv/insns/srlw.h
@@ -1,2 +1,2 @@
 require_xpr64;
-RD = sext32((uint32_t)RS1 >> (RS2 & 0x1F));
+WRITE_RD(sext32((uint32_t)RS1 >> (RS2 & 0x1F)));

diff --git a/riscv/insns/sub.h b/riscv/insns/sub.h
index 2b1e0570ad4213cce46ce84a1e78adf849ff7597..95fb83e3340f71beb2ca64115ed14bda85f29ec4 100644 (file)
--- a/riscv/insns/sub.h
+++ b/riscv/insns/sub.h
@@ -1 +1 @@
-RD = sext_xprlen(RS1 - RS2);
+WRITE_RD(sext_xprlen(RS1 - RS2));

diff --git a/riscv/insns/subw.h b/riscv/insns/subw.h
index 28db33481c28eebdd134eb103444432bac483ceb..dce982f9d01866588454bc97b1d1a9f298dc2a50 100644 (file)
--- a/riscv/insns/subw.h
+++ b/riscv/insns/subw.h
@@ -1,3 +1,3 @@
 require_xpr64;
-RD = sext32(RS1 - RS2);
+WRITE_RD(sext32(RS1 - RS2));
 

diff --git a/riscv/insns/xor.h b/riscv/insns/xor.h
index 49b178367e653c92de67124c76cbb748364df7cc..771efa7fa05aa5f7341ba48f6cc66935ec788a5a 100644 (file)
--- a/riscv/insns/xor.h
+++ b/riscv/insns/xor.h
@@ -1 +1 @@
-RD = RS1 ^ RS2;
+WRITE_RD(RS1 ^ RS2);

diff --git a/riscv/insns/xori.h b/riscv/insns/xori.h
index 4eba2334b4f4633b0a9649444aebdbde08a80d7a..33ce6307419d25055922e60bf4da30c89e3de8b3 100644 (file)
--- a/riscv/insns/xori.h
+++ b/riscv/insns/xori.h
@@ -1 +1 @@
-RD = insn.i_imm() ^ RS1;
+WRITE_RD(insn.i_imm() ^ RS1);

diff --git a/riscv/rocc.cc b/riscv/rocc.cc
index 3e8596f0c11ad7b33e46c695e2286a0fc9a45b11..a4766d4c8d41e628429017f2aee4c5817bde0b8d 100644 (file)
--- a/riscv/rocc.cc
+++ b/riscv/rocc.cc
@@ -18,7 +18,7 @@ union rocc_insn_union_t
     reg_t xs2 = u.r.xs1 ? RS2 : -1; \
     reg_t xd = rocc->custom##n(u.r, xs1, xs2); \
     if (u.r.xd) \
-      RD = xd; \
+      WRITE_RD(xd); \
     return pc+4; \
   } \
   \