style: Fix line continuation, especially in debug messages

This patch closes a number of space gaps in debug messages caused by
the incorrect use of line continuation within strings. (There's also
one consistency change to a similar, but correct, use of line
continuation)

diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index 6c1992dd6039040ee8ced98c0fe9fcd0a0e536b5..94a82b9d516cc75cb4b0d266c2a4759076e310bf 100644 (file)
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -1120,8 +1120,8 @@ DataAbort::ec(ThreadContext *tc) const
     if (to64) {
         // AArch64
         if (source == ArmFault::AsynchronousExternalAbort) {
-            panic("Asynchronous External Abort should be handled with \
-                    SystemErrors (SErrors)!");
+            panic("Asynchronous External Abort should be handled with "
+                    "SystemErrors (SErrors)!");
         }
         if (toEL == fromEL)
             return EC_DATA_ABORT_CURR_EL;

diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index 757dac6953ed0c46fb5207fb66e44c4af9d28338..5f9d9b20db73206b7aeec168e54ebd593695256f 100644 (file)
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -1116,8 +1116,8 @@ TableWalker::memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr,
             }
         }
     }
-    DPRINTF(TLBVerbose, "memAttrs: shareable: %d, innerAttrs: %d, \
-            outerAttrs: %d\n",
+    DPRINTF(TLBVerbose, "memAttrs: shareable: %d, innerAttrs: %d, "
+            "outerAttrs: %d\n",
             te.shareable, te.innerAttrs, te.outerAttrs);
     te.setAttributes(false);
 }

diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index 37cf9b14944c8dd3ac5059da75d3c2a2c7f13dcb..ece4e5a1c073f458a91a97d2edbbb3722a30a595 100644 (file)
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -163,7 +163,7 @@ TLB::lookup(Addr va, uint16_t asn, uint8_t vmid, bool hyp, bool secure,
             retval ? retval->pAddr(va) : 0, retval ? retval->ap    : 0,
             retval ? retval->ns        : 0, retval ? retval->nstid : 0,
             retval ? retval->global    : 0, retval ? retval->asid  : 0,
-            retval ? retval->el        : 0, retval ? retval->el    : 0);
+            retval ? retval->el        : 0);
 
     return retval;
 }
@@ -1027,8 +1027,8 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
             temp_te.outerShareable = false;
         }
         temp_te.setAttributes(long_desc_format);
-        DPRINTF(TLBVerbose, "(No MMU) setting memory attributes: shareable:\
-                %d, innerAttrs: %d, outerAttrs: %d, isStage2: %d\n",
+        DPRINTF(TLBVerbose, "(No MMU) setting memory attributes: shareable: "
+                "%d, innerAttrs: %d, outerAttrs: %d, isStage2: %d\n",
                 temp_te.shareable, temp_te.innerAttrs, temp_te.outerAttrs,
                 isStage2);
         setAttr(temp_te.attributes);
@@ -1052,8 +1052,8 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
     if (te != NULL) {
         // Set memory attributes
         DPRINTF(TLBVerbose,
-                "Setting memory attributes: shareable: %d, innerAttrs: %d, \
-                outerAttrs: %d, mtype: %d, isStage2: %d\n",
+                "Setting memory attributes: shareable: %d, innerAttrs: %d, "
+                "outerAttrs: %d, mtype: %d, isStage2: %d\n",
                 te->shareable, te->innerAttrs, te->outerAttrs,
                 static_cast<uint8_t>(te->mtype), isStage2);
         setAttr(te->attributes);

diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc
index b02c0701fe4248d7206d7f42241d14c34486481e..c6dacf9db1a25895ab72d7d26979df5cf2ecc79d 100644 (file)
--- a/src/cpu/checker/cpu.cc
+++ b/src/cpu/checker/cpu.cc
@@ -306,8 +306,8 @@ CheckerCPU::writeMem(uint8_t *data, unsigned size,
 
    if (unverifiedReq && unverifiedMemData &&
        memcmp(data, unverifiedMemData, fullSize) && extraData) {
-           warn("%lli: Store value does not match value sent to memory!\
-                  data: %#x inst_data: %#x", curTick(), data,
+           warn("%lli: Store value does not match value sent to memory! "
+                  "data: %#x inst_data: %#x", curTick(), data,
                   unverifiedMemData);
        handleError();
    }

diff --git a/src/dev/arm/pl111.cc b/src/dev/arm/pl111.cc
index 6abc9b4acf53c4e0517161bfd58891dd2e1715f4..4d1bcba1e548d043da38bc687ec2f7dcd1c699c0 100644 (file)
--- a/src/dev/arm/pl111.cc
+++ b/src/dev/arm/pl111.cc
@@ -196,8 +196,8 @@ Pl111::read(PacketPtr pkt)
             data = lcdPalette[index];
             break;
         } else {
-            panic("Tried to read CLCD register at offset %#x that \
-                       doesn't exist\n", daddr);
+            panic("Tried to read CLCD register at offset %#x that "
+                       "doesn't exist\n", daddr);
             break;
         }
     }
@@ -369,8 +369,8 @@ Pl111::write(PacketPtr pkt)
             lcdPalette[index] = data;
             break;
         } else {
-            panic("Tried to write PL111 register at offset %#x that \
-                       doesn't exist\n", daddr);
+            panic("Tried to write PL111 register at offset %#x that "
+                       "doesn't exist\n", daddr);
             break;
         }
     }

diff --git a/src/dev/ns_gige.cc b/src/dev/ns_gige.cc
index 9a6ea5c6b46640002fa76846868c6f82fccb3680..f180b0ecd08ba8d86f4d721c82c1fa0ce24430b7 100644 (file)
--- a/src/dev/ns_gige.cc
+++ b/src/dev/ns_gige.cc
@@ -732,8 +732,8 @@ NSGigE::write(PacketPtr pkt)
                         = (uint8_t)(reg >> 8);
                     break;
                 }
-                panic("writing RFDR for something other than pattern matching\
-                    or hashing! %#x\n", rfaddr);
+                panic("writing RFDR for something other than pattern matching "
+                    "or hashing! %#x\n", rfaddr);
             }
 
           case BRAR:

diff --git a/src/sim/stat_control.cc b/src/sim/stat_control.cc
index 83089f399e0a66547ad0ca8116dcfcfde80d3134..75e717bfa52055b6e802acb57437fd24d7eea90e 100644 (file)
--- a/src/sim/stat_control.cc
+++ b/src/sim/stat_control.cc
@@ -157,8 +157,8 @@ Global::Global()
     finalTick
         .functor(statFinalTick)
         .name("final_tick")
-        .desc("Number of ticks from beginning of simulation \
-(restored from checkpoints and never reset)")
+        .desc("Number of ticks from beginning of simulation "
+              "(restored from checkpoints and never reset)")
         ;
 
     hostInstRate

diff --git a/src/sim/system.cc b/src/sim/system.cc
index cabb358b33906f907655760a97e92d2a43ccbe0f..fe5be23dc6e4f15a0fbcb6f8f97b8e9fec4cf6bc 100644 (file)
--- a/src/sim/system.cc
+++ b/src/sim/system.cc
@@ -450,9 +450,10 @@ System::getMasterId(std::string master_name)
     // Otherwise objects will have sized their stat buckets and
     // they will be too small
 
-    if (Stats::enabled())
-        fatal("Can't request a masterId after regStats(). \
-                You must do so in init().\n");
+    if (Stats::enabled()) {
+        fatal("Can't request a masterId after regStats(). "
+                "You must do so in init().\n");
+    }
 
     masterIds.push_back(master_name);