add pyrtl pipeline introspection example

diff --git a/3d_gpu/microarchitecture.mdwn b/3d_gpu/microarchitecture.mdwn
index 4cab848e0808bdbe09d85b632026d6ecbc71ee70..de5fc334640d9df71d90246726ce16c7db872769 100644 (file)
--- a/3d_gpu/microarchitecture.mdwn
+++ b/3d_gpu/microarchitecture.mdwn
@@ -111,3 +111,4 @@ called the flip-flops orchestrating the timing "collectors".
 * <https://en.wikipedia.org/wiki/Reservation_station>
 * Register File Bank Cacheing <https://www.princeton.edu/~rblee/ELE572Papers/MultiBankRegFile_ISCA2000.pdf>
 * Discussion <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2018-November/000157.html>
+* <https://github.com/UCSBarchlab/PyRTL/blob/master/examples/example5-instrospection.py>