hdl.dsl: reject name mismatch in `m.domains.<name> +=`.

This would violate invariants later in the elaboration process.

Fixes #282.

diff --git a/nmigen/hdl/dsl.py b/nmigen/hdl/dsl.py
index aaecd9c503f951dd7473025512c17c465a5c29ca..96f19231830ecd59146450190ae083b57ce82b77 100644 (file)
--- a/nmigen/hdl/dsl.py
+++ b/nmigen/hdl/dsl.py
@@ -118,6 +118,10 @@ class _ModuleBuilderDomainSet:
         if not isinstance(domain, ClockDomain):
             raise TypeError("Only clock domains may be added to `m.domains`, not {!r}"
                             .format(domain))
+        if domain.name != name:
+            raise NameError("Clock domain name {!r} must match name in `m.domains.{} += ...` "
+                            "syntax"
+                            .format(domain.name, name))
         self._builder._add_domain(domain)
 
 

diff --git a/nmigen/test/test_hdl_dsl.py b/nmigen/test/test_hdl_dsl.py
index 959c6e506367b27db88a36483863bf54c25c8a09..9b3a91d28696d8a1538dcbe6aac09aef254465b3 100644 (file)
--- a/nmigen/test/test_hdl_dsl.py
+++ b/nmigen/test/test_hdl_dsl.py
@@ -716,6 +716,12 @@ class DSLTestCase(FHDLTestCase):
                 msg="Only clock domains may be added to `m.domains`, not 1"):
             m.domains += 1
 
+    def test_domain_add_wrong_name(self):
+        m = Module()
+        with self.assertRaises(NameError,
+                msg="Clock domain name 'bar' must match name in `m.domains.foo += ...` syntax"):
+            m.domains.foo = ClockDomain("bar")
+
     def test_lower(self):
         m1 = Module()
         m1.d.comb += self.c1.eq(self.s1)