(rest_of_compilation): Call reload_cse_regs here.

From-SVN: r14478

diff --git a/gcc/toplev.c b/gcc/toplev.c
index 4804a11e385275e3d90bf1006d0c32c2c4cb3bfa..8635e81e0297c1dc77c60d2f79d525e89e033bc9 100644 (file)
--- a/gcc/toplev.c
+++ b/gcc/toplev.c
@@ -3349,6 +3349,10 @@ rest_of_compilation (decl)
 
   reload_completed = 1;
 
+  /* Do a very simple CSE pass over just the hard registers.  */
+  if (optimize > 0)
+    reload_cse_regs (insns);
+
   /* On some machines, the prologue and epilogue code, or parts thereof,
      can be represented as RTL.  Doing so lets us schedule insns between
      it and the rest of the code and also allows delayed branch