doh

diff --git a/src/nmigen_gf/hdl/cldivrem.py b/src/nmigen_gf/hdl/cldivrem.py
index 973e0c98cbc332951f4727495a513c79ecf78d25..43257e7888680bafabe36cb7c2d3bf2a786706c5 100644 (file)
--- a/src/nmigen_gf/hdl/cldivrem.py
+++ b/src/nmigen_gf/hdl/cldivrem.py
@@ -98,7 +98,7 @@ class EqualLeadingZeroCount(Elaboratable):
 
         csum = Signal(self.width + 1)
         carry_in = 1  # both have no leading zeros so far, so set carry
-        m.d.comb += sum.eq(addend1 + addend2 + carry_in)
+        m.d.comb += csum.eq(addend1 + addend2 + carry_in)
         m.d.comb += self.out.eq(csum[self.width])  # out is carry-out
         return m