freedreno/a6xx: move tile_mode to sampler-view CSO

This is known when the CSO is created, so no need to patch it in later.

Also, it seems like smaller textures where the first level is small
enough to be linear, it seems like we should set linear tile mode.

See: dEQP-GLES3.functional.texture.format.unsized.rgb_unsigned_byte_3d_pot

Signed-off-by: Rob Clark <robdclark@gmail.com>

diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_emit.c b/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
index 245353ee16279feca77e8a815e5222b8e43cd704..711ff4ac66c33eeef45783911c7c4f82f823f47b 100644 (file)
--- a/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
@@ -394,13 +394,8 @@ fd6_emit_textures(struct fd_pipe *pipe, struct fd_ringbuffer *ring,
                        static const struct fd6_pipe_sampler_view dummy_view = {};
                        const struct fd6_pipe_sampler_view *view = tex->textures[i] ?
                                fd6_pipe_sampler_view(tex->textures[i]) : &dummy_view;
-                       enum a6xx_tile_mode tile_mode = TILE6_LINEAR;
 
-                       if (view->base.texture)
-                               tile_mode = fd_resource(view->base.texture)->tile_mode;
-
-                       OUT_RING(state, view->texconst0 |
-                               A6XX_TEX_CONST_0_TILE_MODE(tile_mode));
+                       OUT_RING(state, view->texconst0);
                        OUT_RING(state, view->texconst1);
                        OUT_RING(state, view->texconst2);
                        OUT_RING(state, view->texconst3);

diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_texture.c b/src/gallium/drivers/freedreno/a6xx/fd6_texture.c
index b9121523b7c85fe047cdd2e778fedaa9efa51aad..e516e94b0d928010287c89859b6d3f7c61da382b 100644 (file)
--- a/src/gallium/drivers/freedreno/a6xx/fd6_texture.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_texture.c
@@ -281,12 +281,17 @@ fd6_sampler_view_create(struct pipe_context *pctx, struct pipe_resource *prsc,
                so->offset = cso->u.buf.offset;
        } else {
                unsigned miplevels;
+               enum a6xx_tile_mode tile_mode = TILE6_LINEAR;
 
                lvl = fd_sampler_first_level(cso);
                miplevels = fd_sampler_last_level(cso) - lvl;
                layers = cso->u.tex.last_layer - cso->u.tex.first_layer + 1;
 
-               so->texconst0 |= A6XX_TEX_CONST_0_MIPLVLS(miplevels);
+               if (!fd_resource_level_linear(prsc, lvl))
+                       tile_mode = fd_resource(prsc)->tile_mode;
+
+               so->texconst0 |= A6XX_TEX_CONST_0_MIPLVLS(miplevels) |
+                       A6XX_TEX_CONST_0_TILE_MODE(tile_mode);
                so->texconst1 =
                        A6XX_TEX_CONST_1_WIDTH(u_minify(prsc->width0, lvl)) |
                        A6XX_TEX_CONST_1_HEIGHT(u_minify(prsc->height0, lvl));