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diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index c57f8e370961efef8a630fbb6930036b4cd081d8..bb163869d2a91965a43e0d7b1f65504ed75c2b88 100644 (file)
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -284,9 +284,12 @@ In SVSTATE, for Single-predication, implementors MUST increment both srcstep and
 dststep can still potentially become different indices.  Only when sz=dz
 is srcstep guaranteed to equal dststep at all times.
 
+Note that in some Mode Formats there is only one flag (zz). This indicates
+that *both* sz *and* dz are set to the same.
+
 Example 1:
 
-* VL=3
+* VL=4
 * mask=0b1101
 * sz=0, dz=1
 
@@ -297,8 +300,43 @@ The following schedule for srcstep and dststep will occur:
 | 0       | 0       | both mask[src=0] and mask[dst=0] are 1 |
 | 1       | 2       | sz=1 but dz=0: dst skips mask[1], src soes not |
 | 2       | 3       | mask[src=2] and mask[dst=3] are 1 |
+| end     | end     | loop has ended because dst reached VL-1 |
+
+Example 2:
+
+* VL=4
+* mask=0b1101
+* sz=1, dz=0
+
+The following schedule for srcstep and dststep will occur:
+
+| srcstep | dststep | comment      |
+| ----    | -----   | --------      |
+| 0       | 0       | both mask[src=0] and mask[dst=0] are 1 |
+| 2       | 1       | sz=0 but dz=1: src skips mask[1], dst does not |
+| 3       | 2       | mask[src=3] and mask[dst=2] are 1 |
+| end     | end     | loop has ended because src reached VL-1 |
+
+In both these examples it is crucial to note that despite there being
+a single predicate mask, with sz and dz being different, srcstep and
+dststep are being requested to react differently.
+
+Example 3:
+
+* VL=4
+* mask=0b1101
+* sz=0, dz=0
+
+The following schedule for srcstep and dststep will occur:
+
+| srcstep | dststep | comment      |
+| ----    | -----   | --------      |
+| 0       | 0       | both mask[src=0] and mask[dst=0] are 1 |
+| 2       | 2       | sz=0 and dz=0: both src and dst skip mask[1] |
+| 3       | 3       | mask[src=3] and mask[dst=3] are 1 |
+| end     | end     | loop has ended because src and dst reached VL-1 |
 
-sz and dz however still interact
+Here, both srcstep and dststep remain in lockstep because sz=dz=1
 
 # Twin Predication