[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be...

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+Date: Thu, 21 May 2020 16:35:52 +0000
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+X-Bugzilla-Severity: enhancement
+X-Bugzilla-Who: lkcl@lkcl.net
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+Message-ID: <bug-336-13-ecAkvrNZKX@https.bugs.libre-soc.org/>
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+Subject: [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA
+ (src1) can be zero
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