--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 23976 # Simulator instruction rate (inst/s)
+host_mem_usage 152688 # Number of bytes of host memory used
+host_seconds 0.24 # Real time elapsed on the host
+host_tick_rate 124659634 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 5656 # Number of instructions simulated
+sim_seconds 0.000029 # Number of seconds simulated
+sim_ticks 29437500 # Number of ticks simulated
+system.cpu.AGEN-Unit.instReqsProcessed 2055 # Number of Instructions Requests that completed in this resource.
+system.cpu.Branch-Predictor.instReqsProcessed 5657 # Number of Instructions Requests that completed in this resource.
+system.cpu.Branch-Predictor.predictedNotTaken 783 # Number of Branches Predicted As Not Taken (False).
+system.cpu.Branch-Predictor.predictedTaken 96 # Number of Branches Predicted As Taken (True).
+system.cpu.Decode-Unit.instReqsProcessed 5657 # Number of Instructions Requests that completed in this resource.
+system.cpu.Execution-Unit.instReqsProcessed 3598 # Number of Instructions Requests that completed in this resource.
+system.cpu.Execution-Unit.predictedNotTakenIncorrect 515 # Number of Branches Incorrectly Predicted As Not Taken).
+system.cpu.Execution-Unit.predictedTakenIncorrect 34 # Number of Branches Incorrectly Predicted As Taken.
+system.cpu.Fetch-Buffer-T0.instReqsProcessed 0 # Number of Instructions Requests that completed in this resource.
+system.cpu.Fetch-Buffer-T0.instsBypassed 0 # Number of Instructions Bypassed.
+system.cpu.Fetch-Buffer-T1.instReqsProcessed 0 # Number of Instructions Requests that completed in this resource.
+system.cpu.Fetch-Buffer-T1.instsBypassed 0 # Number of Instructions Bypassed.
+system.cpu.Fetch-Seq-Unit.instReqsProcessed 11315 # Number of Instructions Requests that completed in this resource.
+system.cpu.Graduation-Unit.instReqsProcessed 5656 # Number of Instructions Requests that completed in this resource.
+system.cpu.Mult-Div-Unit.divInstReqsProcessed 1 # Number of Divide Requests Processed.
+system.cpu.Mult-Div-Unit.instReqsProcessed 8 # Number of Instructions Requests that completed in this resource.
+system.cpu.Mult-Div-Unit.multInstReqsProcessed 3 # Number of Multiply Requests Processed.
+system.cpu.RegFile-Manager.instReqsProcessed 10420 # Number of Instructions Requests that completed in this resource.
+system.cpu.committedInsts 5656 # Number of Instructions Simulated (Per-Thread)
+system.cpu.committedInsts_total 5656 # Number of Instructions Simulated (Total)
+system.cpu.cpi 10.409477 # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi_total 10.409477 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 1131 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 56207.317073 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53207.317073 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 1049 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 4609000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.072502 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 82 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 4363000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.072502 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 82 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 924 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 56554.687500 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53554.687500 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 860 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 3619500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.069264 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 64 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 3427500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.069264 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 64 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 14.568182 # Average number of references to valid blocks.
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 2055 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 56359.589041 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 53359.589041 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 1909 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 8228500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.071046 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 146 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 7790500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.071046 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 146 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses 2055 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 56359.589041 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 53359.589041 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 1909 # number of overall hits
+system.cpu.dcache.overall_miss_latency 8228500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.071046 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 146 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 7790500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.071046 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 146 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.replacements 0 # number of replacements
+system.cpu.dcache.sampled_refs 132 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 84.205216 # Cycle average of tags in use
+system.cpu.dcache.total_refs 1923 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 0 # number of writebacks
+system.cpu.dcache_port.instReqsProcessed 2054 # Number of Instructions Requests that completed in this resource.
+system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.read_accesses 0 # DTB read accesses
+system.cpu.dtb.read_hits 0 # DTB read hits
+system.cpu.dtb.read_misses 0 # DTB read misses
+system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.write_hits 0 # DTB write hits
+system.cpu.dtb.write_misses 0 # DTB write misses
+system.cpu.icache.ReadReq_accesses 5658 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 55772.277228 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 52772.277228 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 5355 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 16899000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.053552 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 303 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency 15990000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.053552 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 303 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 17.673267 # Average number of references to valid blocks.
+system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 5658 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 55772.277228 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 52772.277228 # average overall mshr miss latency
+system.cpu.icache.demand_hits 5355 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 16899000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.053552 # miss rate for demand accesses
+system.cpu.icache.demand_misses 303 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 15990000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.053552 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 303 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses 5658 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 55772.277228 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 52772.277228 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 5355 # number of overall hits
+system.cpu.icache.overall_miss_latency 16899000 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.053552 # miss rate for overall accesses
+system.cpu.icache.overall_misses 303 # number of overall misses
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 15990000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.053552 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 303 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.replacements 13 # number of replacements
+system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 135.958324 # Cycle average of tags in use
+system.cpu.icache.total_refs 5355 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.icache_port.instReqsProcessed 5657 # Number of Instructions Requests that completed in this resource.
+system.cpu.ipc 0.096066 # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.ipc_total 0.096066 # IPC: Total IPC of All Threads
+system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.l2cache.ReadExReq_accesses 50 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52500 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40080 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 2625000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 50 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 2004000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 50 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 385 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 52052.219321 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40026.109661 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 19936000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.994805 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 383 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 15330000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994805 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 383 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 52535.714286 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40071.428571 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 735500 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 561000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 0.005420 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 435 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 52103.926097 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40032.332564 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 22561000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.995402 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 433 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 17334000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.995402 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 433 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses 435 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 52103.926097 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 40032.332564 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 2 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 22561000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.995402 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 433 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 17334000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.995402 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 433 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.replacements 0 # number of replacements
+system.cpu.l2cache.sampled_refs 369 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 183.249501 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 0 # number of writebacks
+system.cpu.numCycles 58876 # number of cpu cycles simulated
+system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread)
+system.cpu.smtCycles 0 # Total number of cycles that the CPU was simultaneous multithreading.(SMT)
+system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
+system.cpu.smt_ipc no_value # IPC: Total SMT-IPC
+system.cpu.threadCycles 58876 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.workload.PROG:num_syscalls 13 # Number of system calls
+
+---------- End Simulation Statistics ----------
projects / gem5.git / commitdiff